[PATCH v2 0/5] Add RZ/G2UL CRU and CSI support

[PATCH v2 0/5] Add RZ/G2UL CRU and CSI support

[Biju Das]

This patch series aims to enable CSI/CRU interface found on RZ/G2UL SMARC
EVK using DT overlay.

v1->v2:
 * Added Ack from Conor Dooley for patch#1.
 * Dropped driver reference from commit description for the binding
   patches.

Biju Das (5):
  media: dt-bindings: renesas,rzg2l-csi2: Document Renesas RZ/G2UL CSI-2
    block
  media: dt-bindings: renesas,rzg2l-cru: Document Renesas RZ/G2UL CRU
    block
  arm64: dts: renesas: r9a07g043u: Add CSI and CRU nodes
  arm64: dts: renesas: rzg2ul-smarc: Enable CRU, CSI support
  arm64: dts: renesas: r9a07g043u11-smarc-cru-csi-ov5645: Reduce I2C
    frequency

 .../bindings/media/renesas,rzg2l-cru.yaml     | 35 ++++++++--
 .../bindings/media/renesas,rzg2l-csi2.yaml    |  1 +
 arch/arm64/boot/dts/renesas/Makefile          |  2 +
 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi   | 69 +++++++++++++++++++
 .../r9a07g043u11-smarc-cru-csi-ov5645.dtso    | 25 +++++++
 5 files changed, 128 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-cru-csi-ov5645.dtso

-- 
2.25.1

[PATCH v2 1/5] media: dt-bindings: renesas,rzg2l-csi2: Document Renesas RZ/G2UL CSI-2 block

[Biju Das]

Document the CSI-2 block which is part of CRU found in Renesas RZ/G2UL
SoC.

The CSI-2 block on the RZ/G2UL SoC is identical to one found on the
RZ/G2L SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
v1->v2:
 * Added Ack from Conor Dooley.
 * Dropped driver reference from commit description.
---
 Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml
index 67eea2ac1d22..7faa12fecd5b 100644
--- a/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml
+++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-csi2.yaml
@@ -19,6 +19,7 @@ properties:
   compatible:
     items:
       - enum:
+          - renesas,r9a07g043-csi2       # RZ/G2UL
           - renesas,r9a07g044-csi2       # RZ/G2{L,LC}
           - renesas,r9a07g054-csi2       # RZ/V2L
       - const: renesas,rzg2l-csi2
-- 
2.25.1

[PATCH v2 2/5] media: dt-bindings: renesas,rzg2l-cru: Document Renesas RZ/G2UL CRU block

[Biju Das]

Document the CRU IP found in Renesas RZ/G2UL SoC.

The CRU block on the RZ/G2UL SoC is identical to one found on the
RZ/G2L SoC, but it does not support parallel input.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * Dropped the description from if/else block.
 * Dropped driver reference from commit description.
---
 .../bindings/media/renesas,rzg2l-cru.yaml     | 35 ++++++++++++++++---
 1 file changed, 31 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
index 1e72b8808d24..bc1245127025 100644
--- a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
+++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
@@ -19,6 +19,7 @@ properties:
   compatible:
     items:
       - enum:
+          - renesas,r9a07g043-cru       # RZ/G2UL
           - renesas,r9a07g044-cru       # RZ/G2{L,LC}
           - renesas,r9a07g054-cru       # RZ/V2L
       - const: renesas,rzg2l-cru
@@ -87,10 +88,6 @@ properties:
           Input port node, describing the Image Processing module connected to the
           CSI-2 receiver.
 
-    required:
-      - port@0
-      - port@1
-
 required:
   - compatible
   - reg
@@ -102,6 +99,36 @@ required:
   - reset-names
   - power-domains
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r9a07g044-cru
+              - renesas,r9a07g054-cru
+    then:
+      properties:
+        ports:
+          required:
+            - port@0
+            - port@1
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r9a07g043-cru
+    then:
+      properties:
+        ports:
+          properties:
+            port@0: false
+
+          required:
+            - port@1
+
 additionalProperties: false
 
 examples:
-- 
2.25.1

Re: [PATCH v2 2/5] media: dt-bindings: renesas,rzg2l-cru: Document Renesas RZ/G2UL CRU block

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2319 bytes --]

On Fri, Jan 26, 2024 at 01:31:13PM +0000, Biju Das wrote:
> Document the CRU IP found in Renesas RZ/G2UL SoC.
> 
> The CRU block on the RZ/G2UL SoC is identical to one found on the
> RZ/G2L SoC, but it does not support parallel input.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> ---
> v1->v2:
>  * Dropped the description from if/else block.
>  * Dropped driver reference from commit description.
> ---
>  .../bindings/media/renesas,rzg2l-cru.yaml     | 35 ++++++++++++++++---
>  1 file changed, 31 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
> index 1e72b8808d24..bc1245127025 100644
> --- a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
> +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
> @@ -19,6 +19,7 @@ properties:
>    compatible:
>      items:
>        - enum:
> +          - renesas,r9a07g043-cru       # RZ/G2UL
>            - renesas,r9a07g044-cru       # RZ/G2{L,LC}
>            - renesas,r9a07g054-cru       # RZ/V2L
>        - const: renesas,rzg2l-cru
> @@ -87,10 +88,6 @@ properties:
>            Input port node, describing the Image Processing module connected to the
>            CSI-2 receiver.
>  
> -    required:
> -      - port@0
> -      - port@1
> -
>  required:
>    - compatible
>    - reg
> @@ -102,6 +99,36 @@ required:
>    - reset-names
>    - power-domains
>  
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - renesas,r9a07g044-cru
> +              - renesas,r9a07g054-cru
> +    then:
> +      properties:
> +        ports:
> +          required:
> +            - port@0
> +            - port@1
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - renesas,r9a07g043-cru
> +    then:
> +      properties:
> +        ports:
> +          properties:
> +            port@0: false
> +
> +          required:
> +            - port@1
> +
>  additionalProperties: false
>  
>  examples:
> -- 
> 2.25.1
> 

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RE: [PATCH v2 5/5] arm64: dts: renesas: r9a07g043u11-smarc-cru-csi-ov5645: Reduce I2C frequency

[Biju Das]

Hi Geert,

> -----Original Message-----
> From: Biju Das
> Sent: Friday, January 26, 2024 3:57 PM
> Subject: RE: [PATCH v2 5/5] arm64: dts: renesas: r9a07g043u11-smarc-cru-
> csi-ov5645: Reduce I2C frequency
> 
> Hi Geert,
> 
> Thanks for the feedback.
> 
> > -----Original Message-----
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > Sent: Friday, January 26, 2024 1:53 PM
> > Subject: Re: [PATCH v2 5/5] arm64: dts: renesas:
> > r9a07g043u11-smarc-cru-
> > csi-ov5645: Reduce I2C frequency
> >
> > Hi Biju,
> >
> > On Fri, Jan 26, 2024 at 2:31 PM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > > Reduce i2c freq from 400->100 kHz on RZ/G2UL SMARC EVK as the
> > > captured image is not proper with the sensor configuration over I2C.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > ---
> > > a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-cru-csi-ov5645.dtso
> > > +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-cru-csi-ov5645.
> > > +++ dt
> > > +++ so
> > > @@ -19,3 +19,7 @@ &ov5645 {
> > >         enable-gpios = <&pinctrl RZG2L_GPIO(4, 4) GPIO_ACTIVE_HIGH>;
> > >         reset-gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>;
> > > };
> > > +
> > > +&i2c0 {
> > > +       clock-frequency = <100000>;
> > > +};
> >
> > Is this a limitation of one of the I2C devices on the bus, or a PCB
> > design issue?
> 
> Currently versa3 clock generator connected to the same bus and it works ok
> with 400kHz clock. Maybe it is stressed not that much compared to OV5645
> sensor configuration.
> 
> At the moment with 400kHz I2C bus clock, Camera capture is not working
> properly on RZ/G2UL, but with same bus frequency the same works fine on
> RZ/{G2L,G2LC,V2L}.
> There may be some hardware differences which is causing this issue.
> 
> >
> > Doesn't this need a Fixes tag?
> 
> I can create a new patch updating bus frequency as 100kHz and add fixes
> tag.
> After this I will drop this patch as it no longer needed.
> 
> Please let me know.

+ media

Adding a delay after Software reset makes it to work at 400kHz with RZ/G2UL SMARC EVK.

So not sure we need to add delay after software reset?

Now after OV5645 gpio reset, then there is 20msec delay and then again
we are issuing software reset and there is no delay after this for this software reset.

diff --git a/drivers/media/i2c/ov5645.c b/drivers/media/i2c/ov5645.c
index a26ac11c989d..d67a5e23fe5a 100644
--- a/drivers/media/i2c/ov5645.c
+++ b/drivers/media/i2c/ov5645.c
@@ -622,11 +622,19 @@ static int ov5645_set_register_array(struct ov5645 *ov5645,
 {
        unsigned int i;
        int ret;

        for (i = 0; i < num_settings; ++i, ++settings) {
                ret = ov5645_write_reg(ov5645, settings->reg, settings->val);
                if (ret < 0)
                        return ret;
+
+               if (settings->reg == OV5645_SYSTEM_CTRL0)
+                       fsleep(1000);

Cheers,
Biju

Re: [PATCH v2 1/5] media: dt-bindings: renesas,rzg2l-csi2: Document Renesas RZ/G2UL CSI-2 block

[Geert Uytterhoeven]

On Fri, Jan 26, 2024 at 2:31 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Document the CSI-2 block which is part of CRU found in Renesas RZ/G2UL
> SoC.
>
> The CSI-2 block on the RZ/G2UL SoC is identical to one found on the
> RZ/G2L SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> v1->v2:
>  * Added Ack from Conor Dooley.
>  * Dropped driver reference from commit description.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 2/5] media: dt-bindings: renesas,rzg2l-cru: Document Renesas RZ/G2UL CRU block

[Geert Uytterhoeven]

On Fri, Jan 26, 2024 at 2:31 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Document the CRU IP found in Renesas RZ/G2UL SoC.
>
> The CRU block on the RZ/G2UL SoC is identical to one found on the
> RZ/G2L SoC, but it does not support parallel input.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
>  * Dropped the description from if/else block.
>  * Dropped driver reference from commit description.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 5/5] arm64: dts: renesas: r9a07g043u11-smarc-cru-csi-ov5645: Reduce I2C frequency

[Biju Das]

Hi Geert,

> -----Original Message-----
> From: Biju Das
> Sent: Tuesday, January 30, 2024 2:15 PM
> Subject: RE: [PATCH v2 5/5] arm64: dts: renesas: r9a07g043u11-smarc-cru-
> csi-ov5645: Reduce I2C frequency
> 
> Hi Geert,
> 
> > -----Original Message-----
> > From: Biju Das
> > Sent: Friday, January 26, 2024 3:57 PM
> > Subject: RE: [PATCH v2 5/5] arm64: dts: renesas:
> > r9a07g043u11-smarc-cru-
> > csi-ov5645: Reduce I2C frequency
> >
> > Hi Geert,
> >
> > Thanks for the feedback.
> >
> > > -----Original Message-----
> > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > Sent: Friday, January 26, 2024 1:53 PM
> > > Subject: Re: [PATCH v2 5/5] arm64: dts: renesas:
> > > r9a07g043u11-smarc-cru-
> > > csi-ov5645: Reduce I2C frequency
> > >
> > > Hi Biju,
> > >
> > > On Fri, Jan 26, 2024 at 2:31 PM Biju Das
> > > <biju.das.jz@bp.renesas.com>
> > > wrote:
> > > > Reduce i2c freq from 400->100 kHz on RZ/G2UL SMARC EVK as the
> > > > captured image is not proper with the sensor configuration over I2C.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > >
> > > Thanks for your patch!
> > >
> > > > ---
> > > > a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-cru-csi-ov5645.dt
> > > > so
> > > > +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-cru-csi-ov5645.
> > > > +++ dt
> > > > +++ so
> > > > @@ -19,3 +19,7 @@ &ov5645 {
> > > >         enable-gpios = <&pinctrl RZG2L_GPIO(4, 4) GPIO_ACTIVE_HIGH>;
> > > >         reset-gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>;
> > > > };
> > > > +
> > > > +&i2c0 {
> > > > +       clock-frequency = <100000>; };
> > >
> > > Is this a limitation of one of the I2C devices on the bus, or a PCB
> > > design issue?
> >
> > Currently versa3 clock generator connected to the same bus and it
> > works ok with 400kHz clock. Maybe it is stressed not that much
> > compared to OV5645 sensor configuration.
> >
> > At the moment with 400kHz I2C bus clock, Camera capture is not working
> > properly on RZ/G2UL, but with same bus frequency the same works fine
> > on RZ/{G2L,G2LC,V2L}.
> > There may be some hardware differences which is causing this issue.
> >
> > >
> > > Doesn't this need a Fixes tag?
> >
> > I can create a new patch updating bus frequency as 100kHz and add
> > fixes tag.
> > After this I will drop this patch as it no longer needed.
> >
> > Please let me know.
> 
> + media
> 
> Adding a delay after Software reset makes it to work at 400kHz with
> RZ/G2UL SMARC EVK.
> 
> So not sure we need to add delay after software reset?
> 
> Now after OV5645 gpio reset, then there is 20msec delay and then again we
> are issuing software reset and there is no delay after this for this
> software reset.
> 
> diff --git a/drivers/media/i2c/ov5645.c b/drivers/media/i2c/ov5645.c index
> a26ac11c989d..d67a5e23fe5a 100644
> --- a/drivers/media/i2c/ov5645.c
> +++ b/drivers/media/i2c/ov5645.c
> @@ -622,11 +622,19 @@ static int ov5645_set_register_array(struct ov5645
> *ov5645,  {
>         unsigned int i;
>         int ret;
> 
>         for (i = 0; i < num_settings; ++i, ++settings) {
>                 ret = ov5645_write_reg(ov5645, settings->reg, settings-
> >val);
>                 if (ret < 0)
>                         return ret;
> +
> +               if (settings->reg == OV5645_SYSTEM_CTRL0)
> +                       fsleep(1000);
> 

This issue seen on RZ/G2L SMARC EVK as well. My testing on G2L family shows
we need to add delay to make OV5645 to work @400kHZ.

I am not sure any one tested OV5645 with I2C bus frequency 400kHz?

Cheers,
Biju

Re: [PATCH v2 5/5] arm64: dts: renesas: r9a07g043u11-smarc-cru-csi-ov5645: Reduce I2C frequency

[Sakari Ailus]

Hi folks,

On Fri, Feb 09, 2024 at 02:36:22PM +0000, Biju Das wrote:
> Hi Geert,
> 
> > -----Original Message-----
> > From: Biju Das
> > Sent: Tuesday, January 30, 2024 2:15 PM
> > Subject: RE: [PATCH v2 5/5] arm64: dts: renesas: r9a07g043u11-smarc-cru-
> > csi-ov5645: Reduce I2C frequency
> > 
> > Hi Geert,
> > 
> > > -----Original Message-----
> > > From: Biju Das
> > > Sent: Friday, January 26, 2024 3:57 PM
> > > Subject: RE: [PATCH v2 5/5] arm64: dts: renesas:
> > > r9a07g043u11-smarc-cru-
> > > csi-ov5645: Reduce I2C frequency
> > >
> > > Hi Geert,
> > >
> > > Thanks for the feedback.
> > >
> > > > -----Original Message-----
> > > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > > Sent: Friday, January 26, 2024 1:53 PM
> > > > Subject: Re: [PATCH v2 5/5] arm64: dts: renesas:
> > > > r9a07g043u11-smarc-cru-
> > > > csi-ov5645: Reduce I2C frequency
> > > >
> > > > Hi Biju,
> > > >
> > > > On Fri, Jan 26, 2024 at 2:31 PM Biju Das
> > > > <biju.das.jz@bp.renesas.com>
> > > > wrote:
> > > > > Reduce i2c freq from 400->100 kHz on RZ/G2UL SMARC EVK as the
> > > > > captured image is not proper with the sensor configuration over I2C.
> > > > >
> > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > >
> > > > Thanks for your patch!
> > > >
> > > > > ---
> > > > > a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-cru-csi-ov5645.dt
> > > > > so
> > > > > +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-cru-csi-ov5645.
> > > > > +++ dt
> > > > > +++ so
> > > > > @@ -19,3 +19,7 @@ &ov5645 {
> > > > >         enable-gpios = <&pinctrl RZG2L_GPIO(4, 4) GPIO_ACTIVE_HIGH>;
> > > > >         reset-gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>;
> > > > > };
> > > > > +
> > > > > +&i2c0 {
> > > > > +       clock-frequency = <100000>; };
> > > >
> > > > Is this a limitation of one of the I2C devices on the bus, or a PCB
> > > > design issue?
> > >
> > > Currently versa3 clock generator connected to the same bus and it
> > > works ok with 400kHz clock. Maybe it is stressed not that much
> > > compared to OV5645 sensor configuration.
> > >
> > > At the moment with 400kHz I2C bus clock, Camera capture is not working
> > > properly on RZ/G2UL, but with same bus frequency the same works fine
> > > on RZ/{G2L,G2LC,V2L}.
> > > There may be some hardware differences which is causing this issue.
> > >
> > > >
> > > > Doesn't this need a Fixes tag?
> > >
> > > I can create a new patch updating bus frequency as 100kHz and add
> > > fixes tag.
> > > After this I will drop this patch as it no longer needed.
> > >
> > > Please let me know.
> > 
> > + media
> > 
> > Adding a delay after Software reset makes it to work at 400kHz with
> > RZ/G2UL SMARC EVK.
> > 
> > So not sure we need to add delay after software reset?
> > 
> > Now after OV5645 gpio reset, then there is 20msec delay and then again we
> > are issuing software reset and there is no delay after this for this
> > software reset.
> > 
> > diff --git a/drivers/media/i2c/ov5645.c b/drivers/media/i2c/ov5645.c index
> > a26ac11c989d..d67a5e23fe5a 100644
> > --- a/drivers/media/i2c/ov5645.c
> > +++ b/drivers/media/i2c/ov5645.c
> > @@ -622,11 +622,19 @@ static int ov5645_set_register_array(struct ov5645
> > *ov5645,  {
> >         unsigned int i;
> >         int ret;
> > 
> >         for (i = 0; i < num_settings; ++i, ++settings) {
> >                 ret = ov5645_write_reg(ov5645, settings->reg, settings-
> > >val);
> >                 if (ret < 0)
> >                         return ret;
> > +
> > +               if (settings->reg == OV5645_SYSTEM_CTRL0)
> > +                       fsleep(1000);
> > 
> 
> This issue seen on RZ/G2L SMARC EVK as well. My testing on G2L family shows
> we need to add delay to make OV5645 to work @400kHZ.

Typically there's a delay before the chip is accessible over I²C after
resetting it. It's a bit open whether this one needs it, very probably it
does. It'd be nicer nonetheless to do this outside the register list and
instead use a separate ov5645_write_reg() call.

Probably the first write is redundant. The second write resets the device.
0x80 should be sufficient value for that.

-- 
Regards,

Sakari Ailus

RE: [PATCH v2 5/5] arm64: dts: renesas: r9a07g043u11-smarc-cru-csi-ov5645: Reduce I2C frequency

[Biju Das]

Hi Sakari Ailus,

> -----Original Message-----
> From: Sakari Ailus <sakari.ailus@linux.intel.com>
> Sent: Friday, February 9, 2024 3:18 PM
> Subject: Re: [PATCH v2 5/5] arm64: dts: renesas: r9a07g043u11-smarc-cru-
> csi-ov5645: Reduce I2C frequency
> 
> Hi folks,
> 
> On Fri, Feb 09, 2024 at 02:36:22PM +0000, Biju Das wrote:
> > Hi Geert,
> >
> > > -----Original Message-----
> > > From: Biju Das
> > > Sent: Tuesday, January 30, 2024 2:15 PM
> > > Subject: RE: [PATCH v2 5/5] arm64: dts: renesas:
> > > r9a07g043u11-smarc-cru-
> > > csi-ov5645: Reduce I2C frequency
> > >
> > > Hi Geert,
> > >
> > > > -----Original Message-----
> > > > From: Biju Das
> > > > Sent: Friday, January 26, 2024 3:57 PM
> > > > Subject: RE: [PATCH v2 5/5] arm64: dts: renesas:
> > > > r9a07g043u11-smarc-cru-
> > > > csi-ov5645: Reduce I2C frequency
> > > >
> > > > Hi Geert,
> > > >
> > > > Thanks for the feedback.
> > > >
> > > > > -----Original Message-----
> > > > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > > > Sent: Friday, January 26, 2024 1:53 PM
> > > > > Subject: Re: [PATCH v2 5/5] arm64: dts: renesas:
> > > > > r9a07g043u11-smarc-cru-
> > > > > csi-ov5645: Reduce I2C frequency
> > > > >
> > > > > Hi Biju,
> > > > >
> > > > > On Fri, Jan 26, 2024 at 2:31 PM Biju Das
> > > > > <biju.das.jz@bp.renesas.com>
> > > > > wrote:
> > > > > > Reduce i2c freq from 400->100 kHz on RZ/G2UL SMARC EVK as the
> > > > > > captured image is not proper with the sensor configuration over
> I2C.
> > > > > >
> > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > >
> > > > > Thanks for your patch!
> > > > >
> > > > > > ---
> > > > > > a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-cru-csi-ov564
> > > > > > 5.dt
> > > > > > so
> > > > > > +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-cru-csi-
> ov5645.
> > > > > > +++ dt
> > > > > > +++ so
> > > > > > @@ -19,3 +19,7 @@ &ov5645 {
> > > > > >         enable-gpios = <&pinctrl RZG2L_GPIO(4, 4)
> GPIO_ACTIVE_HIGH>;
> > > > > >         reset-gpios = <&pinctrl RZG2L_GPIO(0, 1)
> > > > > > GPIO_ACTIVE_LOW>; };
> > > > > > +
> > > > > > +&i2c0 {
> > > > > > +       clock-frequency = <100000>; };
> > > > >
> > > > > Is this a limitation of one of the I2C devices on the bus, or a
> > > > > PCB design issue?
> > > >
> > > > Currently versa3 clock generator connected to the same bus and it
> > > > works ok with 400kHz clock. Maybe it is stressed not that much
> > > > compared to OV5645 sensor configuration.
> > > >
> > > > At the moment with 400kHz I2C bus clock, Camera capture is not
> > > > working properly on RZ/G2UL, but with same bus frequency the same
> > > > works fine on RZ/{G2L,G2LC,V2L}.
> > > > There may be some hardware differences which is causing this issue.
> > > >
> > > > >
> > > > > Doesn't this need a Fixes tag?
> > > >
> > > > I can create a new patch updating bus frequency as 100kHz and add
> > > > fixes tag.
> > > > After this I will drop this patch as it no longer needed.
> > > >
> > > > Please let me know.
> > >
> > > + media
> > >
> > > Adding a delay after Software reset makes it to work at 400kHz with
> > > RZ/G2UL SMARC EVK.
> > >
> > > So not sure we need to add delay after software reset?
> > >
> > > Now after OV5645 gpio reset, then there is 20msec delay and then
> > > again we are issuing software reset and there is no delay after this
> > > for this software reset.
> > >
> > > diff --git a/drivers/media/i2c/ov5645.c b/drivers/media/i2c/ov5645.c
> > > index a26ac11c989d..d67a5e23fe5a 100644
> > > --- a/drivers/media/i2c/ov5645.c
> > > +++ b/drivers/media/i2c/ov5645.c
> > > @@ -622,11 +622,19 @@ static int ov5645_set_register_array(struct
> > > ov5645 *ov5645,  {
> > >         unsigned int i;
> > >         int ret;
> > >
> > >         for (i = 0; i < num_settings; ++i, ++settings) {
> > >                 ret = ov5645_write_reg(ov5645, settings->reg,
> > > settings-
> > > >val);
> > >                 if (ret < 0)
> > >                         return ret;
> > > +
> > > +               if (settings->reg == OV5645_SYSTEM_CTRL0)
> > > +                       fsleep(1000);
> > >
> >
> > This issue seen on RZ/G2L SMARC EVK as well. My testing on G2L family
> > shows we need to add delay to make OV5645 to work @400kHZ.
> 
> Typically there's a delay before the chip is accessible over I²C after
> resetting it. It's a bit open whether this one needs it, very probably it
> does. It'd be nicer nonetheless to do this outside the register list and
> instead use a separate ov5645_write_reg() call.

OK.
> 
> Probably the first write is redundant. The second write resets the device.
> 0x80 should be sufficient value for that.

Will test and send patch for it.

Cheers,
Biju