Re: [PATCH v2 00/77] media: imx: Miscellaneous fixes and cleanups for i.MX7

[Laurent Pinchart <laurent.pinchart@ideasonboard.com>]

Hi Frieder,

On Wed, Mar 17, 2021 at 07:04:19PM +0100, Frieder Schrempf wrote:
> On 15.02.21 05:26, Laurent Pinchart wrote:
> > Hello,
> > 
> > This large patch series is a collection of miscellaneous fixes, cleanups
> > and enhancements for the i.MX7 camera support. Most notably, it
> > implements support for the Media Controller API in the driver.
> > 
> > Compared to v1, review comments have been taken into account, and the
> > patches have been rebased on top of the DT bindings and latest imx
> > changes as present in the linux-media tree. Patches 38/77, 39/77, 60/77
> > and 61/77 are new. For additional information, please see individual
> > patches.
> > 
> > I have successfully tested the code on an i.MX6ULL board (with an
> > MT9M114 sensor), an I.MX7D board (with an IMX296 sensor), and an i.MX8MM
> > board (with an OV5640 sensor, and additional patches for i.MX8MM
> > support).
> 
> First of all, thanks for the great work!

You're welcome.

> I'm currently trying to get a setup with CSI + MIPI + ADV7280 working on 
> an i.MX8MM system. Would you mind sharing the additional patches I need 
> for this?
> 
> I guess you are referring to patches for the MIPI CSIS PHY and the 
> devicetree. Anything else, that I'm missing?

I've pushed my work in progress patches to

	git://linuxtv.org/pinchartl/media.git imx/next

I haven't tested this on mainline though, as the i.MX8MM board I'm using
currently requires an NXP BSP.

For the DT integration, here's what I have in imx8mm.dtsi:

			csi1_bridge: csi1_bridge@32e20000 {
				compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
				reg = <0x32e20000 0x1000>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
					 <&clk IMX8MM_CLK_CSI1_ROOT>,
					 <&clk IMX8MM_CLK_DISP_APB_ROOT>;
				clock-names = "axi", "mclk", "dcic";
				power-domains = <&dispmix_pd>;
				status = "disabled";

				port {
					csi_in: endpoint {
						remote-endpoint = <&mipi_csi_out>;
					};
				};
			};

			mipi_csi: mipi_csi@32e30000 {
				compatible = "fsl,imx8mm-mipi-csi2", "fsl,imx7-mipi-csi2";
				reg = <0x32e30000 0x1000>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clock-frequency = <333000000>;
				clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
					 <&clk IMX8MM_CLK_CSI1_ROOT>,
					 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
					 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
				clock-names = "pclk", "wrap", "phy", "axi";
				power-domains = <&mipi_pd>;

				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
					};

					port@1 {
						reg = <1>;

						mipi_csi_out: endpoint {
							remote-endpoint = <&csi_in>;
						};
					};
				};
			};

Mainline seems to be missing the power domains, so you'll likely have to
sort this out.

-- 
Regards,

Laurent Pinchart