[PATCH 0/3] This patchset adds IR controller driver support for

[PATCH 0/3] This patchset adds IR controller driver support for

[zelong dong]

From: Zelong Dong <zelong.dong@amlogic.com>

Meson IR Controller supports hardware decoder in Meson-S4 and later
SoC. So far, protocol NEC could be decoded by hardware decoder.

Zelong Dong (3):
  media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE
  dt-bindings: media: Add compatible for Meson-S4 IR Controller
  arm64: dts: meson: add IR controller for Meson-S4 SoC

 .../bindings/media/amlogic,meson6-ir.yaml     |   1 +
 .../dts/amlogic/meson-s4-s805x2-aq222.dts     |   6 +
 arch/arm64/boot/dts/amlogic/meson-s4.dtsi     |  15 +
 drivers/media/rc/meson-ir.c                   | 522 +++++++++++++++---
 4 files changed, 473 insertions(+), 71 deletions(-)

-- 
2.35.1

[PATCH 1/3] media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE

[zelong dong]

From: Zelong Dong <zelong.dong@amlogic.com>

Meson IR Controller supports hardware decoder in Meson-S4 and later
SoC. So far, protocol NEC could be decoded by hardware decoder.

Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
---
 drivers/media/rc/meson-ir.c | 522 +++++++++++++++++++++++++++++++-----
 1 file changed, 451 insertions(+), 71 deletions(-)

diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c
index 70322fab34ac..5303e6da5809 100644
--- a/drivers/media/rc/meson-ir.c
+++ b/drivers/media/rc/meson-ir.c
@@ -20,48 +20,196 @@
 
 #define DRIVER_NAME		"meson-ir"
 
-#define IR_DEC_LDR_ACTIVE	0x00
-#define IR_DEC_LDR_IDLE		0x04
-#define IR_DEC_LDR_REPEAT	0x08
-#define IR_DEC_BIT_0		0x0c
-#define IR_DEC_REG0		0x10
-#define IR_DEC_REG0_BASE_TIME	GENMASK(11, 0)
-#define IR_DEC_FRAME		0x14
-#define IR_DEC_STATUS		0x18
-#define IR_DEC_STATUS_PULSE	BIT(8)
-#define IR_DEC_REG1		0x1c
-#define IR_DEC_REG1_TIME_IV	GENMASK(28, 16)
-#define IR_DEC_REG1_ENABLE	BIT(15)
-#define IR_DEC_REG1_MODE	GENMASK(8, 7)
-#define IR_DEC_REG1_IRQSEL	GENMASK(3, 2)
-#define IR_DEC_REG1_RESET	BIT(0)
-/* The following regs are only available on Meson 8b and newer */
-#define IR_DEC_REG2		0x20
-#define IR_DEC_REG2_MODE	GENMASK(3, 0)
-
-#define DEC_MODE_NEC		0x0
-#define DEC_MODE_RAW		0x2
-
-#define IRQSEL_NEC_MODE		0
-#define IRQSEL_RISE_FALL	1
-#define IRQSEL_FALL		2
-#define IRQSEL_RISE		3
-
-#define MESON_RAW_TRATE		10	/* us */
-#define MESON_HW_TRATE		20	/* us */
+#define IR_DEC_LDR_ACTIVE			0x00
+#define IR_DEC_LDR_ACTIVE_MAX			GENMASK(28, 16)
+#define IR_DEC_LDR_ACTIVE_MIN			GENMASK(12, 0)
+#define IR_DEC_LDR_IDLE				0x04
+#define IR_DEC_LDR_IDLE_MAX			GENMASK(28, 16)
+#define IR_DEC_LDR_IDLE_MIN			GENMASK(12, 0)
+#define IR_DEC_LDR_REPEAT			0x08
+#define IR_DEC_LDR_REPEAT_MAX			GENMASK(25, 16)
+#define IR_DEC_LDR_REPEAT_MIN			GENMASK(9, 0)
+#define IR_DEC_BIT_0				0x0c
+#define IR_DEC_BIT_0_MAX			GENMASK(25, 16)
+#define IR_DEC_BIT_0_MIN			GENMASK(9, 0)
+#define IR_DEC_REG0				0x10
+#define IR_DEC_REG0_FILTER			GENMASK(30, 28)
+#define IR_DEC_REG0_FRAME_TIME_MAX		GENMASK(24, 12)
+#define IR_DEC_REG0_BASE_TIME			GENMASK(11, 0)
+#define IR_DEC_FRAME				0x14
+#define IR_DEC_STATUS				0x18
+#define IR_DEC_STATUS_BIT_1_ENABLE		BIT(30)
+#define IR_DEC_STATUS_BIT_1_MAX			GENMASK(29, 20)
+#define IR_DEC_STATUS_BIT_1_MIN			GENMASK(19, 10)
+#define IR_DEC_STATUS_PULSE			BIT(8)
+#define IR_DEC_STATUS_BUSY			BIT(7)
+#define IR_DEC_STATUS_FRAME_STATUS		GENMASK(3, 0)
+#define IR_DEC_REG1				0x1c
+#define IR_DEC_REG1_TIME_IV			GENMASK(28, 16)
+#define IR_DEC_REG1_FRAME_LEN			GENMASK(13, 8)
+#define IR_DEC_REG1_ENABLE			BIT(15)
+#define IR_DEC_REG1_HOLD_CODE			BIT(6)
+#define IR_DEC_REG1_IRQSEL			GENMASK(3, 2)
+#define IR_DEC_REG1_RESET			BIT(0)
+/* Meson 6b uses REG1 to configure IR mode */
+#define IR_DEC_REG1_MODE			GENMASK(8, 7)
+
+/* The following registers are only available on Meson 8b and newer */
+#define IR_DEC_REG2				0x20
+#define IR_DEC_REG2_TICK_MODE			BIT(15)
+#define IR_DEC_REG2_REPEAT_COUNTER		BIT(13)
+#define IR_DEC_REG2_REPEAT_TIME			BIT(12)
+#define IR_DEC_REG2_COMPARE_FRAME		BIT(11)
+#define IR_DEC_REG2_BIT_ORDER			BIT(8)
+/* Meson 8b / GXBB use REG2 to configure IR mode */
+#define IR_DEC_REG2_MODE			GENMASK(3, 0)
+#define IR_DEC_DURATN2				0x24
+#define IR_DEC_DURATN2_MAX			GENMASK(25, 16)
+#define IR_DEC_DURATN2_MIN			GENMASK(9, 0)
+#define IR_DEC_DURATN3				0x28
+#define IR_DEC_DURATN3_MAX			GENMASK(25, 16)
+#define IR_DEC_DURATN3_MIN			GENMASK(9, 0)
+#define IR_DEC_FRAME1				0x2c
+
+#define FRAME_MSB_FIRST				true
+#define FRAME_LSB_FIRST				false
+
+#define DEC_MODE_NEC				0x0
+#define DEC_MODE_RAW				0x2
+#define DEC_MODE_RC6				0x9
+#define DEC_MODE_XMP				0xE
+#define DEC_MODE_UNKNOW				0xFF
+
+#define DEC_STATUS_VALID			BIT(3)
+#define DEC_STATUS_DATA_CODE_ERR		BIT(2)
+#define DEC_STATUS_CUSTOM_CODE_ERR		BIT(1)
+#define DEC_STATUS_REPEAT			BIT(0)
+
+#define IRQSEL_DEC_MODE				0
+#define IRQSEL_RISE_FALL			1
+#define IRQSEL_FALL				2
+#define IRQSEL_RISE				3
+
+#define MESON_RAW_TRATE				10	/* us */
+#define MESON_HW_TRATE				20	/* us */
+
+/**
+ * struct meson_ir_protocol - describe IR Protocol parameter
+ *
+ * @hw_protocol: select IR Protocol from IR Controller
+ * @repeat_counter_enable: enable frame-to-frame time counter, it should work
+ *                         with @repeat_compare_enable to detect the repeat frame
+ * @repeat_check_enable: enable repeat time check for repeat detection
+ * @repeat_compare_enable: enable to compare frame for repeat frame detection.
+ *                         Some IR Protocol send the same data as repeat frame.
+ *                         In this case, it should work with
+ *                         @repeat_counter_enable to detect the repeat frame.
+ * @bit_order: bit order, LSB or MSB
+ * @bit1_match_enable: enable to check bit 1
+ * @hold_code_enable: hold frame code in register IR_DEC_FRAME1, the new one
+ *                    frame code will not be store in IR_DEC_FRAME1.
+ *                    until IR_DEC_FRAME1 has been read
+ * @count_tick_mode: increasing time unit of frame-to-frame time counter.
+ *                   0 = 100us, 1 = 10us
+ * @code_length: length (N-1) of data frame
+ * @frame_time_max: max time for whole frame. Unit: MESON_HW_TRATE
+ * @leader_active_max: max time for NEC/RC6 leader active part. Unit: MESON_HW_TRATE
+ * @leader_active_min: min time for NEC/RC6 leader active part. Unit: MESON_HW_TRATE
+ * @leader_idle_max: max time for NEC/RC6 leader idle part. Unit: MESON_HW_TRATE
+ * @leader_idle_min: min time for NEC/RC6 leader idle part. Unit: MESON_HW_TRATE
+ * @repeat_leader_max: max time for NEC repeat leader idle part. Unit: MESON_HW_TRATE
+ * @repeat_leader_min: min time for NEC repeat leader idle part. Unit: MESON_HW_TRATE
+ * @bit0_max: max time for NEC Logic '0', half of RC6 trailer bit, XMP Logic '00'
+ * @bit0_min: min time for NEC Logic '0', half of RC6 trailer bit, XMP Logic '00'
+ * @bit1_max: max time for NEC Logic '1', whole of RC6 trailer bit, XMP Logic '01'
+ * @bit1_min: min time for NEC Logic '1', whole of RC6 trailer bit, XMP Logic '01'
+ * @duration2_max: max time for half of RC6 normal bit, XMP Logic '10'
+ * @duration2_min: min time for half of RC6 normal bit, XMP Logic '10'
+ * @duration3_max: max time for whole of RC6 normal bit, XMP Logic '11'
+ * @duration3_min: min time for whole of RC6 normal bit, XMP Logic '11'
+ */
+
+struct meson_ir_protocol {
+	u8 hw_protocol;
+	bool repeat_counter_enable;
+	bool repeat_check_enable;
+	bool repeat_compare_enable;
+	bool bit_order;
+	bool bit1_match_enable;
+	bool hold_code_enable;
+	bool count_tick_mode;
+	u8 code_length;
+	u16 frame_time_max;
+	u16 leader_active_max;
+	u16 leader_active_min;
+	u16 leader_idle_max;
+	u16 leader_idle_min;
+	u16 repeat_leader_max;
+	u16 repeat_leader_min;
+	u16 bit0_max;
+	u16 bit0_min;
+	u16 bit1_max;
+	u16 bit1_min;
+	u16 duration2_max;
+	u16 duration2_min;
+	u16 duration3_max;
+	u16 duration3_min;
+};
+
+struct meson_ir_param {
+	bool support_hw_decoder;
+	unsigned int max_register;
+};
 
 struct meson_ir {
+	const struct meson_ir_param *param;
 	struct regmap	*reg;
 	struct rc_dev	*rc;
 	spinlock_t	lock;
 };
 
-static const struct regmap_config meson_ir_regmap_config = {
+static struct regmap_config meson_ir_regmap_config = {
 	.reg_bits = 32,
 	.val_bits = 32,
 	.reg_stride = 4,
 };
 
+static const struct meson_ir_protocol protocol_timings[] = {
+	/* protocol, repeat counter, repeat check, repeat compare, order */
+	{DEC_MODE_NEC, false, false, false, FRAME_LSB_FIRST,
+	/* bit 1 match, hold code, count tick, len, frame time */
+	true, false, false, 32, 4000,
+	/* leader active max/min, leader idle max/min, repeat leader max/min */
+	500, 400, 300, 200, 150, 80,
+	/* bit0 max/min, bit1 max/min, duration2 max/min, duration3 max/min */
+	72, 40, 134, 90, 0, 0, 0, 0}
+};
+
+static void meson_ir_nec_handler(struct meson_ir *ir)
+{
+	u32 code = 0;
+	u32 status = 0;
+	enum rc_proto proto;
+
+	regmap_read(ir->reg, IR_DEC_STATUS, &status);
+
+	if (status & DEC_STATUS_REPEAT) {
+		rc_repeat(ir->rc);
+	} else {
+		regmap_read(ir->reg, IR_DEC_FRAME, &code);
+
+		code = ir_nec_bytes_to_scancode(code, code >> 8,
+						code >> 16, code >> 24, &proto);
+		rc_keydown(ir->rc, proto, code, 0);
+	}
+}
+
+static void meson_ir_hw_handler(struct meson_ir *ir)
+{
+	if (ir->rc->enabled_protocols & RC_PROTO_BIT_NEC)
+		meson_ir_nec_handler(ir);
+}
+
 static irqreturn_t meson_ir_irq(int irqno, void *dev_id)
 {
 	struct meson_ir *ir = dev_id;
@@ -70,22 +218,232 @@ static irqreturn_t meson_ir_irq(int irqno, void *dev_id)
 
 	spin_lock(&ir->lock);
 
-	regmap_read(ir->reg, IR_DEC_REG1, &duration);
-	duration = FIELD_GET(IR_DEC_REG1_TIME_IV, duration);
-	rawir.duration = duration * MESON_RAW_TRATE;
-
 	regmap_read(ir->reg, IR_DEC_STATUS, &status);
-	rawir.pulse = !!(status & IR_DEC_STATUS_PULSE);
 
-	ir_raw_event_store_with_timeout(ir->rc, &rawir);
+	if (ir->rc->driver_type == RC_DRIVER_IR_RAW) {
+		rawir.pulse = !!(status & IR_DEC_STATUS_PULSE);
+
+		regmap_read(ir->reg, IR_DEC_REG1, &duration);
+		duration = FIELD_GET(IR_DEC_REG1_TIME_IV, duration);
+		rawir.duration = duration * MESON_RAW_TRATE;
+
+		ir_raw_event_store_with_timeout(ir->rc, &rawir);
+	} else if (ir->rc->driver_type == RC_DRIVER_SCANCODE) {
+		if (status & DEC_STATUS_VALID)
+			meson_ir_hw_handler(ir);
+	}
 
 	spin_unlock(&ir->lock);
 
 	return IRQ_HANDLED;
 }
 
+static int meson_ir_hw_decoder_init(struct rc_dev *dev, u64 *rc_type)
+{
+	u8 protocol;
+	u32 regval;
+	int i;
+	unsigned long flags;
+	const struct meson_ir_protocol *timings;
+	struct meson_ir *ir = dev->priv;
+
+	if (*rc_type & RC_PROTO_BIT_NEC)
+		protocol = DEC_MODE_NEC;
+	else
+		return 0;
+
+	for (i = 0; i < ARRAY_SIZE(protocol_timings); i++)
+		if (protocol_timings[i].hw_protocol == protocol)
+			break;
+
+	if (i == ARRAY_SIZE(protocol_timings)) {
+		dev_err(&dev->dev, "hw protocol isn't supported: %d\n",
+			protocol);
+		return -EINVAL;
+	}
+	timings = &protocol_timings[i];
+
+	spin_lock_irqsave(&ir->lock, flags);
+
+	/* Clear controller status */
+	regmap_read(ir->reg, IR_DEC_STATUS, &regval);
+	regmap_read(ir->reg, IR_DEC_FRAME, &regval);
+
+	/* Reset ir decoder and disable decoder */
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
+			   IR_DEC_REG1_RESET);
+
+	/* Base time resolution, (19+1)*1us=20us */
+	regval = FIELD_PREP(IR_DEC_REG0_BASE_TIME, MESON_HW_TRATE - 1);
+	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME, regval);
+
+	/* Monitor timing for input filter */
+	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_FILTER,
+			   FIELD_PREP(IR_DEC_REG0_FILTER, 7));
+
+	/* HW protocol */
+	regval = FIELD_PREP(IR_DEC_REG2_MODE, timings->hw_protocol);
+	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE, regval);
+
+	/* Hold frame data until register was read */
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_HOLD_CODE,
+			   timings->hold_code_enable ?
+			   IR_DEC_REG1_HOLD_CODE : 0);
+
+	/* Bit order */
+	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_BIT_ORDER,
+			   timings->bit_order ? IR_DEC_REG2_BIT_ORDER : 0);
+
+	/* Select tick mode */
+	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_TICK_MODE,
+			   timings->count_tick_mode ?
+			   IR_DEC_REG2_TICK_MODE : 0);
+
+	/*
+	 * Some protocols transmit the same data frame as repeat frame
+	 * when the key is pressing. In this case, it could be detected as
+	 * repeat frame if the repeat checker was enabled.
+	 */
+	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_REPEAT_COUNTER,
+			   timings->repeat_counter_enable ?
+			   IR_DEC_REG2_REPEAT_COUNTER : 0);
+	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_REPEAT_TIME,
+			   timings->repeat_check_enable ?
+			   IR_DEC_REG2_REPEAT_TIME : 0);
+	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_COMPARE_FRAME,
+			   timings->repeat_compare_enable ?
+			   IR_DEC_REG2_COMPARE_FRAME : 0);
+
+	/*
+	 * FRAME_TIME_MAX should be larger than the time between
+	 * data frame and repeat frame
+	 */
+	regval = FIELD_PREP(IR_DEC_REG0_FRAME_TIME_MAX,
+			    timings->frame_time_max);
+	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_FRAME_TIME_MAX,
+			   regval);
+
+	/* Length(N-1) of data frame */
+	regval = FIELD_PREP(IR_DEC_REG1_FRAME_LEN, timings->code_length - 1);
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_FRAME_LEN, regval);
+
+	/* Time for leader active part */
+	regval = FIELD_PREP(IR_DEC_LDR_ACTIVE_MAX,
+			    timings->leader_active_max) |
+		 FIELD_PREP(IR_DEC_LDR_ACTIVE_MIN,
+			    timings->leader_active_min);
+	regmap_update_bits(ir->reg, IR_DEC_LDR_ACTIVE, IR_DEC_LDR_ACTIVE_MAX |
+			   IR_DEC_LDR_ACTIVE_MIN, regval);
+
+	/* Time for leader idle part */
+	regval = FIELD_PREP(IR_DEC_LDR_IDLE_MAX, timings->leader_idle_max) |
+		 FIELD_PREP(IR_DEC_LDR_IDLE_MIN, timings->leader_idle_min);
+	regmap_update_bits(ir->reg, IR_DEC_LDR_IDLE,
+			   IR_DEC_LDR_IDLE_MAX | IR_DEC_LDR_IDLE_MIN, regval);
+
+	/* Time for repeat leader idle part */
+	regval = FIELD_PREP(IR_DEC_LDR_REPEAT_MAX, timings->repeat_leader_max) |
+		 FIELD_PREP(IR_DEC_LDR_REPEAT_MIN, timings->repeat_leader_min);
+	regmap_update_bits(ir->reg, IR_DEC_LDR_REPEAT, IR_DEC_LDR_REPEAT_MAX |
+			   IR_DEC_LDR_REPEAT_MIN, regval);
+
+	/*
+	 * NEC: Time for logic '0'
+	 * RC6: Time for half of trailer bit
+	 */
+	regval = FIELD_PREP(IR_DEC_BIT_0_MAX, timings->bit0_max) |
+		 FIELD_PREP(IR_DEC_BIT_0_MIN, timings->bit0_min);
+	regmap_update_bits(ir->reg, IR_DEC_BIT_0,
+			   IR_DEC_BIT_0_MAX | IR_DEC_BIT_0_MIN, regval);
+
+	/*
+	 * NEC: Time for logic '1'
+	 * RC6: Time for whole of trailer bit
+	 */
+	regval = FIELD_PREP(IR_DEC_STATUS_BIT_1_MAX, timings->bit1_max) |
+		 FIELD_PREP(IR_DEC_STATUS_BIT_1_MIN, timings->bit1_min);
+	regmap_update_bits(ir->reg, IR_DEC_STATUS, IR_DEC_STATUS_BIT_1_MAX |
+			   IR_DEC_STATUS_BIT_1_MIN, regval);
+
+	/* Enable to match logic '1' */
+	regmap_update_bits(ir->reg, IR_DEC_STATUS, IR_DEC_STATUS_BIT_1_ENABLE,
+			   timings->bit1_match_enable ?
+			   IR_DEC_STATUS_BIT_1_ENABLE : 0);
+
+	/*
+	 * NEC: Unused
+	 * RC6: Time for halt of logic 0/1
+	 */
+	regval = FIELD_PREP(IR_DEC_DURATN2_MAX, timings->duration2_max) |
+		 FIELD_PREP(IR_DEC_DURATN2_MIN, timings->duration2_min);
+	regmap_update_bits(ir->reg, IR_DEC_DURATN2,
+			   IR_DEC_DURATN2_MAX | IR_DEC_DURATN2_MIN, regval);
+
+	/*
+	 * NEC: Unused
+	 * RC6: Time for whole logic 0/1
+	 */
+	regval = FIELD_PREP(IR_DEC_DURATN3_MAX, timings->duration3_max) |
+		 FIELD_PREP(IR_DEC_DURATN3_MIN, timings->duration3_min);
+	regmap_update_bits(ir->reg, IR_DEC_DURATN3,
+			   IR_DEC_DURATN3_MAX | IR_DEC_DURATN3_MIN, regval);
+
+	/* Reset ir decoder and enable decode */
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
+			   IR_DEC_REG1_RESET);
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
+			   IR_DEC_REG1_ENABLE);
+
+	spin_unlock_irqrestore(&ir->lock, flags);
+
+	dev_info(&dev->dev, "hw decoder init, protocol: %d\n", protocol);
+
+	return 0;
+}
+
+static void meson_ir_sw_decoder_init(struct rc_dev *dev)
+{
+	unsigned long flags;
+	struct meson_ir *ir = dev->priv;
+
+	spin_lock_irqsave(&ir->lock, flags);
+
+	/* Reset the decoder */
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
+			   IR_DEC_REG1_RESET);
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
+
+	/* Set general operation mode (= raw/software decoding) */
+	if (of_device_is_compatible(dev->dev.of_node, "amlogic,meson6-ir"))
+		regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE,
+				   FIELD_PREP(IR_DEC_REG1_MODE,
+					      DEC_MODE_RAW));
+	else
+		regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE,
+				   FIELD_PREP(IR_DEC_REG2_MODE,
+					      DEC_MODE_RAW));
+
+	/* Set rate */
+	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
+			   FIELD_PREP(IR_DEC_REG0_BASE_TIME,
+				      MESON_RAW_TRATE - 1));
+	/* IRQ on rising and falling edges */
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_IRQSEL,
+			   FIELD_PREP(IR_DEC_REG1_IRQSEL, IRQSEL_RISE_FALL));
+	/* Enable the decoder */
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
+			   IR_DEC_REG1_ENABLE);
+
+	spin_unlock_irqrestore(&ir->lock, flags);
+
+	dev_info(&dev->dev, "sw decoder init\n");
+}
+
 static int meson_ir_probe(struct platform_device *pdev)
 {
+	const struct meson_ir_param *match_data;
 	struct device *dev = &pdev->dev;
 	struct device_node *node = dev->of_node;
 	void __iomem *res_start;
@@ -97,10 +455,17 @@ static int meson_ir_probe(struct platform_device *pdev)
 	if (!ir)
 		return -ENOMEM;
 
+	match_data = of_device_get_match_data(dev);
+	if (!match_data)
+		return dev_err_probe(dev, -ENODEV, "failed to get match data\n");
+
+	ir->param = match_data;
+
 	res_start = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(res_start))
 		return PTR_ERR(res_start);
 
+	meson_ir_regmap_config.max_register = ir->param->max_register;
 	ir->reg = devm_regmap_init_mmio(&pdev->dev, res_start,
 					&meson_ir_regmap_config);
 	if (IS_ERR(ir->reg))
@@ -110,23 +475,34 @@ static int meson_ir_probe(struct platform_device *pdev)
 	if (irq < 0)
 		return irq;
 
-	ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
+	if (ir->param->support_hw_decoder)
+		ir->rc = devm_rc_allocate_device(&pdev->dev,
+						 RC_DRIVER_SCANCODE);
+	else
+		ir->rc = devm_rc_allocate_device(&pdev->dev, RC_DRIVER_IR_RAW);
+
 	if (!ir->rc) {
 		dev_err(dev, "failed to allocate rc device\n");
 		return -ENOMEM;
 	}
 
+	if (ir->rc->driver_type == RC_DRIVER_IR_RAW) {
+		ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
+		ir->rc->rx_resolution = MESON_RAW_TRATE;
+		ir->rc->min_timeout = 1;
+		ir->rc->timeout = IR_DEFAULT_TIMEOUT;
+		ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
+	} else if (ir->rc->driver_type == RC_DRIVER_SCANCODE) {
+		ir->rc->allowed_protocols = RC_PROTO_BIT_NEC;
+		ir->rc->change_protocol = meson_ir_hw_decoder_init;
+	}
+
 	ir->rc->priv = ir;
 	ir->rc->device_name = DRIVER_NAME;
 	ir->rc->input_phys = DRIVER_NAME "/input0";
 	ir->rc->input_id.bustype = BUS_HOST;
 	map_name = of_get_property(node, "linux,rc-map-name", NULL);
 	ir->rc->map_name = map_name ? map_name : RC_MAP_EMPTY;
-	ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
-	ir->rc->rx_resolution = MESON_RAW_TRATE;
-	ir->rc->min_timeout = 1;
-	ir->rc->timeout = IR_DEFAULT_TIMEOUT;
-	ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
 	ir->rc->driver_name = DRIVER_NAME;
 
 	spin_lock_init(&ir->lock);
@@ -138,36 +514,15 @@ static int meson_ir_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	ret = devm_request_irq(dev, irq, meson_ir_irq, 0, NULL, ir);
+	if (ir->rc->driver_type == RC_DRIVER_IR_RAW)
+		meson_ir_sw_decoder_init(ir->rc);
+
+	ret = devm_request_irq(dev, irq, meson_ir_irq, 0, "meson_ir", ir);
 	if (ret) {
 		dev_err(dev, "failed to request irq\n");
 		return ret;
 	}
 
-	/* Reset the decoder */
-	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
-			   IR_DEC_REG1_RESET);
-	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
-
-	/* Set general operation mode (= raw/software decoding) */
-	if (of_device_is_compatible(node, "amlogic,meson6-ir"))
-		regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE,
-				   FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_RAW));
-	else
-		regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE,
-				   FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_RAW));
-
-	/* Set rate */
-	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
-			   FIELD_PREP(IR_DEC_REG0_BASE_TIME,
-				      MESON_RAW_TRATE - 1));
-	/* IRQ on rising and falling edges */
-	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_IRQSEL,
-			   FIELD_PREP(IR_DEC_REG1_IRQSEL, IRQSEL_RISE_FALL));
-	/* Enable the decoder */
-	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
-			   IR_DEC_REG1_ENABLE);
-
 	dev_info(dev, "receiver initialized\n");
 
 	return 0;
@@ -212,11 +567,36 @@ static void meson_ir_shutdown(struct platform_device *pdev)
 	spin_unlock_irqrestore(&ir->lock, flags);
 }
 
+static const struct meson_ir_param meson6_ir_param = {
+	.support_hw_decoder = false,
+	.max_register = IR_DEC_REG1,
+};
+
+static const struct meson_ir_param meson8b_ir_param = {
+	.support_hw_decoder = false,
+	.max_register = IR_DEC_REG2,
+};
+
+static const struct meson_ir_param meson_s4_ir_param = {
+	.support_hw_decoder = true,
+	.max_register = IR_DEC_FRAME1,
+};
+
 static const struct of_device_id meson_ir_match[] = {
-	{ .compatible = "amlogic,meson6-ir" },
-	{ .compatible = "amlogic,meson8b-ir" },
-	{ .compatible = "amlogic,meson-gxbb-ir" },
-	{ },
+	{
+		.compatible = "amlogic,meson6-ir",
+		.data = &meson6_ir_param,
+	}, {
+		.compatible = "amlogic,meson8b-ir",
+		.data = &meson8b_ir_param,
+	}, {
+		.compatible = "amlogic,meson-gxbb-ir",
+		.data = &meson8b_ir_param,
+	}, {
+		.compatible = "amlogic,meson-s4-ir",
+		.data = &meson_s4_ir_param,
+	},
+	{},
 };
 MODULE_DEVICE_TABLE(of, meson_ir_match);
 
-- 
2.35.1

[PATCH 2/3] dt-bindings: media: Add compatible for Meson-S4 IR Controller

[zelong dong]

From: Zelong Dong <zelong.dong@amlogic.com>

Add new compatible for Amlogic's Meson-S4 IR Controller.
Meson IR Controller supports hardware decoder in Meson-S4 and later SoC.

Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
---
 Documentation/devicetree/bindings/media/amlogic,meson6-ir.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/amlogic,meson6-ir.yaml b/Documentation/devicetree/bindings/media/amlogic,meson6-ir.yaml
index 3f9fa92703bb..0f95fe8dd9ac 100644
--- a/Documentation/devicetree/bindings/media/amlogic,meson6-ir.yaml
+++ b/Documentation/devicetree/bindings/media/amlogic,meson6-ir.yaml
@@ -19,6 +19,7 @@ properties:
           - amlogic,meson6-ir
           - amlogic,meson8b-ir
           - amlogic,meson-gxbb-ir
+          - amlogic,meson-s4-ir
       - items:
           - const: amlogic,meson-gx-ir
           - const: amlogic,meson-gxbb-ir
-- 
2.35.1

[PATCH 3/3] arm64: dts: meson: add IR controller for Meson-S4 SoC

[zelong dong]

From: Zelong Dong <zelong.dong@amlogic.com>

Add the IR controller device of Meson-S4 SoC family.

Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
---
 .../boot/dts/amlogic/meson-s4-s805x2-aq222.dts    |  6 ++++++
 arch/arm64/boot/dts/amlogic/meson-s4.dtsi         | 15 +++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
index 8ffbcb2b1ac5..c1f322c73982 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
@@ -28,3 +28,9 @@ memory@0 {
 &uart_B {
 	status = "okay";
 };
+
+&ir {
+	status = "okay";
+	pinctrl-0 = <&remote_pins>;
+	pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index f24460186d3d..5a3abcc08ee5 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -106,6 +106,14 @@ gpio: bank@4000 {
 					#gpio-cells = <2>;
 					gpio-ranges = <&periphs_pinctrl 0 0 82>;
 				};
+
+				remote_pins: remote-pin {
+					mux {
+						groups = "remote_in";
+						function = "remote_in";
+						bias-disable;
+					};
+				};
 			};
 
 			gpio_intc: interrupt-controller@4080 {
@@ -133,6 +141,13 @@ reset: reset-controller@2000 {
 				reg = <0x0 0x2000 0x0 0x98>;
 				#reset-cells = <1>;
 			};
+
+			ir: ir@84040 {
+				compatible = "amlogic,meson-s4-ir";
+				reg = <0x0 0x84040 0x0 0x30>;
+				interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
+				status = "disabled";
+			};
 		};
 	};
 };
-- 
2.35.1

Re: [PATCH 2/3] dt-bindings: media: Add compatible for Meson-S4 IR Controller

[Krzysztof Kozlowski]

On 25/08/2023 13:53, zelong dong wrote:
> From: Zelong Dong <zelong.dong@amlogic.com>
> 
> Add new compatible for Amlogic's Meson-S4 IR Controller.
> Meson IR Controller supports hardware decoder in Meson-S4 and later SoC.
> 
> Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
> ---

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 3/3] arm64: dts: meson: add IR controller for Meson-S4 SoC

[Neil Armstrong]

On 25/08/2023 13:53, zelong dong wrote:
> From: Zelong Dong <zelong.dong@amlogic.com>
> 
> Add the IR controller device of Meson-S4 SoC family.
> 
> Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
> ---
>   .../boot/dts/amlogic/meson-s4-s805x2-aq222.dts    |  6 ++++++
>   arch/arm64/boot/dts/amlogic/meson-s4.dtsi         | 15 +++++++++++++++
>   2 files changed, 21 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
> index 8ffbcb2b1ac5..c1f322c73982 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
> @@ -28,3 +28,9 @@ memory@0 {
>   &uart_B {
>   	status = "okay";
>   };
> +
> +&ir {
> +	status = "okay";
> +	pinctrl-0 = <&remote_pins>;
> +	pinctrl-names = "default";
> +};
> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
> index f24460186d3d..5a3abcc08ee5 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
> @@ -106,6 +106,14 @@ gpio: bank@4000 {
>   					#gpio-cells = <2>;
>   					gpio-ranges = <&periphs_pinctrl 0 0 82>;
>   				};
> +
> +				remote_pins: remote-pin {
> +					mux {
> +						groups = "remote_in";
> +						function = "remote_in";
> +						bias-disable;
> +					};
> +				};
>   			};
>   
>   			gpio_intc: interrupt-controller@4080 {
> @@ -133,6 +141,13 @@ reset: reset-controller@2000 {
>   				reg = <0x0 0x2000 0x0 0x98>;
>   				#reset-cells = <1>;
>   			};
> +
> +			ir: ir@84040 {
> +				compatible = "amlogic,meson-s4-ir";
> +				reg = <0x0 0x84040 0x0 0x30>;
> +				interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
> +				status = "disabled";
> +			};
>   		};
>   	};
>   };

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Re: [PATCH 1/3] media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE

[Neil Armstrong]

On 25/08/2023 13:53, zelong dong wrote:
> From: Zelong Dong <zelong.dong@amlogic.com>
> 
> Meson IR Controller supports hardware decoder in Meson-S4 and later
> SoC. So far, protocol NEC could be decoded by hardware decoder.
> 
> Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
> ---
>   drivers/media/rc/meson-ir.c | 522 +++++++++++++++++++++++++++++++-----
>   1 file changed, 451 insertions(+), 71 deletions(-)
> 

<snip>

It looks pretty good now, so far I'm ok with it:

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

I think some test reports would be needed to be sure it doesn't regress existing HW.

Thanks,
Neil

Re: [PATCH 1/3] media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE

[Sean Young]

On Fri, Aug 25, 2023 at 07:53:08PM +0800, zelong dong wrote:
> From: Zelong Dong <zelong.dong@amlogic.com>
> 
> Meson IR Controller supports hardware decoder in Meson-S4 and later
> SoC. So far, protocol NEC could be decoded by hardware decoder.

On Meson-S4, only the hardware decoder for NEC can be used using this
driver. Does the Meson-S4 hardware support software decoding? If
software decoding could be used, then any protocol could be supported,
not just NEC.

Also, out of interest, is there are documentation available for this
hardware?

Thanks,

Sean

> 
> Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
> ---
>  drivers/media/rc/meson-ir.c | 522 +++++++++++++++++++++++++++++++-----
>  1 file changed, 451 insertions(+), 71 deletions(-)
> 
> diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c
> index 70322fab34ac..5303e6da5809 100644
> --- a/drivers/media/rc/meson-ir.c
> +++ b/drivers/media/rc/meson-ir.c
> @@ -20,48 +20,196 @@
>  
>  #define DRIVER_NAME		"meson-ir"
>  
> -#define IR_DEC_LDR_ACTIVE	0x00
> -#define IR_DEC_LDR_IDLE		0x04
> -#define IR_DEC_LDR_REPEAT	0x08
> -#define IR_DEC_BIT_0		0x0c
> -#define IR_DEC_REG0		0x10
> -#define IR_DEC_REG0_BASE_TIME	GENMASK(11, 0)
> -#define IR_DEC_FRAME		0x14
> -#define IR_DEC_STATUS		0x18
> -#define IR_DEC_STATUS_PULSE	BIT(8)
> -#define IR_DEC_REG1		0x1c
> -#define IR_DEC_REG1_TIME_IV	GENMASK(28, 16)
> -#define IR_DEC_REG1_ENABLE	BIT(15)
> -#define IR_DEC_REG1_MODE	GENMASK(8, 7)
> -#define IR_DEC_REG1_IRQSEL	GENMASK(3, 2)
> -#define IR_DEC_REG1_RESET	BIT(0)
> -/* The following regs are only available on Meson 8b and newer */
> -#define IR_DEC_REG2		0x20
> -#define IR_DEC_REG2_MODE	GENMASK(3, 0)
> -
> -#define DEC_MODE_NEC		0x0
> -#define DEC_MODE_RAW		0x2
> -
> -#define IRQSEL_NEC_MODE		0
> -#define IRQSEL_RISE_FALL	1
> -#define IRQSEL_FALL		2
> -#define IRQSEL_RISE		3
> -
> -#define MESON_RAW_TRATE		10	/* us */
> -#define MESON_HW_TRATE		20	/* us */
> +#define IR_DEC_LDR_ACTIVE			0x00
> +#define IR_DEC_LDR_ACTIVE_MAX			GENMASK(28, 16)
> +#define IR_DEC_LDR_ACTIVE_MIN			GENMASK(12, 0)
> +#define IR_DEC_LDR_IDLE				0x04
> +#define IR_DEC_LDR_IDLE_MAX			GENMASK(28, 16)
> +#define IR_DEC_LDR_IDLE_MIN			GENMASK(12, 0)
> +#define IR_DEC_LDR_REPEAT			0x08
> +#define IR_DEC_LDR_REPEAT_MAX			GENMASK(25, 16)
> +#define IR_DEC_LDR_REPEAT_MIN			GENMASK(9, 0)
> +#define IR_DEC_BIT_0				0x0c
> +#define IR_DEC_BIT_0_MAX			GENMASK(25, 16)
> +#define IR_DEC_BIT_0_MIN			GENMASK(9, 0)
> +#define IR_DEC_REG0				0x10
> +#define IR_DEC_REG0_FILTER			GENMASK(30, 28)
> +#define IR_DEC_REG0_FRAME_TIME_MAX		GENMASK(24, 12)
> +#define IR_DEC_REG0_BASE_TIME			GENMASK(11, 0)
> +#define IR_DEC_FRAME				0x14
> +#define IR_DEC_STATUS				0x18
> +#define IR_DEC_STATUS_BIT_1_ENABLE		BIT(30)
> +#define IR_DEC_STATUS_BIT_1_MAX			GENMASK(29, 20)
> +#define IR_DEC_STATUS_BIT_1_MIN			GENMASK(19, 10)
> +#define IR_DEC_STATUS_PULSE			BIT(8)
> +#define IR_DEC_STATUS_BUSY			BIT(7)
> +#define IR_DEC_STATUS_FRAME_STATUS		GENMASK(3, 0)
> +#define IR_DEC_REG1				0x1c
> +#define IR_DEC_REG1_TIME_IV			GENMASK(28, 16)
> +#define IR_DEC_REG1_FRAME_LEN			GENMASK(13, 8)
> +#define IR_DEC_REG1_ENABLE			BIT(15)
> +#define IR_DEC_REG1_HOLD_CODE			BIT(6)
> +#define IR_DEC_REG1_IRQSEL			GENMASK(3, 2)
> +#define IR_DEC_REG1_RESET			BIT(0)
> +/* Meson 6b uses REG1 to configure IR mode */
> +#define IR_DEC_REG1_MODE			GENMASK(8, 7)
> +
> +/* The following registers are only available on Meson 8b and newer */
> +#define IR_DEC_REG2				0x20
> +#define IR_DEC_REG2_TICK_MODE			BIT(15)
> +#define IR_DEC_REG2_REPEAT_COUNTER		BIT(13)
> +#define IR_DEC_REG2_REPEAT_TIME			BIT(12)
> +#define IR_DEC_REG2_COMPARE_FRAME		BIT(11)
> +#define IR_DEC_REG2_BIT_ORDER			BIT(8)
> +/* Meson 8b / GXBB use REG2 to configure IR mode */
> +#define IR_DEC_REG2_MODE			GENMASK(3, 0)
> +#define IR_DEC_DURATN2				0x24
> +#define IR_DEC_DURATN2_MAX			GENMASK(25, 16)
> +#define IR_DEC_DURATN2_MIN			GENMASK(9, 0)
> +#define IR_DEC_DURATN3				0x28
> +#define IR_DEC_DURATN3_MAX			GENMASK(25, 16)
> +#define IR_DEC_DURATN3_MIN			GENMASK(9, 0)
> +#define IR_DEC_FRAME1				0x2c
> +
> +#define FRAME_MSB_FIRST				true
> +#define FRAME_LSB_FIRST				false
> +
> +#define DEC_MODE_NEC				0x0
> +#define DEC_MODE_RAW				0x2
> +#define DEC_MODE_RC6				0x9
> +#define DEC_MODE_XMP				0xE
> +#define DEC_MODE_UNKNOW				0xFF
> +
> +#define DEC_STATUS_VALID			BIT(3)
> +#define DEC_STATUS_DATA_CODE_ERR		BIT(2)
> +#define DEC_STATUS_CUSTOM_CODE_ERR		BIT(1)
> +#define DEC_STATUS_REPEAT			BIT(0)
> +
> +#define IRQSEL_DEC_MODE				0
> +#define IRQSEL_RISE_FALL			1
> +#define IRQSEL_FALL				2
> +#define IRQSEL_RISE				3
> +
> +#define MESON_RAW_TRATE				10	/* us */
> +#define MESON_HW_TRATE				20	/* us */
> +
> +/**
> + * struct meson_ir_protocol - describe IR Protocol parameter
> + *
> + * @hw_protocol: select IR Protocol from IR Controller
> + * @repeat_counter_enable: enable frame-to-frame time counter, it should work
> + *                         with @repeat_compare_enable to detect the repeat frame
> + * @repeat_check_enable: enable repeat time check for repeat detection
> + * @repeat_compare_enable: enable to compare frame for repeat frame detection.
> + *                         Some IR Protocol send the same data as repeat frame.
> + *                         In this case, it should work with
> + *                         @repeat_counter_enable to detect the repeat frame.
> + * @bit_order: bit order, LSB or MSB
> + * @bit1_match_enable: enable to check bit 1
> + * @hold_code_enable: hold frame code in register IR_DEC_FRAME1, the new one
> + *                    frame code will not be store in IR_DEC_FRAME1.
> + *                    until IR_DEC_FRAME1 has been read
> + * @count_tick_mode: increasing time unit of frame-to-frame time counter.
> + *                   0 = 100us, 1 = 10us
> + * @code_length: length (N-1) of data frame
> + * @frame_time_max: max time for whole frame. Unit: MESON_HW_TRATE
> + * @leader_active_max: max time for NEC/RC6 leader active part. Unit: MESON_HW_TRATE
> + * @leader_active_min: min time for NEC/RC6 leader active part. Unit: MESON_HW_TRATE
> + * @leader_idle_max: max time for NEC/RC6 leader idle part. Unit: MESON_HW_TRATE
> + * @leader_idle_min: min time for NEC/RC6 leader idle part. Unit: MESON_HW_TRATE
> + * @repeat_leader_max: max time for NEC repeat leader idle part. Unit: MESON_HW_TRATE
> + * @repeat_leader_min: min time for NEC repeat leader idle part. Unit: MESON_HW_TRATE
> + * @bit0_max: max time for NEC Logic '0', half of RC6 trailer bit, XMP Logic '00'
> + * @bit0_min: min time for NEC Logic '0', half of RC6 trailer bit, XMP Logic '00'
> + * @bit1_max: max time for NEC Logic '1', whole of RC6 trailer bit, XMP Logic '01'
> + * @bit1_min: min time for NEC Logic '1', whole of RC6 trailer bit, XMP Logic '01'
> + * @duration2_max: max time for half of RC6 normal bit, XMP Logic '10'
> + * @duration2_min: min time for half of RC6 normal bit, XMP Logic '10'
> + * @duration3_max: max time for whole of RC6 normal bit, XMP Logic '11'
> + * @duration3_min: min time for whole of RC6 normal bit, XMP Logic '11'
> + */
> +
> +struct meson_ir_protocol {
> +	u8 hw_protocol;
> +	bool repeat_counter_enable;
> +	bool repeat_check_enable;
> +	bool repeat_compare_enable;
> +	bool bit_order;
> +	bool bit1_match_enable;
> +	bool hold_code_enable;
> +	bool count_tick_mode;
> +	u8 code_length;
> +	u16 frame_time_max;
> +	u16 leader_active_max;
> +	u16 leader_active_min;
> +	u16 leader_idle_max;
> +	u16 leader_idle_min;
> +	u16 repeat_leader_max;
> +	u16 repeat_leader_min;
> +	u16 bit0_max;
> +	u16 bit0_min;
> +	u16 bit1_max;
> +	u16 bit1_min;
> +	u16 duration2_max;
> +	u16 duration2_min;
> +	u16 duration3_max;
> +	u16 duration3_min;
> +};
> +
> +struct meson_ir_param {
> +	bool support_hw_decoder;
> +	unsigned int max_register;
> +};
>  
>  struct meson_ir {
> +	const struct meson_ir_param *param;
>  	struct regmap	*reg;
>  	struct rc_dev	*rc;
>  	spinlock_t	lock;
>  };
>  
> -static const struct regmap_config meson_ir_regmap_config = {
> +static struct regmap_config meson_ir_regmap_config = {
>  	.reg_bits = 32,
>  	.val_bits = 32,
>  	.reg_stride = 4,
>  };
>  
> +static const struct meson_ir_protocol protocol_timings[] = {
> +	/* protocol, repeat counter, repeat check, repeat compare, order */
> +	{DEC_MODE_NEC, false, false, false, FRAME_LSB_FIRST,
> +	/* bit 1 match, hold code, count tick, len, frame time */
> +	true, false, false, 32, 4000,
> +	/* leader active max/min, leader idle max/min, repeat leader max/min */
> +	500, 400, 300, 200, 150, 80,
> +	/* bit0 max/min, bit1 max/min, duration2 max/min, duration3 max/min */
> +	72, 40, 134, 90, 0, 0, 0, 0}
> +};
> +
> +static void meson_ir_nec_handler(struct meson_ir *ir)
> +{
> +	u32 code = 0;
> +	u32 status = 0;
> +	enum rc_proto proto;
> +
> +	regmap_read(ir->reg, IR_DEC_STATUS, &status);
> +
> +	if (status & DEC_STATUS_REPEAT) {
> +		rc_repeat(ir->rc);
> +	} else {
> +		regmap_read(ir->reg, IR_DEC_FRAME, &code);
> +
> +		code = ir_nec_bytes_to_scancode(code, code >> 8,
> +						code >> 16, code >> 24, &proto);
> +		rc_keydown(ir->rc, proto, code, 0);
> +	}
> +}
> +
> +static void meson_ir_hw_handler(struct meson_ir *ir)
> +{
> +	if (ir->rc->enabled_protocols & RC_PROTO_BIT_NEC)
> +		meson_ir_nec_handler(ir);
> +}
> +
>  static irqreturn_t meson_ir_irq(int irqno, void *dev_id)
>  {
>  	struct meson_ir *ir = dev_id;
> @@ -70,22 +218,232 @@ static irqreturn_t meson_ir_irq(int irqno, void *dev_id)
>  
>  	spin_lock(&ir->lock);
>  
> -	regmap_read(ir->reg, IR_DEC_REG1, &duration);
> -	duration = FIELD_GET(IR_DEC_REG1_TIME_IV, duration);
> -	rawir.duration = duration * MESON_RAW_TRATE;
> -
>  	regmap_read(ir->reg, IR_DEC_STATUS, &status);
> -	rawir.pulse = !!(status & IR_DEC_STATUS_PULSE);
>  
> -	ir_raw_event_store_with_timeout(ir->rc, &rawir);
> +	if (ir->rc->driver_type == RC_DRIVER_IR_RAW) {
> +		rawir.pulse = !!(status & IR_DEC_STATUS_PULSE);
> +
> +		regmap_read(ir->reg, IR_DEC_REG1, &duration);
> +		duration = FIELD_GET(IR_DEC_REG1_TIME_IV, duration);
> +		rawir.duration = duration * MESON_RAW_TRATE;
> +
> +		ir_raw_event_store_with_timeout(ir->rc, &rawir);
> +	} else if (ir->rc->driver_type == RC_DRIVER_SCANCODE) {
> +		if (status & DEC_STATUS_VALID)
> +			meson_ir_hw_handler(ir);
> +	}
>  
>  	spin_unlock(&ir->lock);
>  
>  	return IRQ_HANDLED;
>  }
>  
> +static int meson_ir_hw_decoder_init(struct rc_dev *dev, u64 *rc_type)
> +{
> +	u8 protocol;
> +	u32 regval;
> +	int i;
> +	unsigned long flags;
> +	const struct meson_ir_protocol *timings;
> +	struct meson_ir *ir = dev->priv;
> +
> +	if (*rc_type & RC_PROTO_BIT_NEC)
> +		protocol = DEC_MODE_NEC;
> +	else
> +		return 0;
> +
> +	for (i = 0; i < ARRAY_SIZE(protocol_timings); i++)
> +		if (protocol_timings[i].hw_protocol == protocol)
> +			break;
> +
> +	if (i == ARRAY_SIZE(protocol_timings)) {
> +		dev_err(&dev->dev, "hw protocol isn't supported: %d\n",
> +			protocol);
> +		return -EINVAL;
> +	}
> +	timings = &protocol_timings[i];
> +
> +	spin_lock_irqsave(&ir->lock, flags);
> +
> +	/* Clear controller status */
> +	regmap_read(ir->reg, IR_DEC_STATUS, &regval);
> +	regmap_read(ir->reg, IR_DEC_FRAME, &regval);
> +
> +	/* Reset ir decoder and disable decoder */
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
> +			   IR_DEC_REG1_RESET);
> +
> +	/* Base time resolution, (19+1)*1us=20us */
> +	regval = FIELD_PREP(IR_DEC_REG0_BASE_TIME, MESON_HW_TRATE - 1);
> +	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME, regval);
> +
> +	/* Monitor timing for input filter */
> +	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_FILTER,
> +			   FIELD_PREP(IR_DEC_REG0_FILTER, 7));
> +
> +	/* HW protocol */
> +	regval = FIELD_PREP(IR_DEC_REG2_MODE, timings->hw_protocol);
> +	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE, regval);
> +
> +	/* Hold frame data until register was read */
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_HOLD_CODE,
> +			   timings->hold_code_enable ?
> +			   IR_DEC_REG1_HOLD_CODE : 0);
> +
> +	/* Bit order */
> +	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_BIT_ORDER,
> +			   timings->bit_order ? IR_DEC_REG2_BIT_ORDER : 0);
> +
> +	/* Select tick mode */
> +	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_TICK_MODE,
> +			   timings->count_tick_mode ?
> +			   IR_DEC_REG2_TICK_MODE : 0);
> +
> +	/*
> +	 * Some protocols transmit the same data frame as repeat frame
> +	 * when the key is pressing. In this case, it could be detected as
> +	 * repeat frame if the repeat checker was enabled.
> +	 */
> +	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_REPEAT_COUNTER,
> +			   timings->repeat_counter_enable ?
> +			   IR_DEC_REG2_REPEAT_COUNTER : 0);
> +	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_REPEAT_TIME,
> +			   timings->repeat_check_enable ?
> +			   IR_DEC_REG2_REPEAT_TIME : 0);
> +	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_COMPARE_FRAME,
> +			   timings->repeat_compare_enable ?
> +			   IR_DEC_REG2_COMPARE_FRAME : 0);
> +
> +	/*
> +	 * FRAME_TIME_MAX should be larger than the time between
> +	 * data frame and repeat frame
> +	 */
> +	regval = FIELD_PREP(IR_DEC_REG0_FRAME_TIME_MAX,
> +			    timings->frame_time_max);
> +	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_FRAME_TIME_MAX,
> +			   regval);
> +
> +	/* Length(N-1) of data frame */
> +	regval = FIELD_PREP(IR_DEC_REG1_FRAME_LEN, timings->code_length - 1);
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_FRAME_LEN, regval);
> +
> +	/* Time for leader active part */
> +	regval = FIELD_PREP(IR_DEC_LDR_ACTIVE_MAX,
> +			    timings->leader_active_max) |
> +		 FIELD_PREP(IR_DEC_LDR_ACTIVE_MIN,
> +			    timings->leader_active_min);
> +	regmap_update_bits(ir->reg, IR_DEC_LDR_ACTIVE, IR_DEC_LDR_ACTIVE_MAX |
> +			   IR_DEC_LDR_ACTIVE_MIN, regval);
> +
> +	/* Time for leader idle part */
> +	regval = FIELD_PREP(IR_DEC_LDR_IDLE_MAX, timings->leader_idle_max) |
> +		 FIELD_PREP(IR_DEC_LDR_IDLE_MIN, timings->leader_idle_min);
> +	regmap_update_bits(ir->reg, IR_DEC_LDR_IDLE,
> +			   IR_DEC_LDR_IDLE_MAX | IR_DEC_LDR_IDLE_MIN, regval);
> +
> +	/* Time for repeat leader idle part */
> +	regval = FIELD_PREP(IR_DEC_LDR_REPEAT_MAX, timings->repeat_leader_max) |
> +		 FIELD_PREP(IR_DEC_LDR_REPEAT_MIN, timings->repeat_leader_min);
> +	regmap_update_bits(ir->reg, IR_DEC_LDR_REPEAT, IR_DEC_LDR_REPEAT_MAX |
> +			   IR_DEC_LDR_REPEAT_MIN, regval);
> +
> +	/*
> +	 * NEC: Time for logic '0'
> +	 * RC6: Time for half of trailer bit
> +	 */
> +	regval = FIELD_PREP(IR_DEC_BIT_0_MAX, timings->bit0_max) |
> +		 FIELD_PREP(IR_DEC_BIT_0_MIN, timings->bit0_min);
> +	regmap_update_bits(ir->reg, IR_DEC_BIT_0,
> +			   IR_DEC_BIT_0_MAX | IR_DEC_BIT_0_MIN, regval);
> +
> +	/*
> +	 * NEC: Time for logic '1'
> +	 * RC6: Time for whole of trailer bit
> +	 */
> +	regval = FIELD_PREP(IR_DEC_STATUS_BIT_1_MAX, timings->bit1_max) |
> +		 FIELD_PREP(IR_DEC_STATUS_BIT_1_MIN, timings->bit1_min);
> +	regmap_update_bits(ir->reg, IR_DEC_STATUS, IR_DEC_STATUS_BIT_1_MAX |
> +			   IR_DEC_STATUS_BIT_1_MIN, regval);
> +
> +	/* Enable to match logic '1' */
> +	regmap_update_bits(ir->reg, IR_DEC_STATUS, IR_DEC_STATUS_BIT_1_ENABLE,
> +			   timings->bit1_match_enable ?
> +			   IR_DEC_STATUS_BIT_1_ENABLE : 0);
> +
> +	/*
> +	 * NEC: Unused
> +	 * RC6: Time for halt of logic 0/1
> +	 */
> +	regval = FIELD_PREP(IR_DEC_DURATN2_MAX, timings->duration2_max) |
> +		 FIELD_PREP(IR_DEC_DURATN2_MIN, timings->duration2_min);
> +	regmap_update_bits(ir->reg, IR_DEC_DURATN2,
> +			   IR_DEC_DURATN2_MAX | IR_DEC_DURATN2_MIN, regval);
> +
> +	/*
> +	 * NEC: Unused
> +	 * RC6: Time for whole logic 0/1
> +	 */
> +	regval = FIELD_PREP(IR_DEC_DURATN3_MAX, timings->duration3_max) |
> +		 FIELD_PREP(IR_DEC_DURATN3_MIN, timings->duration3_min);
> +	regmap_update_bits(ir->reg, IR_DEC_DURATN3,
> +			   IR_DEC_DURATN3_MAX | IR_DEC_DURATN3_MIN, regval);
> +
> +	/* Reset ir decoder and enable decode */
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
> +			   IR_DEC_REG1_RESET);
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
> +			   IR_DEC_REG1_ENABLE);
> +
> +	spin_unlock_irqrestore(&ir->lock, flags);
> +
> +	dev_info(&dev->dev, "hw decoder init, protocol: %d\n", protocol);
> +
> +	return 0;
> +}
> +
> +static void meson_ir_sw_decoder_init(struct rc_dev *dev)
> +{
> +	unsigned long flags;
> +	struct meson_ir *ir = dev->priv;
> +
> +	spin_lock_irqsave(&ir->lock, flags);
> +
> +	/* Reset the decoder */
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
> +			   IR_DEC_REG1_RESET);
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
> +
> +	/* Set general operation mode (= raw/software decoding) */
> +	if (of_device_is_compatible(dev->dev.of_node, "amlogic,meson6-ir"))
> +		regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE,
> +				   FIELD_PREP(IR_DEC_REG1_MODE,
> +					      DEC_MODE_RAW));
> +	else
> +		regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE,
> +				   FIELD_PREP(IR_DEC_REG2_MODE,
> +					      DEC_MODE_RAW));
> +
> +	/* Set rate */
> +	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
> +			   FIELD_PREP(IR_DEC_REG0_BASE_TIME,
> +				      MESON_RAW_TRATE - 1));
> +	/* IRQ on rising and falling edges */
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_IRQSEL,
> +			   FIELD_PREP(IR_DEC_REG1_IRQSEL, IRQSEL_RISE_FALL));
> +	/* Enable the decoder */
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
> +			   IR_DEC_REG1_ENABLE);
> +
> +	spin_unlock_irqrestore(&ir->lock, flags);
> +
> +	dev_info(&dev->dev, "sw decoder init\n");
> +}
> +
>  static int meson_ir_probe(struct platform_device *pdev)
>  {
> +	const struct meson_ir_param *match_data;
>  	struct device *dev = &pdev->dev;
>  	struct device_node *node = dev->of_node;
>  	void __iomem *res_start;
> @@ -97,10 +455,17 @@ static int meson_ir_probe(struct platform_device *pdev)
>  	if (!ir)
>  		return -ENOMEM;
>  
> +	match_data = of_device_get_match_data(dev);
> +	if (!match_data)
> +		return dev_err_probe(dev, -ENODEV, "failed to get match data\n");
> +
> +	ir->param = match_data;
> +
>  	res_start = devm_platform_ioremap_resource(pdev, 0);
>  	if (IS_ERR(res_start))
>  		return PTR_ERR(res_start);
>  
> +	meson_ir_regmap_config.max_register = ir->param->max_register;
>  	ir->reg = devm_regmap_init_mmio(&pdev->dev, res_start,
>  					&meson_ir_regmap_config);
>  	if (IS_ERR(ir->reg))
> @@ -110,23 +475,34 @@ static int meson_ir_probe(struct platform_device *pdev)
>  	if (irq < 0)
>  		return irq;
>  
> -	ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
> +	if (ir->param->support_hw_decoder)
> +		ir->rc = devm_rc_allocate_device(&pdev->dev,
> +						 RC_DRIVER_SCANCODE);
> +	else
> +		ir->rc = devm_rc_allocate_device(&pdev->dev, RC_DRIVER_IR_RAW);
> +
>  	if (!ir->rc) {
>  		dev_err(dev, "failed to allocate rc device\n");
>  		return -ENOMEM;
>  	}
>  
> +	if (ir->rc->driver_type == RC_DRIVER_IR_RAW) {
> +		ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
> +		ir->rc->rx_resolution = MESON_RAW_TRATE;
> +		ir->rc->min_timeout = 1;
> +		ir->rc->timeout = IR_DEFAULT_TIMEOUT;
> +		ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
> +	} else if (ir->rc->driver_type == RC_DRIVER_SCANCODE) {
> +		ir->rc->allowed_protocols = RC_PROTO_BIT_NEC;
> +		ir->rc->change_protocol = meson_ir_hw_decoder_init;
> +	}
> +
>  	ir->rc->priv = ir;
>  	ir->rc->device_name = DRIVER_NAME;
>  	ir->rc->input_phys = DRIVER_NAME "/input0";
>  	ir->rc->input_id.bustype = BUS_HOST;
>  	map_name = of_get_property(node, "linux,rc-map-name", NULL);
>  	ir->rc->map_name = map_name ? map_name : RC_MAP_EMPTY;
> -	ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
> -	ir->rc->rx_resolution = MESON_RAW_TRATE;
> -	ir->rc->min_timeout = 1;
> -	ir->rc->timeout = IR_DEFAULT_TIMEOUT;
> -	ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
>  	ir->rc->driver_name = DRIVER_NAME;
>  
>  	spin_lock_init(&ir->lock);
> @@ -138,36 +514,15 @@ static int meson_ir_probe(struct platform_device *pdev)
>  		return ret;
>  	}
>  
> -	ret = devm_request_irq(dev, irq, meson_ir_irq, 0, NULL, ir);
> +	if (ir->rc->driver_type == RC_DRIVER_IR_RAW)
> +		meson_ir_sw_decoder_init(ir->rc);
> +
> +	ret = devm_request_irq(dev, irq, meson_ir_irq, 0, "meson_ir", ir);
>  	if (ret) {
>  		dev_err(dev, "failed to request irq\n");
>  		return ret;
>  	}
>  
> -	/* Reset the decoder */
> -	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
> -			   IR_DEC_REG1_RESET);
> -	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
> -
> -	/* Set general operation mode (= raw/software decoding) */
> -	if (of_device_is_compatible(node, "amlogic,meson6-ir"))
> -		regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE,
> -				   FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_RAW));
> -	else
> -		regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE,
> -				   FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_RAW));
> -
> -	/* Set rate */
> -	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
> -			   FIELD_PREP(IR_DEC_REG0_BASE_TIME,
> -				      MESON_RAW_TRATE - 1));
> -	/* IRQ on rising and falling edges */
> -	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_IRQSEL,
> -			   FIELD_PREP(IR_DEC_REG1_IRQSEL, IRQSEL_RISE_FALL));
> -	/* Enable the decoder */
> -	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
> -			   IR_DEC_REG1_ENABLE);
> -
>  	dev_info(dev, "receiver initialized\n");
>  
>  	return 0;
> @@ -212,11 +567,36 @@ static void meson_ir_shutdown(struct platform_device *pdev)
>  	spin_unlock_irqrestore(&ir->lock, flags);
>  }
>  
> +static const struct meson_ir_param meson6_ir_param = {
> +	.support_hw_decoder = false,
> +	.max_register = IR_DEC_REG1,
> +};
> +
> +static const struct meson_ir_param meson8b_ir_param = {
> +	.support_hw_decoder = false,
> +	.max_register = IR_DEC_REG2,
> +};
> +
> +static const struct meson_ir_param meson_s4_ir_param = {
> +	.support_hw_decoder = true,
> +	.max_register = IR_DEC_FRAME1,
> +};
> +
>  static const struct of_device_id meson_ir_match[] = {
> -	{ .compatible = "amlogic,meson6-ir" },
> -	{ .compatible = "amlogic,meson8b-ir" },
> -	{ .compatible = "amlogic,meson-gxbb-ir" },
> -	{ },
> +	{
> +		.compatible = "amlogic,meson6-ir",
> +		.data = &meson6_ir_param,
> +	}, {
> +		.compatible = "amlogic,meson8b-ir",
> +		.data = &meson8b_ir_param,
> +	}, {
> +		.compatible = "amlogic,meson-gxbb-ir",
> +		.data = &meson8b_ir_param,
> +	}, {
> +		.compatible = "amlogic,meson-s4-ir",
> +		.data = &meson_s4_ir_param,
> +	},
> +	{},
>  };
>  MODULE_DEVICE_TABLE(of, meson_ir_match);
>  
> -- 
> 2.35.1

Re: [PATCH 1/3] media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE

[Zelong Dong]

在 2023/8/29 15:39, Sean Young 写道:
> On Fri, Aug 25, 2023 at 07:53:08PM +0800, zelong dong wrote:
>> From: Zelong Dong<zelong.dong@amlogic.com>
>>
>> Meson IR Controller supports hardware decoder in Meson-S4 and later
>> SoC. So far, protocol NEC could be decoded by hardware decoder.
> On Meson-S4, only the hardware decoder for NEC can be used using this
> driver. Does the Meson-S4 hardware support software decoding? If
> software decoding could be used, then any protocol could be supported,
> not just NEC.
> 
> Also, out of interest, is there are documentation available for this
> hardware?
> 
> Thanks,
> 
> Sean
> 
Yes, IR driver still supports SW decoding on Meson-S4. The decode mode 
could be changed by 'support_hw_decoder'.
If IR Controller works in SW decoding, driver will be registered by 
RC_DRIVER_IR_RAW and allows all protocol.
Otherwise, driver will be registered by RC_DRIVER_SCANCODE and only 
allows NEC.

489         if (ir->rc->driver_type == RC_DRIVER_IR_RAW) {
490                 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
491                 ir->rc->rx_resolution = MESON_RAW_TRATE;
492                 ir->rc->min_timeout = 1;
493                 ir->rc->timeout = IR_DEFAULT_TIMEOUT;
494                 ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
495         } else if (ir->rc->driver_type == RC_DRIVER_SCANCODE) {
496                 ir->rc->allowed_protocols = RC_PROTO_BIT_NEC;
497                 ir->rc->change_protocol = meson_ir_hw_decoder_init;
498         }

Do you get Meson-S4 datasheet? Please refer to chapter 13.5 Infrared Remote.

Re: [PATCH 1/3] media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE

[Sean Young]

On Thu, Aug 31, 2023 at 08:13:22PM +0800, Zelong Dong wrote:
> 在 2023/8/29 15:39, Sean Young 写道:
> > On Fri, Aug 25, 2023 at 07:53:08PM +0800, zelong dong wrote:
> > > From: Zelong Dong<zelong.dong@amlogic.com>
> > > 
> > > Meson IR Controller supports hardware decoder in Meson-S4 and later
> > > SoC. So far, protocol NEC could be decoded by hardware decoder.
> > On Meson-S4, only the hardware decoder for NEC can be used using this
> > driver. Does the Meson-S4 hardware support software decoding? If
> > software decoding could be used, then any protocol could be supported,
> > not just NEC.
> > 
> > Also, out of interest, is there are documentation available for this
> > hardware?
> > 
> > Thanks,
> > 
> > Sean
> > 
> Yes, IR driver still supports SW decoding on Meson-S4. The decode mode could
> be changed by 'support_hw_decoder'.

This requires changing the source code, it cannot be done at runtime.

> If IR Controller works in SW decoding, driver will be registered by
> RC_DRIVER_IR_RAW and allows all protocol.
> Otherwise, driver will be registered by RC_DRIVER_SCANCODE and only allows
> NEC.
> 
> 489         if (ir->rc->driver_type == RC_DRIVER_IR_RAW) {
> 490                 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
> 491                 ir->rc->rx_resolution = MESON_RAW_TRATE;
> 492                 ir->rc->min_timeout = 1;
> 493                 ir->rc->timeout = IR_DEFAULT_TIMEOUT;
> 494                 ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
> 495         } else if (ir->rc->driver_type == RC_DRIVER_SCANCODE) {
> 496                 ir->rc->allowed_protocols = RC_PROTO_BIT_NEC;
> 497                 ir->rc->change_protocol = meson_ir_hw_decoder_init;
> 498         }

There are other drivers too which can do hardware decoding and software
decoding. Ideally we should have a mechanism to switch between them at
runtime, but as-is rc-core does not provide for this.

> Do you get Meson-S4 datasheet? Please refer to chapter 13.5 Infrared Remote.

I did not get it, unfortunately. Any help would be appreciated, thanks.

Other than that, the driver does look fine. Nothing to hold up merging for. 
I'll apply it when I can.

Thanks,

Sean

Re: [PATCH 1/3] media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE

[Zelong Dong]

在 2023/8/25 20:19, Neil Armstrong 写道:
> On 25/08/2023 13:53, zelong dong wrote:
>> From: Zelong Dong <zelong.dong@amlogic.com>
>>
>> Meson IR Controller supports hardware decoder in Meson-S4 and later
>> SoC. So far, protocol NEC could be decoded by hardware decoder.
>>
>> Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
>> ---
>>   drivers/media/rc/meson-ir.c | 522 +++++++++++++++++++++++++++++++-----
>>   1 file changed, 451 insertions(+), 71 deletions(-)
>>
> 
> <snip>
> 
> It looks pretty good now, so far I'm ok with it:
> 
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> 
> I think some test reports would be needed to be sure it doesn't regress 
> existing HW.
> 
> Thanks,
> Neil

Sorry for my late reply, I spent a long time looking for development boards.
I searched Meson-IR DT Node from all the Amlogic DT, only 4 DTSI as follow:
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
arch/arm/boot/dts/amlogic/meson.dtsi

So I planned to sample the boards to test:
arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts

Unfortunately, meson-gxl-s905x-p212 & meson8b-odroidc1 are too old to be 
find.
there are only 2 boards I got, meson-g12a-u200 & meson-axg-s400, and 
they worked.

[    0.943097] IR NEC protocol handler initialized
[    0.943146] IR RC5(x/sz) protocol handler initialized
[    0.947029] IR RC6 protocol handler initialized
[    0.951508] IR RCMM protocol handler initialized
[    0.956080] IR XMP protocol handler initialized
[    0.961266] Registered IR keymap rc-empty
[    0.964674] rc rc0: meson-ir as 
/devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
[    0.972437] input: meson-ir as 
/devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
[    0.980983] rc rc0: sw decoder init
[    0.984089] meson-ir ff808000.ir: receiver initialized

# cd /sys/devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/
# cat protocols
rc-5 nec rc-6 rc-5-sz xmp rc-mm
# echo nec > protocols
# hexdump /dev/input/event0
0000000 0069 0000 3180 0005 0004 0004 011b 0000
0000010 0069 0000 3180 0005 0000 0000 0000 0000
0000020 0069 0000 fc80 0005 0004 0004 011b 0000
0000030 0069 0000 fc80 0005 0000 0000 0000 0000
0000040 0069 0000 92db 0007 0004 0004 011b 0000
0000050 0069 0000 92db 0007 0000 0000 0000 0000
0000060 0069 0000 388b 0009 0004 0004 011b 0000
0000070 0069 0000 388b 0009 0000 0000 0000 0000
0000080 0069 0000 de72 000a 0004 0004 011b 0000
0000090 0069 0000 de72 000a 0000 0000 0000 0000

Re: [PATCH 1/3] media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE

[neil.armstrong]

On 06/09/2023 09:11, Zelong Dong wrote:
> 
> 
> 在 2023/8/25 20:19, Neil Armstrong 写道:
>> On 25/08/2023 13:53, zelong dong wrote:
>>> From: Zelong Dong <zelong.dong@amlogic.com>
>>>
>>> Meson IR Controller supports hardware decoder in Meson-S4 and later
>>> SoC. So far, protocol NEC could be decoded by hardware decoder.
>>>
>>> Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
>>> ---
>>>   drivers/media/rc/meson-ir.c | 522 +++++++++++++++++++++++++++++++-----
>>>   1 file changed, 451 insertions(+), 71 deletions(-)
>>>
>>
>> <snip>
>>
>> It looks pretty good now, so far I'm ok with it:
>>
>> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
>>
>> I think some test reports would be needed to be sure it doesn't regress existing HW.
>>
>> Thanks,
>> Neil
> 
> Sorry for my late reply, I spent a long time looking for development boards.
> I searched Meson-IR DT Node from all the Amlogic DT, only 4 DTSI as follow:
> arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
> arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> arch/arm/boot/dts/amlogic/meson.dtsi
> 
> So I planned to sample the boards to test:
> arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
> arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts
> arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts
> 
> Unfortunately, meson-gxl-s905x-p212 & meson8b-odroidc1 are too old to be find.
> there are only 2 boards I got, meson-g12a-u200 & meson-axg-s400, and they worked.
> 
> [    0.943097] IR NEC protocol handler initialized
> [    0.943146] IR RC5(x/sz) protocol handler initialized
> [    0.947029] IR RC6 protocol handler initialized
> [    0.951508] IR RCMM protocol handler initialized
> [    0.956080] IR XMP protocol handler initialized
> [    0.961266] Registered IR keymap rc-empty
> [    0.964674] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
> [    0.972437] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
> [    0.980983] rc rc0: sw decoder init
> [    0.984089] meson-ir ff808000.ir: receiver initialized
> 
> # cd /sys/devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/
> # cat protocols
> rc-5 nec rc-6 rc-5-sz xmp rc-mm
> # echo nec > protocols
> # hexdump /dev/input/event0
> 0000000 0069 0000 3180 0005 0004 0004 011b 0000
> 0000010 0069 0000 3180 0005 0000 0000 0000 0000
> 0000020 0069 0000 fc80 0005 0004 0004 011b 0000
> 0000030 0069 0000 fc80 0005 0000 0000 0000 0000
> 0000040 0069 0000 92db 0007 0004 0004 011b 0000
> 0000050 0069 0000 92db 0007 0000 0000 0000 0000
> 0000060 0069 0000 388b 0009 0004 0004 011b 0000
> 0000070 0069 0000 388b 0009 0000 0000 0000 0000
> 0000080 0069 0000 de72 000a 0004 0004 011b 0000
> 0000090 0069 0000 de72 000a 0000 0000 0000 0000

It's fine !

Thanks for testing !!

Neil

Re: [PATCH 1/3] media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE

[Zelong Dong]

在 2023/9/1 16:02, Sean Young 写道:
> On Thu, Aug 31, 2023 at 08:13:22PM +0800, Zelong Dong wrote:
>> 在 2023/8/29 15:39, Sean Young 写道:
>>> On Fri, Aug 25, 2023 at 07:53:08PM +0800, zelong dong wrote:
>>>> From: Zelong Dong<zelong.dong@amlogic.com>
>>>>
>>>> Meson IR Controller supports hardware decoder in Meson-S4 and later
>>>> SoC. So far, protocol NEC could be decoded by hardware decoder.
>>> On Meson-S4, only the hardware decoder for NEC can be used using this
>>> driver. Does the Meson-S4 hardware support software decoding? If
>>> software decoding could be used, then any protocol could be supported,
>>> not just NEC.
>>>
>>> Also, out of interest, is there are documentation available for this
>>> hardware?
>>>
>>> Thanks,
>>>
>>> Sean
>>>
>> Yes, IR driver still supports SW decoding on Meson-S4. The decode mode could
>> be changed by 'support_hw_decoder'.
> 
> This requires changing the source code, it cannot be done at runtime.
> 
>> If IR Controller works in SW decoding, driver will be registered by
>> RC_DRIVER_IR_RAW and allows all protocol.
>> Otherwise, driver will be registered by RC_DRIVER_SCANCODE and only allows
>> NEC.
>>
>> 489         if (ir->rc->driver_type == RC_DRIVER_IR_RAW) {
>> 490                 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
>> 491                 ir->rc->rx_resolution = MESON_RAW_TRATE;
>> 492                 ir->rc->min_timeout = 1;
>> 493                 ir->rc->timeout = IR_DEFAULT_TIMEOUT;
>> 494                 ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
>> 495         } else if (ir->rc->driver_type == RC_DRIVER_SCANCODE) {
>> 496                 ir->rc->allowed_protocols = RC_PROTO_BIT_NEC;
>> 497                 ir->rc->change_protocol = meson_ir_hw_decoder_init;
>> 498         }
> 
> There are other drivers too which can do hardware decoding and software
> decoding. Ideally we should have a mechanism to switch between them at
> runtime, but as-is rc-core does not provide for this.
Anything else I should update for this patchset?
> 
>> Do you get Meson-S4 datasheet? Please refer to chapter 13.5 Infrared Remote.
> 
> I did not get it, unfortunately. Any help would be appreciated, thanks.
Sorry, this document is not public and I don't have permission to share 
with you. Perhaps you could apply to xiaohong.zou@amlogic.com for 
Meson-S4 datasheet.
> 
> Other than that, the driver does look fine. Nothing to hold up merging for.
> I'll apply it when I can.
> 
> Thanks,
> 
> Sean

Re: [PATCH 1/3] media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE

[Sean Young]

On Wed, Sep 06, 2023 at 06:37:41PM +0800, Zelong Dong wrote:
> 在 2023/9/1 16:02, Sean Young 写道:
> > There are other drivers too which can do hardware decoding and software
> > decoding. Ideally we should have a mechanism to switch between them at
> > runtime, but as-is rc-core does not provide for this.
> Anything else I should update for this patchset?

I don't think so.

I was just saying that it would be great to have runtime switching in the
future.

Thanks,

Sean

Re: (subset) [PATCH 0/3] This patchset adds IR controller driver support for

[Neil Armstrong]

Hi,

On Fri, 25 Aug 2023 19:53:07 +0800, zelong dong wrote:
> From: Zelong Dong <zelong.dong@amlogic.com>
> 
> Meson IR Controller supports hardware decoder in Meson-S4 and later
> SoC. So far, protocol NEC could be decoded by hardware decoder.
> 
> Zelong Dong (3):
>   media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE
>   dt-bindings: media: Add compatible for Meson-S4 IR Controller
>   arm64: dts: meson: add IR controller for Meson-S4 SoC
> 
> [...]

Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v6.7/arm64-dt)

[3/3] arm64: dts: meson: add IR controller for Meson-S4 SoC
      https://git.kernel.org/amlogic/c/dc8bc779feb5e855421215384f23de90a4fcd622

These changes has been applied on the intermediate git tree [1].

The v6.7/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
for inclusion in their intermediate git branches in order to be sent to Linus during
the next merge window, or sooner if it's a set of fixes.

In the cases of fixes, those will be merged in the current release candidate
kernel and as soon they appear on the Linux master branch they will be
backported to the previous Stable and Long-Stable kernels [2].

The intermediate git branches are merged daily in the linux-next tree [3],
people are encouraged testing these pre-release kernels and report issues on the
relevant mailing-lists.

If problems are discovered on those changes, please submit a signed-off-by revert
patch followed by a corrective changeset.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
[3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git

-- 
Neil

Re: (subset) [PATCH 0/3] This patchset adds IR controller driver support for

[Sean Young]

On Mon, Sep 11, 2023 at 11:46:33AM +0200, Neil Armstrong wrote:
> On Fri, 25 Aug 2023 19:53:07 +0800, zelong dong wrote:
> > From: Zelong Dong <zelong.dong@amlogic.com>
> > 
> > Meson IR Controller supports hardware decoder in Meson-S4 and later
> > SoC. So far, protocol NEC could be decoded by hardware decoder.
> > 
> > Zelong Dong (3):
> >   media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE
> >   dt-bindings: media: Add compatible for Meson-S4 IR Controller
> >   arm64: dts: meson: add IR controller for Meson-S4 SoC
> > 
> > [...]
> 
> Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v6.7/arm64-dt)
> 
> [3/3] arm64: dts: meson: add IR controller for Meson-S4 SoC
>       https://git.kernel.org/amlogic/c/dc8bc779feb5e855421215384f23de90a4fcd622

Would make more sense to have all three patches go in together through a single
tree? I was about to apply all three of these patches to the media_stage
tree.


Sean

Re: (subset) [PATCH 0/3] This patchset adds IR controller driver support for

[Neil Armstrong]

On 11/09/2023 12:30, Sean Young wrote:
> On Mon, Sep 11, 2023 at 11:46:33AM +0200, Neil Armstrong wrote:
>> On Fri, 25 Aug 2023 19:53:07 +0800, zelong dong wrote:
>>> From: Zelong Dong <zelong.dong@amlogic.com>
>>>
>>> Meson IR Controller supports hardware decoder in Meson-S4 and later
>>> SoC. So far, protocol NEC could be decoded by hardware decoder.
>>>
>>> Zelong Dong (3):
>>>    media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE
>>>    dt-bindings: media: Add compatible for Meson-S4 IR Controller
>>>    arm64: dts: meson: add IR controller for Meson-S4 SoC
>>>
>>> [...]
>>
>> Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v6.7/arm64-dt)
>>
>> [3/3] arm64: dts: meson: add IR controller for Meson-S4 SoC
>>        https://git.kernel.org/amlogic/c/dc8bc779feb5e855421215384f23de90a4fcd622
> 
> Would make more sense to have all three patches go in together through a single
> tree? I was about to apply all three of these patches to the media_stage
> tree.

There's a lot of changes in the S4 dtsi, it would create some merge conflicts
if it went into the media tree, if you can take the 2 first patches it would be perfect.

It won't break anything to have the DT merged separately anyway

Neil

> 
> 
> Sean

Re: (subset) [PATCH 0/3] This patchset adds IR controller driver support for

[Krzysztof Kozlowski]

On 11/09/2023 12:30, Sean Young wrote:
> On Mon, Sep 11, 2023 at 11:46:33AM +0200, Neil Armstrong wrote:
>> On Fri, 25 Aug 2023 19:53:07 +0800, zelong dong wrote:
>>> From: Zelong Dong <zelong.dong@amlogic.com>
>>>
>>> Meson IR Controller supports hardware decoder in Meson-S4 and later
>>> SoC. So far, protocol NEC could be decoded by hardware decoder.
>>>
>>> Zelong Dong (3):
>>>   media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE
>>>   dt-bindings: media: Add compatible for Meson-S4 IR Controller
>>>   arm64: dts: meson: add IR controller for Meson-S4 SoC
>>>
>>> [...]
>>
>> Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v6.7/arm64-dt)
>>
>> [3/3] arm64: dts: meson: add IR controller for Meson-S4 SoC
>>       https://git.kernel.org/amlogic/c/dc8bc779feb5e855421215384f23de90a4fcd622
> 
> Would make more sense to have all three patches go in together through a single
> tree? I was about to apply all three of these patches to the media_stage

No, DTS should not go via driver (non-SoC) tree. If you insist on that,
it would be a sign your patchset is not bisectable or have ABI break.

Best regards,
Krzysztof

Re: [PATCH 1/3] media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE

[Dmitry Rokosov]

Hello Zelong,

On Thu, Mar 02, 2023 at 02:34:00PM +0800, zelong dong wrote:
> From: Zelong Dong <zelong.dong@amlogic.com>
> 
> Meson IR Controller supports hardware decoder in Meson-8B and later
> SoC. So far, protocol NEC/RC-6/XMP could be decoded in hardware.
> DTS property 'amlogic,ir-support-hw-decode' can enable this feature.
> 
> Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
> ---
>  drivers/media/rc/meson-ir.c | 713 ++++++++++++++++++++++++++++++++----
>  1 file changed, 632 insertions(+), 81 deletions(-)
> 
> diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c
> index 4b769111f78e..1bfdce1c1864 100644
> --- a/drivers/media/rc/meson-ir.c
> +++ b/drivers/media/rc/meson-ir.c
> @@ -14,6 +14,7 @@
>  #include <linux/platform_device.h>
>  #include <linux/spinlock.h>
>  #include <linux/bitfield.h>
> +#include <linux/regmap.h>
>  
>  #include <media/rc-core.h>
>  
> @@ -21,87 +22,598 @@
>  
>  /* valid on all Meson platforms */
>  #define IR_DEC_LDR_ACTIVE	0x00
> +	#define	IR_DEC_LDR_ACTIVE_MAX		GENMASK(28, 16)
> +	#define	IR_DEC_LDR_ACTIVE_MIN		GENMASK(12, 0)

Extra tabs before #define statement. The same problem is located in
the whole patchset.

[...]

> +#define MESON_IR_TIMINGS(proto, r_cnt, r_chk, r_comp, b1_e, hc, cnt_tick, ori, \
> +			 flt, len, f_max, la_max, la_min, li_max, li_min,      \
> +			 rl_max, rl_min, b0_max, b0_min, b1_max, b1_min,       \
> +			 d2_max, d2_min, d3_max, d3_min)		\
> +	{								\
> +		.hw_protocol =			proto,			\
> +		.repeat_counter_enable =	r_cnt,			\
> +		.repeat_check_enable =		r_chk,			\
> +		.repeat_compare_enable =	r_comp,			\
> +		.bit1_match_enable =		b1_e,			\
> +		.hold_code_enable =		hc,			\
> +		.count_tick_mode =		cnt_tick,		\
> +		.bit_order =			ori,			\
> +		.filter_cnt =			flt,			\
> +		.code_length =			len,			\
> +		.frame_time_max =		f_max,			\
> +		.leader_active_max =		la_max,			\
> +		.leader_active_min =		la_min,			\
> +		.leader_idle_max =		li_max,			\
> +		.leader_idle_min =		li_min,			\
> +		.repeat_leader_max =		rl_max,			\
> +		.repeat_leader_min =		rl_min,			\
> +		.bit0_max =			b0_max,			\
> +		.bit0_min =			b0_min,			\
> +		.bit1_max =			b1_max,			\
> +		.bit1_min =			b1_min,			\
> +		.duration2_max =		d2_max,			\
> +		.duration2_min =		d2_min,			\
> +		.duration3_max =		d3_max,			\
> +		.duration3_min =		d3_min,			\
> +	}								\

Extra tabs for back slash alignment

> +
> +/**
> + * struct meson_ir_param - describe IR Protocol parameter
> + * @hw_protocol: select IR Protocol from IR Controller.
> + * @repeat_counter_enable: enable frame-to-frame time counter, it should work
> + *	with @repeat_compare_enable to detect the repeat frame.
> + * @repeat_check_enable: enable repeat time check for repeat detection.
> + * @repeat_compare_enable: enable to compare frame for repeat frame detection.
> + *	Some IR Protocol send the same data as repeat frame. In this case,
> + *	it should work with @repeat_counter_enable to detect the repeat frame.
> + * @bit_order: bit order, LSB or MSB.
> + * @bit1_match_enable: enable to check bit 1.
> + * @hold_code_enable: hold frame code in register IR_DEC_FRAME1, the new one
> + *	frame code will not be store in IR_DEC_FRAME1. until IR_DEC_FRAME1
> + *	has been read.
> + * @count_tick_mode: increasing time unit of frame-to-frame time counter.
> + *	0 = 100us, 1 = 10us.
> + * @filter_cnt: input filter, to filter burr
> + * @code_length: length (N-1) of frame's data part.
> + * @frame_time_max: max time for whole frame. Unit: MESON_HW_TRATE
> + * @leader_active_max: max time for NEC/RC6 leader active part. Unit: MESON_HW_TRATE.
> + * @leader_active_min: min time for NEC/RC6 leader active part. Unit: MESON_HW_TRATE.
> + * @leader_idle_max: max time for NEC/RC6 leader idle part. Unit: MESON_HW_TRATE.
> + * @leader_idle_min: min time for NEC/RC6 leader idle part. Unit: MESON_HW_TRATE.
> + * @repeat_leader_max: max time for NEC repeat leader idle part. Unit: MESON_HW_TRATE.
> + * @repeat_leader_min: min time for NEC repeat leader idle part. Unit: MESON_HW_TRATE.
> + * @bit0_max: max time for NEC Logic '0', half of RC6 trailer bit, XMP Logic '00'
> + * @bit0_min: min time for NEC Logic '0', half of RC6 trailer bit, XMP Logic '00'
> + * @bit1_max: max time for NEC Logic '1', whole of RC6 trailer bit, XMP Logic '01'
> + * @bit1_min: min time for NEC Logic '1', whole of RC6 trailer bit, XMP Logic '01'
> + * @duration2_max: max time for half of RC6 normal bit, XMP Logic '10'.
> + * @duration2_min: min time for half of RC6 normal bit, XMP Logic '10'.
> + * @duration3_max: max time for whole of RC6 normal bit, XMP Logic '11'.
> + * @duration3_min: min time for whole of RC6 normal bit, XMP Logic '11'.
> + */
>  

Did you run checkpatch and kernel-doc checker for above struct
documentation?

> -#define REG0_RATE_MASK		GENMASK(11, 0)
> +struct meson_ir_param {
> +	u8		hw_protocol;
> +	bool		repeat_counter_enable;
> +	bool		repeat_check_enable;
> +	bool		repeat_compare_enable;
> +	bool		bit_order;
> +	bool		bit1_match_enable;
> +	bool		hold_code_enable;
> +	bool		count_tick_mode;
> +	u8		filter_cnt;
> +	u8		code_length;
> +	u16		frame_time_max;
> +	u16		leader_active_max;
> +	u16		leader_active_min;
> +	u16		leader_idle_max;
> +	u16		leader_idle_min;
> +	u16		repeat_leader_max;
> +	u16		repeat_leader_min;
> +	u16		bit0_max;
> +	u16		bit0_min;
> +	u16		bit1_max;
> +	u16		bit1_min;
> +	u16		duration2_max;
> +	u16		duration2_min;
> +	u16		duration3_max;
> +	u16		duration3_min;
> +};

Why do you need tab alignment between type and variable?

[...]

> +#ifdef CONFIG_PM
> +static int meson_ir_resume(struct device *dev)
> +{
> +	struct meson_ir *ir = dev_get_drvdata(dev);
> +
> +	if (ir->support_hw_dec)
> +		meson_ir_change_protocol(ir->rc, &ir->rc->enabled_protocols);
> +	else
> +		meson_ir_sw_decoder_init(ir->rc);
> +
> +	return 0;
> +}
> +
> +static int meson_ir_suspend(struct device *dev)
> +{
> +	struct meson_ir *ir = dev_get_drvdata(dev);
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&ir->lock, flags);
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
> +	spin_unlock_irqrestore(&ir->lock, flags);
> +
> +	return 0;
> +}
> +#endif
> +
>  static const struct of_device_id meson_ir_match[] = {
>  	{ .compatible = "amlogic,meson6-ir" },
>  	{ .compatible = "amlogic,meson8b-ir" },
>  	{ .compatible = "amlogic,meson-gxbb-ir" },
> +	{ .compatible = "amlogic,meson-s4-ir" },
>  	{ },
>  };
>  MODULE_DEVICE_TABLE(of, meson_ir_match);
>  
> +#ifdef CONFIG_PM
> +static const struct dev_pm_ops meson_ir_pm_ops = {
> +	.suspend_late = meson_ir_suspend,
> +	.resume_early = meson_ir_resume,
> +};
> +#endif
> +
>  static struct platform_driver meson_ir_driver = {
>  	.probe		= meson_ir_probe,
>  	.remove		= meson_ir_remove,
> @@ -231,6 +779,9 @@ static struct platform_driver meson_ir_driver = {
>  	.driver = {
>  		.name		= DRIVER_NAME,
>  		.of_match_table	= meson_ir_match,
> +#ifdef CONFIG_PM
> +		.pm = &meson_ir_pm_ops,
> +#endif

You can use pm_ptr() and DEFINE_SIMPLE_DEV_PM_OPS instead of checking of
CONFIG_PM definition.

[...]

-- 
Thank you,
Dmitry

Re: [PATCH 1/3] media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE

[Neil Armstrong]

Hi,

On 02/03/2023 07:34, zelong dong wrote:
> From: Zelong Dong <zelong.dong@amlogic.com>
> 
> Meson IR Controller supports hardware decoder in Meson-8B and later
> SoC. So far, protocol NEC/RC-6/XMP could be decoded in hardware.
> DTS property 'amlogic,ir-support-hw-decode' can enable this feature.

Thamks for your submittion, it's appeciated !

But, The change is too hard to review since you migrate to regmap at the same
time, please separate the migration to regmap first, then add HW decoding
in a separate change.
Same for suspend/resume addition and any other hw-decoding unrelated changes.

Neil

> 
> Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
> ---
>   drivers/media/rc/meson-ir.c | 713 ++++++++++++++++++++++++++++++++----
>   1 file changed, 632 insertions(+), 81 deletions(-)
> 
> diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c
> index 4b769111f78e..1bfdce1c1864 100644
> --- a/drivers/media/rc/meson-ir.c
> +++ b/drivers/media/rc/meson-ir.c
> @@ -14,6 +14,7 @@
>   #include <linux/platform_device.h>
>   #include <linux/spinlock.h>
>   #include <linux/bitfield.h>
> +#include <linux/regmap.h>
>   
>   #include <media/rc-core.h>
>   
> @@ -21,87 +22,598 @@
>   
>   /* valid on all Meson platforms */
>   #define IR_DEC_LDR_ACTIVE	0x00
> +	#define	IR_DEC_LDR_ACTIVE_MAX		GENMASK(28, 16)
> +	#define	IR_DEC_LDR_ACTIVE_MIN		GENMASK(12, 0)
> +
>   #define IR_DEC_LDR_IDLE		0x04
> +	#define	IR_DEC_LDR_IDLE_MAX		GENMASK(28, 16)
> +	#define	IR_DEC_LDR_IDLE_MIN		GENMASK(12, 0)
> +
>   #define IR_DEC_LDR_REPEAT	0x08
> +	#define	IR_DEC_LDR_REPEAT_MAX		GENMASK(25, 16)
> +	#define	IR_DEC_LDR_REPEAT_MIN		GENMASK(9, 0)
> +
>   #define IR_DEC_BIT_0		0x0c
> +	#define	IR_DEC_BIT_0_MAX		GENMASK(25, 16)
> +	#define	IR_DEC_BIT_0_MIN		GENMASK(9, 0)
> +
>   #define IR_DEC_REG0		0x10
> +	#define	IR_DEC_REG0_FILTER		GENMASK(30, 28)
> +	#define	IR_DEC_REG0_FRAME_TIME_MAX	GENMASK(24, 12)
> +	#define	IR_DEC_REG0_BASE_TIME		GENMASK(11, 0)
> +
>   #define IR_DEC_FRAME		0x14
> +
>   #define IR_DEC_STATUS		0x18
> +	#define	IR_DEC_STATUS_BIT_1_ENABLE	BIT(30)
> +	#define	IR_DEC_STATUS_BIT_1_MAX		GENMASK(29, 20)
> +	#define	IR_DEC_STATUS_BIT_1_MIN		GENMASK(19, 10)
> +	#define IR_DEC_STATUS_PULSE		BIT(8)
> +	#define	IR_DEC_STATUS_BUSY		BIT(7)
> +	#define	IR_DEC_STATUS_FRAME_STATUS	GENMASK(3, 0)
> +
>   #define IR_DEC_REG1		0x1c
> -/* only available on Meson 8b and newer */
> +	#define IR_DEC_REG1_TIME_IV		GENMASK(28, 16)
> +	#define	IR_DEC_REG1_FRAME_LEN		GENMASK(13, 8)
> +	#define IR_DEC_REG1_ENABLE		BIT(15)
> +	#define	IR_DEC_REG1_HOLD_CODE		BIT(6)
> +	#define IR_DEC_REG1_IRQSEL		GENMASK(3, 2)
> +	#define IR_DEC_REG1_RESET		BIT(0)
> +	/* Meson 6b uses REG1 to configure the mode */
> +	#define IR_DEC_REG1_MODE		GENMASK(8, 7)
> +
> +/* The following registers are only available on Meson 8b and newer */
>   #define IR_DEC_REG2		0x20
> +	#define	IR_DEC_REG2_TICK_MODE		BIT(15)
> +	#define	IR_DEC_REG2_REPEAT_COUNTER	BIT(13)
> +	#define	IR_DEC_REG2_REPEAT_TIME		BIT(12)
> +	#define	IR_DEC_REG2_COMPARE_FRAME	BIT(11)
> +	#define	IR_DEC_REG2_BIT_ORDER		BIT(8)
> +	/* Meson 8b / GXBB use REG2 to configure the mode */
> +	#define IR_DEC_REG2_MODE		GENMASK(3, 0)
> +
> +#define	IR_DEC_DURATN2		0x24
> +	#define	IR_DEC_DURATN2_MAX		GENMASK(25, 16)
> +	#define	IR_DEC_DURATN2_MIN		GENMASK(9, 0)
> +
> +#define	IR_DEC_DURATN3		0x28
> +	#define	IR_DEC_DURATN3_MAX		GENMASK(25, 16)
> +	#define	IR_DEC_DURATN3_MIN		GENMASK(9, 0)
> +
> +#define	IR_DEC_FRAME1		0x2c
> +
> +#define FRAME_MSB_FIRST				true
> +#define FRAME_LSB_FIRST				false
> +
> +#define DECODE_MODE_NEC				0x0
> +#define DECODE_MODE_RAW				0x2
> +#define DECODE_MODE_RC6				0x9
> +#define DECODE_MODE_XMP				0xE
> +
> +#define DECODER_STATUS_VALID			BIT(3)
> +#define DECODER_STATUS_DATA_CODE_ERR		BIT(2)
> +#define DECODER_STATUS_CUSTOM_CODE_ERR		BIT(1)
> +#define DECODER_STATUS_REPEAT			BIT(0)
> +
> +#define IRQSEL_NEC_MODE				0
> +#define IRQSEL_RISE_FALL			1
> +#define IRQSEL_FALL				2
> +#define IRQSEL_RISE				3
> +
> +#define MESON_RAW_TRATE				10	/* us */
> +#define MESON_HW_TRATE				20	/* us */
> +
> +#define MESON_IR_TIMINGS(proto, r_cnt, r_chk, r_comp, b1_e, hc, cnt_tick, ori, \
> +			 flt, len, f_max, la_max, la_min, li_max, li_min,      \
> +			 rl_max, rl_min, b0_max, b0_min, b1_max, b1_min,       \
> +			 d2_max, d2_min, d3_max, d3_min)		\
> +	{								\
> +		.hw_protocol =			proto,			\
> +		.repeat_counter_enable =	r_cnt,			\
> +		.repeat_check_enable =		r_chk,			\
> +		.repeat_compare_enable =	r_comp,			\
> +		.bit1_match_enable =		b1_e,			\
> +		.hold_code_enable =		hc,			\
> +		.count_tick_mode =		cnt_tick,		\
> +		.bit_order =			ori,			\
> +		.filter_cnt =			flt,			\
> +		.code_length =			len,			\
> +		.frame_time_max =		f_max,			\
> +		.leader_active_max =		la_max,			\
> +		.leader_active_min =		la_min,			\
> +		.leader_idle_max =		li_max,			\
> +		.leader_idle_min =		li_min,			\
> +		.repeat_leader_max =		rl_max,			\
> +		.repeat_leader_min =		rl_min,			\
> +		.bit0_max =			b0_max,			\
> +		.bit0_min =			b0_min,			\
> +		.bit1_max =			b1_max,			\
> +		.bit1_min =			b1_min,			\
> +		.duration2_max =		d2_max,			\
> +		.duration2_min =		d2_min,			\
> +		.duration3_max =		d3_max,			\
> +		.duration3_min =		d3_min,			\
> +	}								\
> +
> +/**
> + * struct meson_ir_param - describe IR Protocol parameter
> + * @hw_protocol: select IR Protocol from IR Controller.
> + * @repeat_counter_enable: enable frame-to-frame time counter, it should work
> + *	with @repeat_compare_enable to detect the repeat frame.
> + * @repeat_check_enable: enable repeat time check for repeat detection.
> + * @repeat_compare_enable: enable to compare frame for repeat frame detection.
> + *	Some IR Protocol send the same data as repeat frame. In this case,
> + *	it should work with @repeat_counter_enable to detect the repeat frame.
> + * @bit_order: bit order, LSB or MSB.
> + * @bit1_match_enable: enable to check bit 1.
> + * @hold_code_enable: hold frame code in register IR_DEC_FRAME1, the new one
> + *	frame code will not be store in IR_DEC_FRAME1. until IR_DEC_FRAME1
> + *	has been read.
> + * @count_tick_mode: increasing time unit of frame-to-frame time counter.
> + *	0 = 100us, 1 = 10us.
> + * @filter_cnt: input filter, to filter burr
> + * @code_length: length (N-1) of frame's data part.
> + * @frame_time_max: max time for whole frame. Unit: MESON_HW_TRATE
> + * @leader_active_max: max time for NEC/RC6 leader active part. Unit: MESON_HW_TRATE.
> + * @leader_active_min: min time for NEC/RC6 leader active part. Unit: MESON_HW_TRATE.
> + * @leader_idle_max: max time for NEC/RC6 leader idle part. Unit: MESON_HW_TRATE.
> + * @leader_idle_min: min time for NEC/RC6 leader idle part. Unit: MESON_HW_TRATE.
> + * @repeat_leader_max: max time for NEC repeat leader idle part. Unit: MESON_HW_TRATE.
> + * @repeat_leader_min: min time for NEC repeat leader idle part. Unit: MESON_HW_TRATE.
> + * @bit0_max: max time for NEC Logic '0', half of RC6 trailer bit, XMP Logic '00'
> + * @bit0_min: min time for NEC Logic '0', half of RC6 trailer bit, XMP Logic '00'
> + * @bit1_max: max time for NEC Logic '1', whole of RC6 trailer bit, XMP Logic '01'
> + * @bit1_min: min time for NEC Logic '1', whole of RC6 trailer bit, XMP Logic '01'
> + * @duration2_max: max time for half of RC6 normal bit, XMP Logic '10'.
> + * @duration2_min: min time for half of RC6 normal bit, XMP Logic '10'.
> + * @duration3_max: max time for whole of RC6 normal bit, XMP Logic '11'.
> + * @duration3_min: min time for whole of RC6 normal bit, XMP Logic '11'.
> + */
>   
> -#define REG0_RATE_MASK		GENMASK(11, 0)
> +struct meson_ir_param {
> +	u8		hw_protocol;
> +	bool		repeat_counter_enable;
> +	bool		repeat_check_enable;
> +	bool		repeat_compare_enable;
> +	bool		bit_order;
> +	bool		bit1_match_enable;
> +	bool		hold_code_enable;
> +	bool		count_tick_mode;
> +	u8		filter_cnt;
> +	u8		code_length;
> +	u16		frame_time_max;
> +	u16		leader_active_max;
> +	u16		leader_active_min;
> +	u16		leader_idle_max;
> +	u16		leader_idle_min;
> +	u16		repeat_leader_max;
> +	u16		repeat_leader_min;
> +	u16		bit0_max;
> +	u16		bit0_min;
> +	u16		bit1_max;
> +	u16		bit1_min;
> +	u16		duration2_max;
> +	u16		duration2_min;
> +	u16		duration3_max;
> +	u16		duration3_min;
> +};
>   
> -#define DECODE_MODE_NEC		0x0
> -#define DECODE_MODE_RAW		0x2
> +struct meson_ir {
> +	struct regmap	*reg;
> +	struct rc_dev	*rc;
> +	spinlock_t	lock;
> +	bool		support_hw_dec;
> +};
>   
> -/* Meson 6b uses REG1 to configure the mode */
> -#define REG1_MODE_MASK		GENMASK(8, 7)
> -#define REG1_MODE_SHIFT		7
> +static struct regmap_config meson_ir_regmap_config = {
> +	.reg_bits = 32,
> +	.val_bits = 32,
> +	.reg_stride = 4,
> +};
>   
> -/* Meson 8b / GXBB use REG2 to configure the mode */
> -#define REG2_MODE_MASK		GENMASK(3, 0)
> -#define REG2_MODE_SHIFT		0
> +static const struct meson_ir_param protocol_timings[] = {
> +	/* protocol, repeat counter, repeat check, repeat compare, bit 1 match */
> +	MESON_IR_TIMINGS(DECODE_MODE_NEC, false, false, false, true,
> +	/* hold code, count tick, order, filter cnt, len, frame time */
> +			 false, false, FRAME_LSB_FIRST, 7, 32, 4000,
> +	/* leader active max/min, leader idle max/min, repeat leader max/min */
> +			 500, 400, 300, 200, 150, 80,
> +	/* bit0 max/min, bit1 max/min, duration2 max/min, duration3 max/min */
> +			 72, 40, 134, 90, 0, 0, 0, 0),
> +	MESON_IR_TIMINGS(DECODE_MODE_XMP, true, false, true, false,
> +			 false, true, FRAME_MSB_FIRST, 7, 32, 1500,
> +			 0, 0, 0, 0, 0, 0,
> +			 52, 45, 86, 80, 121, 114, 7, 7),
> +	MESON_IR_TIMINGS(DECODE_MODE_RC6, true, false, true, false,
> +			 true, false, FRAME_MSB_FIRST, 7, 37, 4000,
> +			 210, 125, 50, 38, 145, 125,
> +			 51, 38, 94, 82, 28, 16, 51, 38)
> +};
>   
> -#define REG1_TIME_IV_MASK	GENMASK(28, 16)
> +static void meson_ir_rc6_handler(struct meson_ir *ir)
> +{
> +	u32 code0, code1;
>   
> -#define REG1_IRQSEL_MASK	GENMASK(3, 2)
> -#define REG1_IRQSEL_NEC_MODE	0
> -#define REG1_IRQSEL_RISE_FALL	1
> -#define REG1_IRQSEL_FALL	2
> -#define REG1_IRQSEL_RISE	3
> +	regmap_read(ir->reg, IR_DEC_FRAME, &code0);
> +	regmap_read(ir->reg, IR_DEC_FRAME1, &code1);
>   
> -#define REG1_RESET		BIT(0)
> -#define REG1_ENABLE		BIT(15)
> +	rc_keydown(ir->rc, RC_PROTO_RC6_6A_32, code0, code1 & 0x1);
> +}
>   
> -#define STATUS_IR_DEC_IN	BIT(8)
> +static void meson_ir_xmp_handler(struct meson_ir *ir)
> +{
> +	static u32 last_xmp_code;
> +	int i;
> +	u32 code = 0;
> +	u32 scancode, checksum = 0;
> +	u8 addr, subaddr, subaddr2, toggle, oem, obc1, obc2;
> +
> +	regmap_read(ir->reg, IR_DEC_FRAME, &code);
> +
> +	for (i = 0; i < 32; i += 4)
> +		checksum += ((code >> i) & 0xf);
> +	checksum = ~(checksum + 0xf - ((code >> 24) & 0xf)) & 0xf;
> +
> +	if (checksum != ((code >> 24) & 0xf)) {
> +		last_xmp_code = 0;
> +		dev_err(&ir->rc->dev, "xmp checksum error, framecode= 0x%x\n",
> +			code);
> +		return;
> +	}
>   
> -#define MESON_TRATE		10	/* us */
> +	subaddr  = (last_xmp_code >> 24 & 0xf0) | (last_xmp_code >> 20 & 0x0f);
> +	subaddr2 = (code >> 24 & 0xf0) | (code >> 16 & 0x0f);
> +	oem      = last_xmp_code >> 8;
> +	addr     = last_xmp_code;
> +	toggle   = code >> 20 & 0xf;
> +	obc1 = code >> 8;
> +	obc2 = code;
> +
> +	if (subaddr != subaddr2) {
> +		last_xmp_code = code;
> +		dev_dbg(&ir->rc->dev, "subaddress nibbles mismatch 0x%02X != 0x%02X\n",
> +			subaddr, subaddr2);
> +		return;
> +	}
> +	if (oem != 0x44)
> +		dev_dbg(&ir->rc->dev, "Warning: OEM nibbles 0x%02X. Expected 0x44\n",
> +			oem);
>   
> -struct meson_ir {
> -	void __iomem	*reg;
> -	struct rc_dev	*rc;
> -	spinlock_t	lock;
> -};
> +	scancode = addr << 24 | subaddr << 16 | obc1 << 8 | obc2;
> +	dev_dbg(&ir->rc->dev, "XMP scancode 0x%06x\n", scancode);
> +
> +	if (toggle == 0)
> +		rc_keydown(ir->rc, RC_PROTO_XMP, scancode, 0);
> +	else
> +		rc_repeat(ir->rc);
> +
> +	last_xmp_code = code;
> +}
>   
> -static void meson_ir_set_mask(struct meson_ir *ir, unsigned int reg,
> -			      u32 mask, u32 value)
> +static void meson_ir_nec_handler(struct meson_ir *ir)
>   {
> -	u32 data;
> +	u32 code = 0;
> +	u32 status = 0;
> +	enum rc_proto proto;
> +
> +	regmap_read(ir->reg, IR_DEC_STATUS, &status);
> +
> +	if (status & DECODER_STATUS_REPEAT) {
> +		rc_repeat(ir->rc);
> +	} else {
> +		regmap_read(ir->reg, IR_DEC_FRAME, &code);
>   
> -	data = readl(ir->reg + reg);
> -	data &= ~mask;
> -	data |= (value & mask);
> -	writel(data, ir->reg + reg);
> +		code = ir_nec_bytes_to_scancode(code, code >> 8,
> +						code >> 16, code >> 24, &proto);
> +		rc_keydown(ir->rc, proto, code, 0);
> +	}
>   }
>   
>   static irqreturn_t meson_ir_irq(int irqno, void *dev_id)
> +{
> +	struct meson_ir *ir = dev_id;
> +	u32 status = 0;
> +
> +	if (ir->support_hw_dec) {
> +		regmap_read(ir->reg, IR_DEC_STATUS, &status);
> +
> +		if (!(status & DECODER_STATUS_VALID))
> +			return IRQ_NONE;
> +	}
> +
> +	return IRQ_WAKE_THREAD;
> +}
> +
> +static irqreturn_t meson_ir_irq_thread(int irq, void *dev_id)
>   {
>   	struct meson_ir *ir = dev_id;
>   	u32 duration, status;
>   	struct ir_raw_event rawir = {};
>   
> -	spin_lock(&ir->lock);
> +	if (ir->support_hw_dec) {
> +		if (ir->rc->enabled_protocols & RC_PROTO_BIT_NEC)
> +			meson_ir_nec_handler(ir);
> +		else if (ir->rc->enabled_protocols & RC_PROTO_BIT_XMP)
> +			meson_ir_xmp_handler(ir);
> +		else if (ir->rc->enabled_protocols & RC_PROTO_BIT_RC6_6A_32)
> +			meson_ir_rc6_handler(ir);
> +	} else {
> +		spin_lock(&ir->lock);
>   
> -	duration = readl_relaxed(ir->reg + IR_DEC_REG1);
> -	duration = FIELD_GET(REG1_TIME_IV_MASK, duration);
> -	rawir.duration = duration * MESON_TRATE;
> +		regmap_read(ir->reg, IR_DEC_REG1, &duration);
> +		duration = FIELD_GET(IR_DEC_REG1_TIME_IV, duration);
> +		rawir.duration = duration * MESON_RAW_TRATE;
>   
> -	status = readl_relaxed(ir->reg + IR_DEC_STATUS);
> -	rawir.pulse = !!(status & STATUS_IR_DEC_IN);
> +		regmap_read(ir->reg, IR_DEC_STATUS, &status);
> +		rawir.pulse = !!(status & IR_DEC_STATUS_PULSE);
>   
> -	ir_raw_event_store_with_timeout(ir->rc, &rawir);
> +		ir_raw_event_store_with_timeout(ir->rc, &rawir);
>   
> -	spin_unlock(&ir->lock);
> +		spin_unlock(&ir->lock);
> +	}
>   
>   	return IRQ_HANDLED;
>   }
>   
> +static int meson_ir_change_hw_protocol(struct rc_dev *dev, u8 protocol)
> +{
> +	struct meson_ir *ir = dev->priv;
> +	int i;
> +	unsigned long flags;
> +	u32 regval;
> +	const struct meson_ir_param *timings;
> +
> +	for (i = 0; i < ARRAY_SIZE(protocol_timings); i++)
> +		if (protocol_timings[i].hw_protocol == protocol)
> +			break;
> +
> +	if (i == ARRAY_SIZE(protocol_timings)) {
> +		dev_err(&dev->dev, "hw protocol isn't supported: %d\n",
> +			protocol);
> +		return -EINVAL;
> +	}
> +	timings = &protocol_timings[i];
> +
> +	spin_lock_irqsave(&ir->lock, flags);
> +
> +	/* HW protocol */
> +	regval = FIELD_PREP(IR_DEC_REG2_MODE, timings->hw_protocol);
> +	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE, regval);
> +
> +	/* Monitor timing for input filter */
> +	regval = FIELD_PREP(IR_DEC_REG0_FILTER, timings->filter_cnt);
> +	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_FILTER, regval);
> +
> +	/* Hold frame data until register was read */
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_HOLD_CODE,
> +			   timings->hold_code_enable ?
> +			   IR_DEC_REG1_HOLD_CODE : 0);
> +
> +	/* Bit order */
> +	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_BIT_ORDER,
> +			   timings->bit_order ? IR_DEC_REG2_BIT_ORDER : 0);
> +
> +	/* Select tick mode */
> +	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_TICK_MODE,
> +			   timings->count_tick_mode ?
> +			   IR_DEC_REG2_TICK_MODE : 0);
> +
> +	/* Some IR formats transer the same data frame as repeat frame
> +	 * when the key is pressing..
> +	 * In this case, it could be detected as repeat frame
> +	 * if the repeat check was enabled
> +	 */
> +	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_REPEAT_COUNTER,
> +			   timings->repeat_counter_enable ?
> +			   IR_DEC_REG2_REPEAT_COUNTER : 0);
> +	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_REPEAT_TIME,
> +			   timings->repeat_check_enable ?
> +			   IR_DEC_REG2_REPEAT_TIME : 0);
> +	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_COMPARE_FRAME,
> +			   timings->repeat_compare_enable ?
> +			   IR_DEC_REG2_COMPARE_FRAME : 0);
> +
> +	/* FRAME_TIME_MAX should be large than the time between
> +	 * data frame and repeat code
> +	 */
> +	regval = FIELD_PREP(IR_DEC_REG0_FRAME_TIME_MAX,
> +			    timings->frame_time_max);
> +	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_FRAME_TIME_MAX,
> +			   regval);
> +
> +	/* Length(N-1) of frame data */
> +	regval = FIELD_PREP(IR_DEC_REG1_FRAME_LEN, timings->code_length - 1);
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_FRAME_LEN, regval);
> +
> +	/* Time for leader active part */
> +	regval = FIELD_PREP(IR_DEC_LDR_ACTIVE_MAX,
> +			    timings->leader_active_max) |
> +		 FIELD_PREP(IR_DEC_LDR_ACTIVE_MIN,
> +			    timings->leader_active_min);
> +	regmap_update_bits(ir->reg, IR_DEC_LDR_ACTIVE, IR_DEC_LDR_ACTIVE_MAX |
> +			   IR_DEC_LDR_ACTIVE_MIN, regval);
> +
> +	/* Time for leader idle part */
> +	regval = FIELD_PREP(IR_DEC_LDR_IDLE_MAX, timings->leader_idle_max) |
> +		 FIELD_PREP(IR_DEC_LDR_IDLE_MIN, timings->leader_idle_min);
> +	regmap_update_bits(ir->reg, IR_DEC_LDR_IDLE,
> +			   IR_DEC_LDR_IDLE_MAX | IR_DEC_LDR_IDLE_MIN, regval);
> +
> +	/* Time for repeat leader idle part */
> +	regval = FIELD_PREP(IR_DEC_LDR_REPEAT_MAX, timings->repeat_leader_max) |
> +		 FIELD_PREP(IR_DEC_LDR_REPEAT_MIN, timings->repeat_leader_min);
> +	regmap_update_bits(ir->reg, IR_DEC_LDR_REPEAT, IR_DEC_LDR_REPEAT_MAX |
> +			   IR_DEC_LDR_REPEAT_MIN, regval);
> +
> +	/* NEC: Time for logic '0'
> +	 * RC6: Time for half of trailer bit
> +	 */
> +	regval = FIELD_PREP(IR_DEC_BIT_0_MAX, timings->bit0_max) |
> +		 FIELD_PREP(IR_DEC_BIT_0_MIN, timings->bit0_min);
> +	regmap_update_bits(ir->reg, IR_DEC_BIT_0,
> +			   IR_DEC_BIT_0_MAX | IR_DEC_BIT_0_MIN, regval);
> +
> +	/* NEC: Time for logic '1'
> +	 * RC6: Time for whole of trailer bit
> +	 */
> +	regval = FIELD_PREP(IR_DEC_STATUS_BIT_1_MAX, timings->bit1_max) |
> +		 FIELD_PREP(IR_DEC_STATUS_BIT_1_MIN, timings->bit1_min);
> +	regmap_update_bits(ir->reg, IR_DEC_STATUS, IR_DEC_STATUS_BIT_1_MAX |
> +			   IR_DEC_STATUS_BIT_1_MIN, regval);
> +
> +	/* Enable to match logic '1' */
> +	regmap_update_bits(ir->reg, IR_DEC_STATUS, IR_DEC_STATUS_BIT_1_ENABLE,
> +			   timings->bit1_match_enable ?
> +			   IR_DEC_STATUS_BIT_1_ENABLE : 0);
> +
> +	/* NEC: Unused
> +	 * RC5/RC6: Time for halt of logic 0/1
> +	 */
> +	regval = FIELD_PREP(IR_DEC_DURATN2_MAX, timings->duration2_max) |
> +		 FIELD_PREP(IR_DEC_DURATN2_MIN, timings->duration2_min);
> +	regmap_update_bits(ir->reg, IR_DEC_DURATN2,
> +			   IR_DEC_DURATN2_MAX | IR_DEC_DURATN2_MIN, regval);
> +
> +	/* NEC: Unused
> +	 * RC5/RC6: Time for whole logic 0/1
> +	 */
> +	regval = FIELD_PREP(IR_DEC_DURATN3_MAX, timings->duration3_max) |
> +		 FIELD_PREP(IR_DEC_DURATN3_MIN, timings->duration3_min);
> +	regmap_update_bits(ir->reg, IR_DEC_DURATN3,
> +			   IR_DEC_DURATN3_MAX | IR_DEC_DURATN3_MIN, regval);
> +
> +	spin_unlock_irqrestore(&ir->lock, flags);
> +
> +	return 0;
> +}
> +
> +static void meson_ir_hw_decoder_init(struct rc_dev *dev)
> +{
> +	u32 regval;
> +	unsigned long flags;
> +	struct meson_ir *ir = dev->priv;
> +
> +	spin_lock_irqsave(&ir->lock, flags);
> +
> +	/* Clear controller status */
> +	regmap_read(ir->reg, IR_DEC_STATUS, &regval);
> +	regmap_read(ir->reg, IR_DEC_FRAME, &regval);
> +
> +	/* Reset ir decoder and disable decoder */
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
> +			   IR_DEC_REG1_RESET);
> +
> +	/* Base time resolution, (19+1)*1us=20us */
> +	regval = FIELD_PREP(IR_DEC_REG0_BASE_TIME, MESON_HW_TRATE - 1);
> +	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME, regval);
> +
> +	spin_unlock_irqrestore(&ir->lock, flags);
> +}
> +
> +static int meson_ir_change_protocol(struct rc_dev *dev, u64 *rc_type)
> +{
> +	unsigned long flags;
> +	struct meson_ir *ir = dev->priv;
> +
> +	meson_ir_hw_decoder_init(dev);
> +
> +	if (*rc_type & RC_PROTO_BIT_NEC)
> +		meson_ir_change_hw_protocol(dev, DECODE_MODE_NEC);
> +	else if (*rc_type & RC_PROTO_BIT_XMP)
> +		meson_ir_change_hw_protocol(dev, DECODE_MODE_XMP);
> +	else if (*rc_type & RC_PROTO_BIT_RC6_6A_32)
> +		meson_ir_change_hw_protocol(dev, DECODE_MODE_RC6);
> +
> +	spin_lock_irqsave(&ir->lock, flags);
> +
> +	/* Reset ir decoder and enable decode */
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
> +			   IR_DEC_REG1_RESET);
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
> +			   IR_DEC_REG1_ENABLE);
> +
> +	spin_unlock_irqrestore(&ir->lock, flags);
> +
> +	return 0;
> +}
> +
> +static void meson_ir_sw_decoder_init(struct rc_dev *dev)
> +{
> +	unsigned long flags;
> +	struct meson_ir *ir = dev->priv;
> +
> +	spin_lock_irqsave(&ir->lock, flags);
> +
> +	/* Reset the decoder */
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
> +			   IR_DEC_REG1_RESET);
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
> +
> +	/* Set general operation mode (= raw/software decoding) */
> +	if (of_device_is_compatible(dev->dev.of_node, "amlogic,meson6-ir"))
> +		regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE,
> +				   FIELD_PREP(IR_DEC_REG1_MODE,
> +					      DECODE_MODE_RAW));
> +	else
> +		regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE,
> +				   FIELD_PREP(IR_DEC_REG2_MODE,
> +					      DECODE_MODE_RAW));
> +
> +	/* Set rate */
> +	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
> +			   FIELD_PREP(IR_DEC_REG0_BASE_TIME,
> +				      MESON_RAW_TRATE - 1));
> +	/* IRQ on rising and falling edges */
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_IRQSEL,
> +			   FIELD_PREP(IR_DEC_REG1_IRQSEL, IRQSEL_RISE_FALL));
> +	/* Enable the decoder */
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
> +			   IR_DEC_REG1_ENABLE);
> +
> +	spin_unlock_irqrestore(&ir->lock, flags);
> +}
> +
> +static int meson_ir_rc_allocate_device(struct platform_device *pdev)
> +{
> +	struct meson_ir *ir = platform_get_drvdata(pdev);
> +
> +	if (ir->support_hw_dec) {
> +		ir->rc = devm_rc_allocate_device(&pdev->dev,
> +						 RC_DRIVER_SCANCODE);
> +		if (!ir->rc) {
> +			dev_err(&pdev->dev, "failed to allocate rc device\n");
> +			return -ENOMEM;
> +		}
> +
> +		ir->rc->allowed_protocols = RC_PROTO_BIT_NEC |
> +					    RC_PROTO_BIT_RC6_6A_32 |
> +					    RC_PROTO_BIT_XMP;
> +		ir->rc->change_protocol = meson_ir_change_protocol;
> +	} else {
> +		ir->rc = devm_rc_allocate_device(&pdev->dev, RC_DRIVER_IR_RAW);
> +		if (!ir->rc) {
> +			dev_err(&pdev->dev, "failed to allocate rc device\n");
> +			return -ENOMEM;
> +		}
> +
> +		ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
> +		ir->rc->rx_resolution = MESON_RAW_TRATE;
> +		ir->rc->min_timeout = 1;
> +		ir->rc->timeout = IR_DEFAULT_TIMEOUT;
> +		ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
> +	}
> +
> +	return 0;
> +}
> +
>   static int meson_ir_probe(struct platform_device *pdev)
>   {
>   	struct device *dev = &pdev->dev;
>   	struct device_node *node = dev->of_node;
> +	struct resource *res;
> +	void __iomem *res_start;
>   	const char *map_name;
>   	struct meson_ir *ir;
>   	int irq, ret;
> @@ -110,7 +622,19 @@ static int meson_ir_probe(struct platform_device *pdev)
>   	if (!ir)
>   		return -ENOMEM;
>   
> -	ir->reg = devm_platform_ioremap_resource(pdev, 0);
> +	platform_set_drvdata(pdev, ir);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (IS_ERR_OR_NULL(res)) {
> +		dev_err(&pdev->dev, "get mem resource error, %ld\n",
> +			PTR_ERR(res));
> +		return PTR_ERR(res);
> +	}
> +
> +	res_start = devm_ioremap_resource(&pdev->dev, res);
> +	meson_ir_regmap_config.max_register = resource_size(res) - 4;
> +	ir->reg = devm_regmap_init_mmio(&pdev->dev, res_start,
> +					&meson_ir_regmap_config);
>   	if (IS_ERR(ir->reg))
>   		return PTR_ERR(ir->reg);
>   
> @@ -118,27 +642,28 @@ static int meson_ir_probe(struct platform_device *pdev)
>   	if (irq < 0)
>   		return irq;
>   
> -	ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
> -	if (!ir->rc) {
> -		dev_err(dev, "failed to allocate rc device\n");
> -		return -ENOMEM;
> +	if (of_device_is_compatible(node, "amlogic,meson6-ir")) {
> +		ir->support_hw_dec = false;
> +	} else {
> +		if (of_property_read_bool(node,
> +					  "amlogic,ir-support-hw-decode"))
> +			ir->support_hw_dec = true;
> +		else
> +			ir->support_hw_dec = false;
>   	}
>   
> +	if (meson_ir_rc_allocate_device(pdev))
> +		return -ENOMEM;
> +
>   	ir->rc->priv = ir;
>   	ir->rc->device_name = DRIVER_NAME;
>   	ir->rc->input_phys = DRIVER_NAME "/input0";
>   	ir->rc->input_id.bustype = BUS_HOST;
>   	map_name = of_get_property(node, "linux,rc-map-name", NULL);
>   	ir->rc->map_name = map_name ? map_name : RC_MAP_EMPTY;
> -	ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
> -	ir->rc->rx_resolution = MESON_TRATE;
> -	ir->rc->min_timeout = 1;
> -	ir->rc->timeout = IR_DEFAULT_TIMEOUT;
> -	ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
>   	ir->rc->driver_name = DRIVER_NAME;
>   
>   	spin_lock_init(&ir->lock);
> -	platform_set_drvdata(pdev, ir);
>   
>   	ret = devm_rc_register_device(dev, ir->rc);
>   	if (ret) {
> @@ -146,33 +671,20 @@ static int meson_ir_probe(struct platform_device *pdev)
>   		return ret;
>   	}
>   
> -	ret = devm_request_irq(dev, irq, meson_ir_irq, 0, NULL, ir);
> +	if (!ir->support_hw_dec)
> +		meson_ir_sw_decoder_init(ir->rc);
> +
> +	ret = devm_request_threaded_irq(dev, irq, meson_ir_irq,
> +					meson_ir_irq_thread,
> +					IRQF_SHARED | IRQF_NO_SUSPEND,
> +					"meson_ir", ir);
>   	if (ret) {
>   		dev_err(dev, "failed to request irq\n");
>   		return ret;
>   	}
>   
> -	/* Reset the decoder */
> -	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, REG1_RESET);
> -	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, 0);
> -
> -	/* Set general operation mode (= raw/software decoding) */
> -	if (of_device_is_compatible(node, "amlogic,meson6-ir"))
> -		meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK,
> -				  FIELD_PREP(REG1_MODE_MASK, DECODE_MODE_RAW));
> -	else
> -		meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK,
> -				  FIELD_PREP(REG2_MODE_MASK, DECODE_MODE_RAW));
> -
> -	/* Set rate */
> -	meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, MESON_TRATE - 1);
> -	/* IRQ on rising and falling edges */
> -	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_IRQSEL_MASK,
> -			  FIELD_PREP(REG1_IRQSEL_MASK, REG1_IRQSEL_RISE_FALL));
> -	/* Enable the decoder */
> -	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, REG1_ENABLE);
> -
> -	dev_info(dev, "receiver initialized\n");
> +	dev_info(dev, "meson ir %s decoder was initialized\n",
> +		 ir->support_hw_dec ? "hw" : "sw");
>   
>   	return 0;
>   }
> @@ -184,7 +696,7 @@ static int meson_ir_remove(struct platform_device *pdev)
>   
>   	/* Disable the decoder */
>   	spin_lock_irqsave(&ir->lock, flags);
> -	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, 0);
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
>   	spin_unlock_irqrestore(&ir->lock, flags);
>   
>   	return 0;
> @@ -193,7 +705,6 @@ static int meson_ir_remove(struct platform_device *pdev)
>   static void meson_ir_shutdown(struct platform_device *pdev)
>   {
>   	struct device *dev = &pdev->dev;
> -	struct device_node *node = dev->of_node;
>   	struct meson_ir *ir = platform_get_drvdata(pdev);
>   	unsigned long flags;
>   
> @@ -203,27 +714,64 @@ static void meson_ir_shutdown(struct platform_device *pdev)
>   	 * Set operation mode to NEC/hardware decoding to give
>   	 * bootloader a chance to power the system back on
>   	 */
> -	if (of_device_is_compatible(node, "amlogic,meson6-ir"))
> -		meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK,
> -				  DECODE_MODE_NEC << REG1_MODE_SHIFT);
> +	if (of_device_is_compatible(dev->of_node, "amlogic,meson6-ir"))
> +		regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE,
> +				   FIELD_PREP(IR_DEC_REG1_MODE,
> +					      DECODE_MODE_NEC));
>   	else
> -		meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK,
> -				  DECODE_MODE_NEC << REG2_MODE_SHIFT);
> +		regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE,
> +				   FIELD_PREP(IR_DEC_REG2_MODE,
> +					      DECODE_MODE_NEC));
>   
>   	/* Set rate to default value */
> -	meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, 0x13);
> +	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
> +			   FIELD_PREP(IR_DEC_REG0_BASE_TIME, MESON_HW_TRATE));
>   
>   	spin_unlock_irqrestore(&ir->lock, flags);
>   }
>   
> +#ifdef CONFIG_PM
> +static int meson_ir_resume(struct device *dev)
> +{
> +	struct meson_ir *ir = dev_get_drvdata(dev);
> +
> +	if (ir->support_hw_dec)
> +		meson_ir_change_protocol(ir->rc, &ir->rc->enabled_protocols);
> +	else
> +		meson_ir_sw_decoder_init(ir->rc);
> +
> +	return 0;
> +}
> +
> +static int meson_ir_suspend(struct device *dev)
> +{
> +	struct meson_ir *ir = dev_get_drvdata(dev);
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&ir->lock, flags);
> +	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
> +	spin_unlock_irqrestore(&ir->lock, flags);
> +
> +	return 0;
> +}
> +#endif
> +
>   static const struct of_device_id meson_ir_match[] = {
>   	{ .compatible = "amlogic,meson6-ir" },
>   	{ .compatible = "amlogic,meson8b-ir" },
>   	{ .compatible = "amlogic,meson-gxbb-ir" },
> +	{ .compatible = "amlogic,meson-s4-ir" },
>   	{ },
>   };
>   MODULE_DEVICE_TABLE(of, meson_ir_match);
>   
> +#ifdef CONFIG_PM
> +static const struct dev_pm_ops meson_ir_pm_ops = {
> +	.suspend_late = meson_ir_suspend,
> +	.resume_early = meson_ir_resume,
> +};
> +#endif
> +
>   static struct platform_driver meson_ir_driver = {
>   	.probe		= meson_ir_probe,
>   	.remove		= meson_ir_remove,
> @@ -231,6 +779,9 @@ static struct platform_driver meson_ir_driver = {
>   	.driver = {
>   		.name		= DRIVER_NAME,
>   		.of_match_table	= meson_ir_match,
> +#ifdef CONFIG_PM
> +		.pm = &meson_ir_pm_ops,
> +#endif
>   	},
>   };
>   

[PATCH 1/3] media: rc: meson-ir: support rc driver type RC_DRIVER_SCANCODE

[zelong dong]

From: Zelong Dong <zelong.dong@amlogic.com>

Meson IR Controller supports hardware decoder in Meson-8B and later
SoC. So far, protocol NEC/RC-6/XMP could be decoded in hardware.
DTS property 'amlogic,ir-support-hw-decode' can enable this feature.

Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
---
 drivers/media/rc/meson-ir.c | 713 ++++++++++++++++++++++++++++++++----
 1 file changed, 632 insertions(+), 81 deletions(-)

diff --git a/drivers/media/rc/meson-ir.c b/drivers/media/rc/meson-ir.c
index 4b769111f78e..1bfdce1c1864 100644
--- a/drivers/media/rc/meson-ir.c
+++ b/drivers/media/rc/meson-ir.c
@@ -14,6 +14,7 @@
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 #include <linux/bitfield.h>
+#include <linux/regmap.h>
 
 #include <media/rc-core.h>
 
@@ -21,87 +22,598 @@
 
 /* valid on all Meson platforms */
 #define IR_DEC_LDR_ACTIVE	0x00
+	#define	IR_DEC_LDR_ACTIVE_MAX		GENMASK(28, 16)
+	#define	IR_DEC_LDR_ACTIVE_MIN		GENMASK(12, 0)
+
 #define IR_DEC_LDR_IDLE		0x04
+	#define	IR_DEC_LDR_IDLE_MAX		GENMASK(28, 16)
+	#define	IR_DEC_LDR_IDLE_MIN		GENMASK(12, 0)
+
 #define IR_DEC_LDR_REPEAT	0x08
+	#define	IR_DEC_LDR_REPEAT_MAX		GENMASK(25, 16)
+	#define	IR_DEC_LDR_REPEAT_MIN		GENMASK(9, 0)
+
 #define IR_DEC_BIT_0		0x0c
+	#define	IR_DEC_BIT_0_MAX		GENMASK(25, 16)
+	#define	IR_DEC_BIT_0_MIN		GENMASK(9, 0)
+
 #define IR_DEC_REG0		0x10
+	#define	IR_DEC_REG0_FILTER		GENMASK(30, 28)
+	#define	IR_DEC_REG0_FRAME_TIME_MAX	GENMASK(24, 12)
+	#define	IR_DEC_REG0_BASE_TIME		GENMASK(11, 0)
+
 #define IR_DEC_FRAME		0x14
+
 #define IR_DEC_STATUS		0x18
+	#define	IR_DEC_STATUS_BIT_1_ENABLE	BIT(30)
+	#define	IR_DEC_STATUS_BIT_1_MAX		GENMASK(29, 20)
+	#define	IR_DEC_STATUS_BIT_1_MIN		GENMASK(19, 10)
+	#define IR_DEC_STATUS_PULSE		BIT(8)
+	#define	IR_DEC_STATUS_BUSY		BIT(7)
+	#define	IR_DEC_STATUS_FRAME_STATUS	GENMASK(3, 0)
+
 #define IR_DEC_REG1		0x1c
-/* only available on Meson 8b and newer */
+	#define IR_DEC_REG1_TIME_IV		GENMASK(28, 16)
+	#define	IR_DEC_REG1_FRAME_LEN		GENMASK(13, 8)
+	#define IR_DEC_REG1_ENABLE		BIT(15)
+	#define	IR_DEC_REG1_HOLD_CODE		BIT(6)
+	#define IR_DEC_REG1_IRQSEL		GENMASK(3, 2)
+	#define IR_DEC_REG1_RESET		BIT(0)
+	/* Meson 6b uses REG1 to configure the mode */
+	#define IR_DEC_REG1_MODE		GENMASK(8, 7)
+
+/* The following registers are only available on Meson 8b and newer */
 #define IR_DEC_REG2		0x20
+	#define	IR_DEC_REG2_TICK_MODE		BIT(15)
+	#define	IR_DEC_REG2_REPEAT_COUNTER	BIT(13)
+	#define	IR_DEC_REG2_REPEAT_TIME		BIT(12)
+	#define	IR_DEC_REG2_COMPARE_FRAME	BIT(11)
+	#define	IR_DEC_REG2_BIT_ORDER		BIT(8)
+	/* Meson 8b / GXBB use REG2 to configure the mode */
+	#define IR_DEC_REG2_MODE		GENMASK(3, 0)
+
+#define	IR_DEC_DURATN2		0x24
+	#define	IR_DEC_DURATN2_MAX		GENMASK(25, 16)
+	#define	IR_DEC_DURATN2_MIN		GENMASK(9, 0)
+
+#define	IR_DEC_DURATN3		0x28
+	#define	IR_DEC_DURATN3_MAX		GENMASK(25, 16)
+	#define	IR_DEC_DURATN3_MIN		GENMASK(9, 0)
+
+#define	IR_DEC_FRAME1		0x2c
+
+#define FRAME_MSB_FIRST				true
+#define FRAME_LSB_FIRST				false
+
+#define DECODE_MODE_NEC				0x0
+#define DECODE_MODE_RAW				0x2
+#define DECODE_MODE_RC6				0x9
+#define DECODE_MODE_XMP				0xE
+
+#define DECODER_STATUS_VALID			BIT(3)
+#define DECODER_STATUS_DATA_CODE_ERR		BIT(2)
+#define DECODER_STATUS_CUSTOM_CODE_ERR		BIT(1)
+#define DECODER_STATUS_REPEAT			BIT(0)
+
+#define IRQSEL_NEC_MODE				0
+#define IRQSEL_RISE_FALL			1
+#define IRQSEL_FALL				2
+#define IRQSEL_RISE				3
+
+#define MESON_RAW_TRATE				10	/* us */
+#define MESON_HW_TRATE				20	/* us */
+
+#define MESON_IR_TIMINGS(proto, r_cnt, r_chk, r_comp, b1_e, hc, cnt_tick, ori, \
+			 flt, len, f_max, la_max, la_min, li_max, li_min,      \
+			 rl_max, rl_min, b0_max, b0_min, b1_max, b1_min,       \
+			 d2_max, d2_min, d3_max, d3_min)		\
+	{								\
+		.hw_protocol =			proto,			\
+		.repeat_counter_enable =	r_cnt,			\
+		.repeat_check_enable =		r_chk,			\
+		.repeat_compare_enable =	r_comp,			\
+		.bit1_match_enable =		b1_e,			\
+		.hold_code_enable =		hc,			\
+		.count_tick_mode =		cnt_tick,		\
+		.bit_order =			ori,			\
+		.filter_cnt =			flt,			\
+		.code_length =			len,			\
+		.frame_time_max =		f_max,			\
+		.leader_active_max =		la_max,			\
+		.leader_active_min =		la_min,			\
+		.leader_idle_max =		li_max,			\
+		.leader_idle_min =		li_min,			\
+		.repeat_leader_max =		rl_max,			\
+		.repeat_leader_min =		rl_min,			\
+		.bit0_max =			b0_max,			\
+		.bit0_min =			b0_min,			\
+		.bit1_max =			b1_max,			\
+		.bit1_min =			b1_min,			\
+		.duration2_max =		d2_max,			\
+		.duration2_min =		d2_min,			\
+		.duration3_max =		d3_max,			\
+		.duration3_min =		d3_min,			\
+	}								\
+
+/**
+ * struct meson_ir_param - describe IR Protocol parameter
+ * @hw_protocol: select IR Protocol from IR Controller.
+ * @repeat_counter_enable: enable frame-to-frame time counter, it should work
+ *	with @repeat_compare_enable to detect the repeat frame.
+ * @repeat_check_enable: enable repeat time check for repeat detection.
+ * @repeat_compare_enable: enable to compare frame for repeat frame detection.
+ *	Some IR Protocol send the same data as repeat frame. In this case,
+ *	it should work with @repeat_counter_enable to detect the repeat frame.
+ * @bit_order: bit order, LSB or MSB.
+ * @bit1_match_enable: enable to check bit 1.
+ * @hold_code_enable: hold frame code in register IR_DEC_FRAME1, the new one
+ *	frame code will not be store in IR_DEC_FRAME1. until IR_DEC_FRAME1
+ *	has been read.
+ * @count_tick_mode: increasing time unit of frame-to-frame time counter.
+ *	0 = 100us, 1 = 10us.
+ * @filter_cnt: input filter, to filter burr
+ * @code_length: length (N-1) of frame's data part.
+ * @frame_time_max: max time for whole frame. Unit: MESON_HW_TRATE
+ * @leader_active_max: max time for NEC/RC6 leader active part. Unit: MESON_HW_TRATE.
+ * @leader_active_min: min time for NEC/RC6 leader active part. Unit: MESON_HW_TRATE.
+ * @leader_idle_max: max time for NEC/RC6 leader idle part. Unit: MESON_HW_TRATE.
+ * @leader_idle_min: min time for NEC/RC6 leader idle part. Unit: MESON_HW_TRATE.
+ * @repeat_leader_max: max time for NEC repeat leader idle part. Unit: MESON_HW_TRATE.
+ * @repeat_leader_min: min time for NEC repeat leader idle part. Unit: MESON_HW_TRATE.
+ * @bit0_max: max time for NEC Logic '0', half of RC6 trailer bit, XMP Logic '00'
+ * @bit0_min: min time for NEC Logic '0', half of RC6 trailer bit, XMP Logic '00'
+ * @bit1_max: max time for NEC Logic '1', whole of RC6 trailer bit, XMP Logic '01'
+ * @bit1_min: min time for NEC Logic '1', whole of RC6 trailer bit, XMP Logic '01'
+ * @duration2_max: max time for half of RC6 normal bit, XMP Logic '10'.
+ * @duration2_min: min time for half of RC6 normal bit, XMP Logic '10'.
+ * @duration3_max: max time for whole of RC6 normal bit, XMP Logic '11'.
+ * @duration3_min: min time for whole of RC6 normal bit, XMP Logic '11'.
+ */
 
-#define REG0_RATE_MASK		GENMASK(11, 0)
+struct meson_ir_param {
+	u8		hw_protocol;
+	bool		repeat_counter_enable;
+	bool		repeat_check_enable;
+	bool		repeat_compare_enable;
+	bool		bit_order;
+	bool		bit1_match_enable;
+	bool		hold_code_enable;
+	bool		count_tick_mode;
+	u8		filter_cnt;
+	u8		code_length;
+	u16		frame_time_max;
+	u16		leader_active_max;
+	u16		leader_active_min;
+	u16		leader_idle_max;
+	u16		leader_idle_min;
+	u16		repeat_leader_max;
+	u16		repeat_leader_min;
+	u16		bit0_max;
+	u16		bit0_min;
+	u16		bit1_max;
+	u16		bit1_min;
+	u16		duration2_max;
+	u16		duration2_min;
+	u16		duration3_max;
+	u16		duration3_min;
+};
 
-#define DECODE_MODE_NEC		0x0
-#define DECODE_MODE_RAW		0x2
+struct meson_ir {
+	struct regmap	*reg;
+	struct rc_dev	*rc;
+	spinlock_t	lock;
+	bool		support_hw_dec;
+};
 
-/* Meson 6b uses REG1 to configure the mode */
-#define REG1_MODE_MASK		GENMASK(8, 7)
-#define REG1_MODE_SHIFT		7
+static struct regmap_config meson_ir_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+};
 
-/* Meson 8b / GXBB use REG2 to configure the mode */
-#define REG2_MODE_MASK		GENMASK(3, 0)
-#define REG2_MODE_SHIFT		0
+static const struct meson_ir_param protocol_timings[] = {
+	/* protocol, repeat counter, repeat check, repeat compare, bit 1 match */
+	MESON_IR_TIMINGS(DECODE_MODE_NEC, false, false, false, true,
+	/* hold code, count tick, order, filter cnt, len, frame time */
+			 false, false, FRAME_LSB_FIRST, 7, 32, 4000,
+	/* leader active max/min, leader idle max/min, repeat leader max/min */
+			 500, 400, 300, 200, 150, 80,
+	/* bit0 max/min, bit1 max/min, duration2 max/min, duration3 max/min */
+			 72, 40, 134, 90, 0, 0, 0, 0),
+	MESON_IR_TIMINGS(DECODE_MODE_XMP, true, false, true, false,
+			 false, true, FRAME_MSB_FIRST, 7, 32, 1500,
+			 0, 0, 0, 0, 0, 0,
+			 52, 45, 86, 80, 121, 114, 7, 7),
+	MESON_IR_TIMINGS(DECODE_MODE_RC6, true, false, true, false,
+			 true, false, FRAME_MSB_FIRST, 7, 37, 4000,
+			 210, 125, 50, 38, 145, 125,
+			 51, 38, 94, 82, 28, 16, 51, 38)
+};
 
-#define REG1_TIME_IV_MASK	GENMASK(28, 16)
+static void meson_ir_rc6_handler(struct meson_ir *ir)
+{
+	u32 code0, code1;
 
-#define REG1_IRQSEL_MASK	GENMASK(3, 2)
-#define REG1_IRQSEL_NEC_MODE	0
-#define REG1_IRQSEL_RISE_FALL	1
-#define REG1_IRQSEL_FALL	2
-#define REG1_IRQSEL_RISE	3
+	regmap_read(ir->reg, IR_DEC_FRAME, &code0);
+	regmap_read(ir->reg, IR_DEC_FRAME1, &code1);
 
-#define REG1_RESET		BIT(0)
-#define REG1_ENABLE		BIT(15)
+	rc_keydown(ir->rc, RC_PROTO_RC6_6A_32, code0, code1 & 0x1);
+}
 
-#define STATUS_IR_DEC_IN	BIT(8)
+static void meson_ir_xmp_handler(struct meson_ir *ir)
+{
+	static u32 last_xmp_code;
+	int i;
+	u32 code = 0;
+	u32 scancode, checksum = 0;
+	u8 addr, subaddr, subaddr2, toggle, oem, obc1, obc2;
+
+	regmap_read(ir->reg, IR_DEC_FRAME, &code);
+
+	for (i = 0; i < 32; i += 4)
+		checksum += ((code >> i) & 0xf);
+	checksum = ~(checksum + 0xf - ((code >> 24) & 0xf)) & 0xf;
+
+	if (checksum != ((code >> 24) & 0xf)) {
+		last_xmp_code = 0;
+		dev_err(&ir->rc->dev, "xmp checksum error, framecode= 0x%x\n",
+			code);
+		return;
+	}
 
-#define MESON_TRATE		10	/* us */
+	subaddr  = (last_xmp_code >> 24 & 0xf0) | (last_xmp_code >> 20 & 0x0f);
+	subaddr2 = (code >> 24 & 0xf0) | (code >> 16 & 0x0f);
+	oem      = last_xmp_code >> 8;
+	addr     = last_xmp_code;
+	toggle   = code >> 20 & 0xf;
+	obc1 = code >> 8;
+	obc2 = code;
+
+	if (subaddr != subaddr2) {
+		last_xmp_code = code;
+		dev_dbg(&ir->rc->dev, "subaddress nibbles mismatch 0x%02X != 0x%02X\n",
+			subaddr, subaddr2);
+		return;
+	}
+	if (oem != 0x44)
+		dev_dbg(&ir->rc->dev, "Warning: OEM nibbles 0x%02X. Expected 0x44\n",
+			oem);
 
-struct meson_ir {
-	void __iomem	*reg;
-	struct rc_dev	*rc;
-	spinlock_t	lock;
-};
+	scancode = addr << 24 | subaddr << 16 | obc1 << 8 | obc2;
+	dev_dbg(&ir->rc->dev, "XMP scancode 0x%06x\n", scancode);
+
+	if (toggle == 0)
+		rc_keydown(ir->rc, RC_PROTO_XMP, scancode, 0);
+	else
+		rc_repeat(ir->rc);
+
+	last_xmp_code = code;
+}
 
-static void meson_ir_set_mask(struct meson_ir *ir, unsigned int reg,
-			      u32 mask, u32 value)
+static void meson_ir_nec_handler(struct meson_ir *ir)
 {
-	u32 data;
+	u32 code = 0;
+	u32 status = 0;
+	enum rc_proto proto;
+
+	regmap_read(ir->reg, IR_DEC_STATUS, &status);
+
+	if (status & DECODER_STATUS_REPEAT) {
+		rc_repeat(ir->rc);
+	} else {
+		regmap_read(ir->reg, IR_DEC_FRAME, &code);
 
-	data = readl(ir->reg + reg);
-	data &= ~mask;
-	data |= (value & mask);
-	writel(data, ir->reg + reg);
+		code = ir_nec_bytes_to_scancode(code, code >> 8,
+						code >> 16, code >> 24, &proto);
+		rc_keydown(ir->rc, proto, code, 0);
+	}
 }
 
 static irqreturn_t meson_ir_irq(int irqno, void *dev_id)
+{
+	struct meson_ir *ir = dev_id;
+	u32 status = 0;
+
+	if (ir->support_hw_dec) {
+		regmap_read(ir->reg, IR_DEC_STATUS, &status);
+
+		if (!(status & DECODER_STATUS_VALID))
+			return IRQ_NONE;
+	}
+
+	return IRQ_WAKE_THREAD;
+}
+
+static irqreturn_t meson_ir_irq_thread(int irq, void *dev_id)
 {
 	struct meson_ir *ir = dev_id;
 	u32 duration, status;
 	struct ir_raw_event rawir = {};
 
-	spin_lock(&ir->lock);
+	if (ir->support_hw_dec) {
+		if (ir->rc->enabled_protocols & RC_PROTO_BIT_NEC)
+			meson_ir_nec_handler(ir);
+		else if (ir->rc->enabled_protocols & RC_PROTO_BIT_XMP)
+			meson_ir_xmp_handler(ir);
+		else if (ir->rc->enabled_protocols & RC_PROTO_BIT_RC6_6A_32)
+			meson_ir_rc6_handler(ir);
+	} else {
+		spin_lock(&ir->lock);
 
-	duration = readl_relaxed(ir->reg + IR_DEC_REG1);
-	duration = FIELD_GET(REG1_TIME_IV_MASK, duration);
-	rawir.duration = duration * MESON_TRATE;
+		regmap_read(ir->reg, IR_DEC_REG1, &duration);
+		duration = FIELD_GET(IR_DEC_REG1_TIME_IV, duration);
+		rawir.duration = duration * MESON_RAW_TRATE;
 
-	status = readl_relaxed(ir->reg + IR_DEC_STATUS);
-	rawir.pulse = !!(status & STATUS_IR_DEC_IN);
+		regmap_read(ir->reg, IR_DEC_STATUS, &status);
+		rawir.pulse = !!(status & IR_DEC_STATUS_PULSE);
 
-	ir_raw_event_store_with_timeout(ir->rc, &rawir);
+		ir_raw_event_store_with_timeout(ir->rc, &rawir);
 
-	spin_unlock(&ir->lock);
+		spin_unlock(&ir->lock);
+	}
 
 	return IRQ_HANDLED;
 }
 
+static int meson_ir_change_hw_protocol(struct rc_dev *dev, u8 protocol)
+{
+	struct meson_ir *ir = dev->priv;
+	int i;
+	unsigned long flags;
+	u32 regval;
+	const struct meson_ir_param *timings;
+
+	for (i = 0; i < ARRAY_SIZE(protocol_timings); i++)
+		if (protocol_timings[i].hw_protocol == protocol)
+			break;
+
+	if (i == ARRAY_SIZE(protocol_timings)) {
+		dev_err(&dev->dev, "hw protocol isn't supported: %d\n",
+			protocol);
+		return -EINVAL;
+	}
+	timings = &protocol_timings[i];
+
+	spin_lock_irqsave(&ir->lock, flags);
+
+	/* HW protocol */
+	regval = FIELD_PREP(IR_DEC_REG2_MODE, timings->hw_protocol);
+	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE, regval);
+
+	/* Monitor timing for input filter */
+	regval = FIELD_PREP(IR_DEC_REG0_FILTER, timings->filter_cnt);
+	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_FILTER, regval);
+
+	/* Hold frame data until register was read */
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_HOLD_CODE,
+			   timings->hold_code_enable ?
+			   IR_DEC_REG1_HOLD_CODE : 0);
+
+	/* Bit order */
+	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_BIT_ORDER,
+			   timings->bit_order ? IR_DEC_REG2_BIT_ORDER : 0);
+
+	/* Select tick mode */
+	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_TICK_MODE,
+			   timings->count_tick_mode ?
+			   IR_DEC_REG2_TICK_MODE : 0);
+
+	/* Some IR formats transer the same data frame as repeat frame
+	 * when the key is pressing..
+	 * In this case, it could be detected as repeat frame
+	 * if the repeat check was enabled
+	 */
+	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_REPEAT_COUNTER,
+			   timings->repeat_counter_enable ?
+			   IR_DEC_REG2_REPEAT_COUNTER : 0);
+	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_REPEAT_TIME,
+			   timings->repeat_check_enable ?
+			   IR_DEC_REG2_REPEAT_TIME : 0);
+	regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_COMPARE_FRAME,
+			   timings->repeat_compare_enable ?
+			   IR_DEC_REG2_COMPARE_FRAME : 0);
+
+	/* FRAME_TIME_MAX should be large than the time between
+	 * data frame and repeat code
+	 */
+	regval = FIELD_PREP(IR_DEC_REG0_FRAME_TIME_MAX,
+			    timings->frame_time_max);
+	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_FRAME_TIME_MAX,
+			   regval);
+
+	/* Length(N-1) of frame data */
+	regval = FIELD_PREP(IR_DEC_REG1_FRAME_LEN, timings->code_length - 1);
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_FRAME_LEN, regval);
+
+	/* Time for leader active part */
+	regval = FIELD_PREP(IR_DEC_LDR_ACTIVE_MAX,
+			    timings->leader_active_max) |
+		 FIELD_PREP(IR_DEC_LDR_ACTIVE_MIN,
+			    timings->leader_active_min);
+	regmap_update_bits(ir->reg, IR_DEC_LDR_ACTIVE, IR_DEC_LDR_ACTIVE_MAX |
+			   IR_DEC_LDR_ACTIVE_MIN, regval);
+
+	/* Time for leader idle part */
+	regval = FIELD_PREP(IR_DEC_LDR_IDLE_MAX, timings->leader_idle_max) |
+		 FIELD_PREP(IR_DEC_LDR_IDLE_MIN, timings->leader_idle_min);
+	regmap_update_bits(ir->reg, IR_DEC_LDR_IDLE,
+			   IR_DEC_LDR_IDLE_MAX | IR_DEC_LDR_IDLE_MIN, regval);
+
+	/* Time for repeat leader idle part */
+	regval = FIELD_PREP(IR_DEC_LDR_REPEAT_MAX, timings->repeat_leader_max) |
+		 FIELD_PREP(IR_DEC_LDR_REPEAT_MIN, timings->repeat_leader_min);
+	regmap_update_bits(ir->reg, IR_DEC_LDR_REPEAT, IR_DEC_LDR_REPEAT_MAX |
+			   IR_DEC_LDR_REPEAT_MIN, regval);
+
+	/* NEC: Time for logic '0'
+	 * RC6: Time for half of trailer bit
+	 */
+	regval = FIELD_PREP(IR_DEC_BIT_0_MAX, timings->bit0_max) |
+		 FIELD_PREP(IR_DEC_BIT_0_MIN, timings->bit0_min);
+	regmap_update_bits(ir->reg, IR_DEC_BIT_0,
+			   IR_DEC_BIT_0_MAX | IR_DEC_BIT_0_MIN, regval);
+
+	/* NEC: Time for logic '1'
+	 * RC6: Time for whole of trailer bit
+	 */
+	regval = FIELD_PREP(IR_DEC_STATUS_BIT_1_MAX, timings->bit1_max) |
+		 FIELD_PREP(IR_DEC_STATUS_BIT_1_MIN, timings->bit1_min);
+	regmap_update_bits(ir->reg, IR_DEC_STATUS, IR_DEC_STATUS_BIT_1_MAX |
+			   IR_DEC_STATUS_BIT_1_MIN, regval);
+
+	/* Enable to match logic '1' */
+	regmap_update_bits(ir->reg, IR_DEC_STATUS, IR_DEC_STATUS_BIT_1_ENABLE,
+			   timings->bit1_match_enable ?
+			   IR_DEC_STATUS_BIT_1_ENABLE : 0);
+
+	/* NEC: Unused
+	 * RC5/RC6: Time for halt of logic 0/1
+	 */
+	regval = FIELD_PREP(IR_DEC_DURATN2_MAX, timings->duration2_max) |
+		 FIELD_PREP(IR_DEC_DURATN2_MIN, timings->duration2_min);
+	regmap_update_bits(ir->reg, IR_DEC_DURATN2,
+			   IR_DEC_DURATN2_MAX | IR_DEC_DURATN2_MIN, regval);
+
+	/* NEC: Unused
+	 * RC5/RC6: Time for whole logic 0/1
+	 */
+	regval = FIELD_PREP(IR_DEC_DURATN3_MAX, timings->duration3_max) |
+		 FIELD_PREP(IR_DEC_DURATN3_MIN, timings->duration3_min);
+	regmap_update_bits(ir->reg, IR_DEC_DURATN3,
+			   IR_DEC_DURATN3_MAX | IR_DEC_DURATN3_MIN, regval);
+
+	spin_unlock_irqrestore(&ir->lock, flags);
+
+	return 0;
+}
+
+static void meson_ir_hw_decoder_init(struct rc_dev *dev)
+{
+	u32 regval;
+	unsigned long flags;
+	struct meson_ir *ir = dev->priv;
+
+	spin_lock_irqsave(&ir->lock, flags);
+
+	/* Clear controller status */
+	regmap_read(ir->reg, IR_DEC_STATUS, &regval);
+	regmap_read(ir->reg, IR_DEC_FRAME, &regval);
+
+	/* Reset ir decoder and disable decoder */
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
+			   IR_DEC_REG1_RESET);
+
+	/* Base time resolution, (19+1)*1us=20us */
+	regval = FIELD_PREP(IR_DEC_REG0_BASE_TIME, MESON_HW_TRATE - 1);
+	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME, regval);
+
+	spin_unlock_irqrestore(&ir->lock, flags);
+}
+
+static int meson_ir_change_protocol(struct rc_dev *dev, u64 *rc_type)
+{
+	unsigned long flags;
+	struct meson_ir *ir = dev->priv;
+
+	meson_ir_hw_decoder_init(dev);
+
+	if (*rc_type & RC_PROTO_BIT_NEC)
+		meson_ir_change_hw_protocol(dev, DECODE_MODE_NEC);
+	else if (*rc_type & RC_PROTO_BIT_XMP)
+		meson_ir_change_hw_protocol(dev, DECODE_MODE_XMP);
+	else if (*rc_type & RC_PROTO_BIT_RC6_6A_32)
+		meson_ir_change_hw_protocol(dev, DECODE_MODE_RC6);
+
+	spin_lock_irqsave(&ir->lock, flags);
+
+	/* Reset ir decoder and enable decode */
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
+			   IR_DEC_REG1_RESET);
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
+			   IR_DEC_REG1_ENABLE);
+
+	spin_unlock_irqrestore(&ir->lock, flags);
+
+	return 0;
+}
+
+static void meson_ir_sw_decoder_init(struct rc_dev *dev)
+{
+	unsigned long flags;
+	struct meson_ir *ir = dev->priv;
+
+	spin_lock_irqsave(&ir->lock, flags);
+
+	/* Reset the decoder */
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
+			   IR_DEC_REG1_RESET);
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
+
+	/* Set general operation mode (= raw/software decoding) */
+	if (of_device_is_compatible(dev->dev.of_node, "amlogic,meson6-ir"))
+		regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE,
+				   FIELD_PREP(IR_DEC_REG1_MODE,
+					      DECODE_MODE_RAW));
+	else
+		regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE,
+				   FIELD_PREP(IR_DEC_REG2_MODE,
+					      DECODE_MODE_RAW));
+
+	/* Set rate */
+	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
+			   FIELD_PREP(IR_DEC_REG0_BASE_TIME,
+				      MESON_RAW_TRATE - 1));
+	/* IRQ on rising and falling edges */
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_IRQSEL,
+			   FIELD_PREP(IR_DEC_REG1_IRQSEL, IRQSEL_RISE_FALL));
+	/* Enable the decoder */
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
+			   IR_DEC_REG1_ENABLE);
+
+	spin_unlock_irqrestore(&ir->lock, flags);
+}
+
+static int meson_ir_rc_allocate_device(struct platform_device *pdev)
+{
+	struct meson_ir *ir = platform_get_drvdata(pdev);
+
+	if (ir->support_hw_dec) {
+		ir->rc = devm_rc_allocate_device(&pdev->dev,
+						 RC_DRIVER_SCANCODE);
+		if (!ir->rc) {
+			dev_err(&pdev->dev, "failed to allocate rc device\n");
+			return -ENOMEM;
+		}
+
+		ir->rc->allowed_protocols = RC_PROTO_BIT_NEC |
+					    RC_PROTO_BIT_RC6_6A_32 |
+					    RC_PROTO_BIT_XMP;
+		ir->rc->change_protocol = meson_ir_change_protocol;
+	} else {
+		ir->rc = devm_rc_allocate_device(&pdev->dev, RC_DRIVER_IR_RAW);
+		if (!ir->rc) {
+			dev_err(&pdev->dev, "failed to allocate rc device\n");
+			return -ENOMEM;
+		}
+
+		ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
+		ir->rc->rx_resolution = MESON_RAW_TRATE;
+		ir->rc->min_timeout = 1;
+		ir->rc->timeout = IR_DEFAULT_TIMEOUT;
+		ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
+	}
+
+	return 0;
+}
+
 static int meson_ir_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *node = dev->of_node;
+	struct resource *res;
+	void __iomem *res_start;
 	const char *map_name;
 	struct meson_ir *ir;
 	int irq, ret;
@@ -110,7 +622,19 @@ static int meson_ir_probe(struct platform_device *pdev)
 	if (!ir)
 		return -ENOMEM;
 
-	ir->reg = devm_platform_ioremap_resource(pdev, 0);
+	platform_set_drvdata(pdev, ir);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (IS_ERR_OR_NULL(res)) {
+		dev_err(&pdev->dev, "get mem resource error, %ld\n",
+			PTR_ERR(res));
+		return PTR_ERR(res);
+	}
+
+	res_start = devm_ioremap_resource(&pdev->dev, res);
+	meson_ir_regmap_config.max_register = resource_size(res) - 4;
+	ir->reg = devm_regmap_init_mmio(&pdev->dev, res_start,
+					&meson_ir_regmap_config);
 	if (IS_ERR(ir->reg))
 		return PTR_ERR(ir->reg);
 
@@ -118,27 +642,28 @@ static int meson_ir_probe(struct platform_device *pdev)
 	if (irq < 0)
 		return irq;
 
-	ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
-	if (!ir->rc) {
-		dev_err(dev, "failed to allocate rc device\n");
-		return -ENOMEM;
+	if (of_device_is_compatible(node, "amlogic,meson6-ir")) {
+		ir->support_hw_dec = false;
+	} else {
+		if (of_property_read_bool(node,
+					  "amlogic,ir-support-hw-decode"))
+			ir->support_hw_dec = true;
+		else
+			ir->support_hw_dec = false;
 	}
 
+	if (meson_ir_rc_allocate_device(pdev))
+		return -ENOMEM;
+
 	ir->rc->priv = ir;
 	ir->rc->device_name = DRIVER_NAME;
 	ir->rc->input_phys = DRIVER_NAME "/input0";
 	ir->rc->input_id.bustype = BUS_HOST;
 	map_name = of_get_property(node, "linux,rc-map-name", NULL);
 	ir->rc->map_name = map_name ? map_name : RC_MAP_EMPTY;
-	ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
-	ir->rc->rx_resolution = MESON_TRATE;
-	ir->rc->min_timeout = 1;
-	ir->rc->timeout = IR_DEFAULT_TIMEOUT;
-	ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
 	ir->rc->driver_name = DRIVER_NAME;
 
 	spin_lock_init(&ir->lock);
-	platform_set_drvdata(pdev, ir);
 
 	ret = devm_rc_register_device(dev, ir->rc);
 	if (ret) {
@@ -146,33 +671,20 @@ static int meson_ir_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	ret = devm_request_irq(dev, irq, meson_ir_irq, 0, NULL, ir);
+	if (!ir->support_hw_dec)
+		meson_ir_sw_decoder_init(ir->rc);
+
+	ret = devm_request_threaded_irq(dev, irq, meson_ir_irq,
+					meson_ir_irq_thread,
+					IRQF_SHARED | IRQF_NO_SUSPEND,
+					"meson_ir", ir);
 	if (ret) {
 		dev_err(dev, "failed to request irq\n");
 		return ret;
 	}
 
-	/* Reset the decoder */
-	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, REG1_RESET);
-	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, 0);
-
-	/* Set general operation mode (= raw/software decoding) */
-	if (of_device_is_compatible(node, "amlogic,meson6-ir"))
-		meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK,
-				  FIELD_PREP(REG1_MODE_MASK, DECODE_MODE_RAW));
-	else
-		meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK,
-				  FIELD_PREP(REG2_MODE_MASK, DECODE_MODE_RAW));
-
-	/* Set rate */
-	meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, MESON_TRATE - 1);
-	/* IRQ on rising and falling edges */
-	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_IRQSEL_MASK,
-			  FIELD_PREP(REG1_IRQSEL_MASK, REG1_IRQSEL_RISE_FALL));
-	/* Enable the decoder */
-	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, REG1_ENABLE);
-
-	dev_info(dev, "receiver initialized\n");
+	dev_info(dev, "meson ir %s decoder was initialized\n",
+		 ir->support_hw_dec ? "hw" : "sw");
 
 	return 0;
 }
@@ -184,7 +696,7 @@ static int meson_ir_remove(struct platform_device *pdev)
 
 	/* Disable the decoder */
 	spin_lock_irqsave(&ir->lock, flags);
-	meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, 0);
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
 	spin_unlock_irqrestore(&ir->lock, flags);
 
 	return 0;
@@ -193,7 +705,6 @@ static int meson_ir_remove(struct platform_device *pdev)
 static void meson_ir_shutdown(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
-	struct device_node *node = dev->of_node;
 	struct meson_ir *ir = platform_get_drvdata(pdev);
 	unsigned long flags;
 
@@ -203,27 +714,64 @@ static void meson_ir_shutdown(struct platform_device *pdev)
 	 * Set operation mode to NEC/hardware decoding to give
 	 * bootloader a chance to power the system back on
 	 */
-	if (of_device_is_compatible(node, "amlogic,meson6-ir"))
-		meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK,
-				  DECODE_MODE_NEC << REG1_MODE_SHIFT);
+	if (of_device_is_compatible(dev->of_node, "amlogic,meson6-ir"))
+		regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE,
+				   FIELD_PREP(IR_DEC_REG1_MODE,
+					      DECODE_MODE_NEC));
 	else
-		meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK,
-				  DECODE_MODE_NEC << REG2_MODE_SHIFT);
+		regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE,
+				   FIELD_PREP(IR_DEC_REG2_MODE,
+					      DECODE_MODE_NEC));
 
 	/* Set rate to default value */
-	meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, 0x13);
+	regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
+			   FIELD_PREP(IR_DEC_REG0_BASE_TIME, MESON_HW_TRATE));
 
 	spin_unlock_irqrestore(&ir->lock, flags);
 }
 
+#ifdef CONFIG_PM
+static int meson_ir_resume(struct device *dev)
+{
+	struct meson_ir *ir = dev_get_drvdata(dev);
+
+	if (ir->support_hw_dec)
+		meson_ir_change_protocol(ir->rc, &ir->rc->enabled_protocols);
+	else
+		meson_ir_sw_decoder_init(ir->rc);
+
+	return 0;
+}
+
+static int meson_ir_suspend(struct device *dev)
+{
+	struct meson_ir *ir = dev_get_drvdata(dev);
+	unsigned long flags;
+
+	spin_lock_irqsave(&ir->lock, flags);
+	regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
+	spin_unlock_irqrestore(&ir->lock, flags);
+
+	return 0;
+}
+#endif
+
 static const struct of_device_id meson_ir_match[] = {
 	{ .compatible = "amlogic,meson6-ir" },
 	{ .compatible = "amlogic,meson8b-ir" },
 	{ .compatible = "amlogic,meson-gxbb-ir" },
+	{ .compatible = "amlogic,meson-s4-ir" },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, meson_ir_match);
 
+#ifdef CONFIG_PM
+static const struct dev_pm_ops meson_ir_pm_ops = {
+	.suspend_late = meson_ir_suspend,
+	.resume_early = meson_ir_resume,
+};
+#endif
+
 static struct platform_driver meson_ir_driver = {
 	.probe		= meson_ir_probe,
 	.remove		= meson_ir_remove,
@@ -231,6 +779,9 @@ static struct platform_driver meson_ir_driver = {
 	.driver = {
 		.name		= DRIVER_NAME,
 		.of_match_table	= meson_ir_match,
+#ifdef CONFIG_PM
+		.pm = &meson_ir_pm_ops,
+#endif
 	},
 };
 
-- 
2.35.1