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* [PATCH 2/8] scsi: ufs: set load before setting voltage in regulators
       [not found] <1580972212-29881-1-git-send-email-cang@codeaurora.org>
@ 2020-02-06  6:56 ` Can Guo
  2020-02-06  6:56 ` [PATCH 3/8] scsi: ufs: Remove the check before call setup clock notify vops Can Guo
  2020-02-06  6:56 ` [PATCH 5/8] scsi: ufs: Fix ufshcd_hold() caused scheduling while atomic Can Guo
  2 siblings, 0 replies; 3+ messages in thread
From: Can Guo @ 2020-02-06  6:56 UTC (permalink / raw)
  To: asutoshd, nguyenb, hongwus, rnayak, linux-scsi, kernel-team,
	saravanak, salyzyn, cang
  Cc: Bart Van Assche, Martin K. Petersen, Venkat Gopalakrishnan,
	James E.J. Bottomley, open list, Avri Altman,
	moderated list:ARM/Mediatek SoC support, Alim Akhtar,
	Matthias Brugger, Tomas Winkler, Stanley Chu,
	moderated list:ARM/Mediatek SoC support, Bean Huo

From: Asutosh Das <asutoshd@codeaurora.org>

This sequence change is required to avoid dips in voltage
during boot-up.

Apparently, this dip is caused because in the original
sequence, the regulators are initialized in lpm mode.
And then when the load is set to high, and more current
is drawn, than is allowed in lpm, the dip is seen.

Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Can Guo <cang@codeaurora.org>
Reviewed-by: Hongwu Su <hongwus@codeaurora.org>
Reviewed-by: Bean Huo <beanhuo@micron.com>
Reviewed-by: Stanley Chu <stanley.chu@mediatek.com>

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 10dbc0c..83ae093 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -7248,6 +7248,11 @@ static int ufshcd_config_vreg(struct device *dev,
 	name = vreg->name;
 
 	if (regulator_count_voltages(reg) > 0) {
+		uA_load = on ? vreg->max_uA : 0;
+		ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
+		if (ret)
+			goto out;
+
 		if (vreg->min_uV && vreg->max_uV) {
 			min_uV = on ? vreg->min_uV : 0;
 			ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
@@ -7258,11 +7263,6 @@ static int ufshcd_config_vreg(struct device *dev,
 				goto out;
 			}
 		}
-
-		uA_load = on ? vreg->max_uA : 0;
-		ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
-		if (ret)
-			goto out;
 	}
 out:
 	return ret;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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^ permalink raw reply related	[flat|nested] 3+ messages in thread

* [PATCH 3/8] scsi: ufs: Remove the check before call setup clock notify vops
       [not found] <1580972212-29881-1-git-send-email-cang@codeaurora.org>
  2020-02-06  6:56 ` [PATCH 2/8] scsi: ufs: set load before setting voltage in regulators Can Guo
@ 2020-02-06  6:56 ` Can Guo
  2020-02-06  6:56 ` [PATCH 5/8] scsi: ufs: Fix ufshcd_hold() caused scheduling while atomic Can Guo
  2 siblings, 0 replies; 3+ messages in thread
From: Can Guo @ 2020-02-06  6:56 UTC (permalink / raw)
  To: asutoshd, nguyenb, hongwus, rnayak, linux-scsi, kernel-team,
	saravanak, salyzyn, cang
  Cc: Bart Van Assche, Martin K. Petersen, Venkat Gopalakrishnan,
	James E.J. Bottomley, open list, Avri Altman,
	moderated list:ARM/Mediatek SoC support, Alim Akhtar,
	Matthias Brugger, Tomas Winkler, Stanley Chu,
	moderated list:ARM/Mediatek SoC support, Bean Huo

The functionality of vendor specific ops should be handled properly in
platform specific driver, but should not count on the UFS driver.

Signed-off-by: Can Guo <cang@codeaurora.org>
Reviewed-by: Bean Huo <beanhuo@micron.com>
Reviewed-by: Stanley Chu <stanley.chu@mediatek.com>

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 83ae093..bbc2607 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -7402,16 +7402,9 @@ static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
 	if (list_empty(head))
 		goto out;
 
-	/*
-	 * vendor specific setup_clocks ops may depend on clocks managed by
-	 * this standard driver hence call the vendor specific setup_clocks
-	 * before disabling the clocks managed here.
-	 */
-	if (!on) {
-		ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
-		if (ret)
-			return ret;
-	}
+	ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
+	if (ret)
+		return ret;
 
 	list_for_each_entry(clki, head, list) {
 		if (!IS_ERR_OR_NULL(clki->clk)) {
@@ -7435,16 +7428,9 @@ static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
 		}
 	}
 
-	/*
-	 * vendor specific setup_clocks ops may depend on clocks managed by
-	 * this standard driver hence call the vendor specific setup_clocks
-	 * after enabling the clocks managed here.
-	 */
-	if (on) {
-		ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
-		if (ret)
-			return ret;
-	}
+	ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
+	if (ret)
+		return ret;
 
 out:
 	if (ret) {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 3+ messages in thread

* [PATCH 5/8] scsi: ufs: Fix ufshcd_hold() caused scheduling while atomic
       [not found] <1580972212-29881-1-git-send-email-cang@codeaurora.org>
  2020-02-06  6:56 ` [PATCH 2/8] scsi: ufs: set load before setting voltage in regulators Can Guo
  2020-02-06  6:56 ` [PATCH 3/8] scsi: ufs: Remove the check before call setup clock notify vops Can Guo
@ 2020-02-06  6:56 ` Can Guo
  2 siblings, 0 replies; 3+ messages in thread
From: Can Guo @ 2020-02-06  6:56 UTC (permalink / raw)
  To: asutoshd, nguyenb, hongwus, rnayak, linux-scsi, kernel-team,
	saravanak, salyzyn, cang
  Cc: Bart Van Assche, Martin K. Petersen, Venkat Gopalakrishnan,
	James E.J. Bottomley, open list, Avri Altman,
	moderated list:ARM/Mediatek SoC support, Alim Akhtar,
	Matthias Brugger, Tomas Winkler, Stanley Chu,
	moderated list:ARM/Mediatek SoC support, Bean Huo

The async version of ufshcd_hold(async == true), which is only called
in queuecommand path as for now, is expected to work in atomic context,
thus it should not sleep or schedule out. When it runs into the condition
that clocks are ON but link is still in hibern8 state, it should bail out
without flushing the clock ungate work.

Signed-off-by: Can Guo <cang@codeaurora.org>
Reviewed-by: Hongwu Su <hongwus@codeaurora.org>
Reviewed-by: Asutosh Das <asutoshd@codeaurora.org>
Reviewed-by: Bean Huo <beanhuo@micron.com>
Reviewed-by: Stanley Chu <stanley.chu@mediatek.com>

diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index bbc2607..e8f7f9d 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -1518,6 +1518,11 @@ int ufshcd_hold(struct ufs_hba *hba, bool async)
 		 */
 		if (ufshcd_can_hibern8_during_gating(hba) &&
 		    ufshcd_is_link_hibern8(hba)) {
+			if (async) {
+				rc = -EAGAIN;
+				hba->clk_gating.active_reqs--;
+				break;
+			}
 			spin_unlock_irqrestore(hba->host->host_lock, flags);
 			flush_work(&hba->clk_gating.ungate_work);
 			spin_lock_irqsave(hba->host->host_lock, flags);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2020-02-06  6:58 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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     [not found] <1580972212-29881-1-git-send-email-cang@codeaurora.org>
2020-02-06  6:56 ` [PATCH 2/8] scsi: ufs: set load before setting voltage in regulators Can Guo
2020-02-06  6:56 ` [PATCH 3/8] scsi: ufs: Remove the check before call setup clock notify vops Can Guo
2020-02-06  6:56 ` [PATCH 5/8] scsi: ufs: Fix ufshcd_hold() caused scheduling while atomic Can Guo

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