* [PATCH v2 0/4] Mediatek MT8192 scpsys support
@ 2020-10-22 12:47 Weiyi Lu
2020-10-22 12:47 ` [PATCH v2 1/4] dt-bindings: power: Add MT8192 power domains Weiyi Lu
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Weiyi Lu @ 2020-10-22 12:47 UTC (permalink / raw)
To: Enric Balletbo Serra, Matthias Brugger, Nicolas Boichat, Rob Herring
Cc: devicetree, Weiyi Lu, srv_heupstream, linux-kernel,
linux-mediatek, linux-arm-kernel
This series is based on v5.9-rc1, MT8192 clock v4[1] and
soc: mediatek: pm-domains: Add new driver for SCPSYS power domains controller[2]
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=368799
[2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=358429
change since v1:
- add patch of default power off flag
Weiyi Lu (4):
dt-bindings: power: Add MT8192 power domains
soc: mediatek: pm-domains: Add default power off flag
soc: mediatek: pm-domains: Add support for mt8192
arm64: dts: mediatek: Add mt8192 power domains controller
.../power/mediatek,power-controller.yaml | 1 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 201 +++++++++++
drivers/soc/mediatek/mtk-pm-domains.c | 313 +++++++++++++++++-
include/dt-bindings/power/mt8192-power.h | 32 ++
include/linux/soc/mediatek/infracfg.h | 56 ++++
5 files changed, 596 insertions(+), 7 deletions(-)
create mode 100644 include/dt-bindings/power/mt8192-power.h
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/4] dt-bindings: power: Add MT8192 power domains
2020-10-22 12:47 [PATCH v2 0/4] Mediatek MT8192 scpsys support Weiyi Lu
@ 2020-10-22 12:47 ` Weiyi Lu
2020-10-22 12:47 ` [PATCH v2 2/4] soc: mediatek: pm-domains: Add default power off flag Weiyi Lu
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Weiyi Lu @ 2020-10-22 12:47 UTC (permalink / raw)
To: Enric Balletbo Serra, Matthias Brugger, Nicolas Boichat, Rob Herring
Cc: devicetree, Weiyi Lu, srv_heupstream, linux-kernel,
linux-mediatek, linux-arm-kernel
Add power domains dt-bindings for MT8192.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
.../bindings/power/mediatek,power-controller.yaml | 1 +
include/dt-bindings/power/mt8192-power.h | 32 ++++++++++++++++++++++
2 files changed, 33 insertions(+)
create mode 100644 include/dt-bindings/power/mt8192-power.h
diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index 67a15f2..1ebed79 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -25,6 +25,7 @@ properties:
enum:
- mediatek,mt8173-power-controller
- mediatek,mt8183-power-controller
+ - mediatek,mt8192-power-controller
'#power-domain-cells':
const: 1
diff --git a/include/dt-bindings/power/mt8192-power.h b/include/dt-bindings/power/mt8192-power.h
new file mode 100644
index 0000000..4eaa53d
--- /dev/null
+++ b/include/dt-bindings/power/mt8192-power.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8192_POWER_H
+#define _DT_BINDINGS_POWER_MT8192_POWER_H
+
+#define MT8192_POWER_DOMAIN_AUDIO 0
+#define MT8192_POWER_DOMAIN_CONN 1
+#define MT8192_POWER_DOMAIN_MFG0 2
+#define MT8192_POWER_DOMAIN_MFG1 3
+#define MT8192_POWER_DOMAIN_MFG2 4
+#define MT8192_POWER_DOMAIN_MFG3 5
+#define MT8192_POWER_DOMAIN_MFG4 6
+#define MT8192_POWER_DOMAIN_MFG5 7
+#define MT8192_POWER_DOMAIN_MFG6 8
+#define MT8192_POWER_DOMAIN_DISP 9
+#define MT8192_POWER_DOMAIN_IPE 10
+#define MT8192_POWER_DOMAIN_ISP 11
+#define MT8192_POWER_DOMAIN_ISP2 12
+#define MT8192_POWER_DOMAIN_MDP 13
+#define MT8192_POWER_DOMAIN_VENC 14
+#define MT8192_POWER_DOMAIN_VDEC 15
+#define MT8192_POWER_DOMAIN_VDEC2 16
+#define MT8192_POWER_DOMAIN_CAM 17
+#define MT8192_POWER_DOMAIN_CAM_RAWA 18
+#define MT8192_POWER_DOMAIN_CAM_RAWB 19
+#define MT8192_POWER_DOMAIN_CAM_RAWC 20
+
+#endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/4] soc: mediatek: pm-domains: Add default power off flag
2020-10-22 12:47 [PATCH v2 0/4] Mediatek MT8192 scpsys support Weiyi Lu
2020-10-22 12:47 ` [PATCH v2 1/4] dt-bindings: power: Add MT8192 power domains Weiyi Lu
@ 2020-10-22 12:47 ` Weiyi Lu
2020-10-27 10:25 ` Matthias Brugger
2020-10-22 12:47 ` [PATCH v2 3/4] soc: mediatek: pm-domains: Add support for mt8192 Weiyi Lu
2020-10-22 12:47 ` [PATCH v2 4/4] arm64: dts: mediatek: Add mt8192 power domains controller Weiyi Lu
3 siblings, 1 reply; 6+ messages in thread
From: Weiyi Lu @ 2020-10-22 12:47 UTC (permalink / raw)
To: Enric Balletbo Serra, Matthias Brugger, Nicolas Boichat, Rob Herring
Cc: devicetree, Weiyi Lu, srv_heupstream, linux-kernel,
linux-mediatek, linux-arm-kernel
For some power domain, like conn on MT8192, it should be default OFF.
Because the power on/off control relies the function of connectivity chip
and its firmware. And if project choose other chip vendor solution,
those necessary connectivity functions will not provided.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-pm-domains.c | 23 +++++++++++++++++------
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index b7ccf94..50a7ae1 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -24,6 +24,7 @@
#define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
#define MTK_SCPD_FWAIT_SRAM BIT(1)
#define MTK_SCPD_SRAM_ISO BIT(2)
+#define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3)
#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
#define SPM_VDE_PWR_CON 0x0210
@@ -506,17 +507,26 @@ static int scpsys_add_one_domain(struct scpsys *scpsys, struct device_node *node
* software. The unused domains will be switched off during
* late_init time.
*/
- ret = scpsys_power_on(&pd->genpd);
- if (ret < 0) {
- dev_err_probe(scpsys->dev, ret, "failed to power on domain %pOFN\n", node);
- goto err_unprepare_clocks;
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF)) {
+ if (scpsys_domain_is_on(pd))
+ dev_warn(scpsys->dev,
+ "A default off power domain %pOFN has been ON\n", node);
+ } else {
+ ret = scpsys_power_on(&pd->genpd);
+ if (ret < 0) {
+ dev_err_probe(scpsys->dev, ret, "failed to power on domain %pOFN\n", node);
+ goto err_unprepare_clocks;
+ }
}
pd->genpd.name = node->name;
pd->genpd.power_off = scpsys_power_off;
pd->genpd.power_on = scpsys_power_on;
- pm_genpd_init(&pd->genpd, NULL, false);
+ if (MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF))
+ pm_genpd_init(&pd->genpd, NULL, true);
+ else
+ pm_genpd_init(&pd->genpd, NULL, false);
scpsys->domains[id] = &pd->genpd;
return 0;
@@ -603,7 +613,8 @@ static void scpsys_remove_one_domain(struct scpsys_domain *pd)
"failed to remove domain '%s' : %d - state may be inconsistent\n",
pd->genpd.name, ret);
- scpsys_power_off(&pd->genpd);
+ if (!MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF))
+ scpsys_power_off(&pd->genpd);
clk_bulk_unprepare(pd->num_clks, pd->clks);
clk_bulk_put(pd->num_clks, pd->clks);
--
1.8.1.1.dirty
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http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/4] soc: mediatek: pm-domains: Add support for mt8192
2020-10-22 12:47 [PATCH v2 0/4] Mediatek MT8192 scpsys support Weiyi Lu
2020-10-22 12:47 ` [PATCH v2 1/4] dt-bindings: power: Add MT8192 power domains Weiyi Lu
2020-10-22 12:47 ` [PATCH v2 2/4] soc: mediatek: pm-domains: Add default power off flag Weiyi Lu
@ 2020-10-22 12:47 ` Weiyi Lu
2020-10-22 12:47 ` [PATCH v2 4/4] arm64: dts: mediatek: Add mt8192 power domains controller Weiyi Lu
3 siblings, 0 replies; 6+ messages in thread
From: Weiyi Lu @ 2020-10-22 12:47 UTC (permalink / raw)
To: Enric Balletbo Serra, Matthias Brugger, Nicolas Boichat, Rob Herring
Cc: devicetree, Weiyi Lu, srv_heupstream, linux-kernel,
linux-mediatek, linux-arm-kernel
Add the needed board data to support mt8192 SoC.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-pm-domains.c | 290 +++++++++++++++++++++++++++++++++-
include/linux/soc/mediatek/infracfg.h | 56 +++++++
2 files changed, 345 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 50a7ae1..a3c2f7e 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -17,6 +17,7 @@
#include <dt-bindings/power/mt8173-power.h>
#include <dt-bindings/power/mt8183-power.h>
+#include <dt-bindings/power/mt8192-power.h>
#define MTK_POLL_DELAY_US 10
#define MTK_POLL_TIMEOUT USEC_PER_SEC
@@ -61,7 +62,7 @@
#define PWR_STATUS_AUDIO BIT(24)
#define PWR_STATUS_USB BIT(25)
-#define SPM_MAX_BUS_PROT_DATA 3
+#define SPM_MAX_BUS_PROT_DATA 5
#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \
.bus_prot_mask = (_mask), \
@@ -922,6 +923,282 @@ static void scpsys_domain_cleanup(struct scpsys *scpsys)
},
};
+/*
+ * MT8192 power domain support
+ */
+
+static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
+ [MT8192_POWER_DOMAIN_AUDIO] = {
+ .sta_mask = BIT(21),
+ .ctl_offs = 0x0354,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO,
+ MT8192_TOP_AXI_PROT_EN_2_SET,
+ MT8192_TOP_AXI_PROT_EN_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_2_STA1),
+ },
+ },
+ [MT8192_POWER_DOMAIN_CONN] = {
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = 0x0304,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN,
+ MT8192_TOP_AXI_PROT_EN_SET,
+ MT8192_TOP_AXI_PROT_EN_CLR,
+ MT8192_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND,
+ MT8192_TOP_AXI_PROT_EN_SET,
+ MT8192_TOP_AXI_PROT_EN_CLR,
+ MT8192_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN,
+ MT8192_TOP_AXI_PROT_EN_1_SET,
+ MT8192_TOP_AXI_PROT_EN_1_CLR,
+ MT8192_TOP_AXI_PROT_EN_1_STA1),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8192_POWER_DOMAIN_MFG0] = {
+ .sta_mask = BIT(2),
+ .ctl_offs = 0x0308,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8192_POWER_DOMAIN_MFG1] = {
+ .sta_mask = BIT(3),
+ .ctl_offs = 0x030c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1,
+ MT8192_TOP_AXI_PROT_EN_1_SET,
+ MT8192_TOP_AXI_PROT_EN_1_CLR,
+ MT8192_TOP_AXI_PROT_EN_1_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1,
+ MT8192_TOP_AXI_PROT_EN_2_SET,
+ MT8192_TOP_AXI_PROT_EN_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_2_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1,
+ MT8192_TOP_AXI_PROT_EN_SET,
+ MT8192_TOP_AXI_PROT_EN_CLR,
+ MT8192_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND,
+ MT8192_TOP_AXI_PROT_EN_2_SET,
+ MT8192_TOP_AXI_PROT_EN_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_2_STA1),
+ },
+ },
+ [MT8192_POWER_DOMAIN_MFG2] = {
+ .sta_mask = BIT(4),
+ .ctl_offs = 0x0310,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8192_POWER_DOMAIN_MFG3] = {
+ .sta_mask = BIT(5),
+ .ctl_offs = 0x0314,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8192_POWER_DOMAIN_MFG4] = {
+ .sta_mask = BIT(6),
+ .ctl_offs = 0x0318,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8192_POWER_DOMAIN_MFG5] = {
+ .sta_mask = BIT(7),
+ .ctl_offs = 0x031c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8192_POWER_DOMAIN_MFG6] = {
+ .sta_mask = BIT(8),
+ .ctl_offs = 0x0320,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8192_POWER_DOMAIN_DISP] = {
+ .sta_mask = BIT(20),
+ .ctl_offs = 0x0350,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_infracfg = {
+ BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_DISP,
+ MT8192_TOP_AXI_PROT_EN_SET,
+ MT8192_TOP_AXI_PROT_EN_CLR,
+ MT8192_TOP_AXI_PROT_EN_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ },
+ },
+ [MT8192_POWER_DOMAIN_IPE] = {
+ .sta_mask = BIT(14),
+ .ctl_offs = 0x0338,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ },
+ },
+ [MT8192_POWER_DOMAIN_ISP] = {
+ .sta_mask = BIT(12),
+ .ctl_offs = 0x0330,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ },
+ },
+ [MT8192_POWER_DOMAIN_ISP2] = {
+ .sta_mask = BIT(13),
+ .ctl_offs = 0x0334,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ },
+ },
+ [MT8192_POWER_DOMAIN_MDP] = {
+ .sta_mask = BIT(19),
+ .ctl_offs = 0x034c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
+ },
+ },
+ [MT8192_POWER_DOMAIN_VENC] = {
+ .sta_mask = BIT(17),
+ .ctl_offs = 0x0344,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ },
+ },
+ [MT8192_POWER_DOMAIN_VDEC] = {
+ .sta_mask = BIT(15),
+ .ctl_offs = 0x033c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ },
+ },
+ [MT8192_POWER_DOMAIN_VDEC2] = {
+ .sta_mask = BIT(16),
+ .ctl_offs = 0x0340,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8192_POWER_DOMAIN_CAM] = {
+ .sta_mask = BIT(23),
+ .ctl_offs = 0x035c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_CAM,
+ MT8192_TOP_AXI_PROT_EN_2_SET,
+ MT8192_TOP_AXI_PROT_EN_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_2_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CAM,
+ MT8192_TOP_AXI_PROT_EN_1_SET,
+ MT8192_TOP_AXI_PROT_EN_1_CLR,
+ MT8192_TOP_AXI_PROT_EN_1_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND,
+ MT8192_TOP_AXI_PROT_EN_MM_SET,
+ MT8192_TOP_AXI_PROT_EN_MM_CLR,
+ MT8192_TOP_AXI_PROT_EN_MM_STA1),
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM,
+ MT8192_TOP_AXI_PROT_EN_VDNR_SET,
+ MT8192_TOP_AXI_PROT_EN_VDNR_CLR,
+ MT8192_TOP_AXI_PROT_EN_VDNR_STA1),
+ },
+ },
+ [MT8192_POWER_DOMAIN_CAM_RAWA] = {
+ .sta_mask = BIT(24),
+ .ctl_offs = 0x0360,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8192_POWER_DOMAIN_CAM_RAWB] = {
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x0364,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8192_POWER_DOMAIN_CAM_RAWC] = {
+ .sta_mask = BIT(26),
+ .ctl_offs = 0x0368,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+};
+
static const struct scpsys_soc_data mt8173_scpsys_data = {
.domains = scpsys_domain_data_mt8173,
.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8173),
@@ -936,6 +1213,13 @@ static void scpsys_domain_cleanup(struct scpsys *scpsys)
.pwr_sta2nd_offs = 0x0184
};
+static const struct scpsys_soc_data mt8192_scpsys_data = {
+ .domains = scpsys_domain_data_mt8192,
+ .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8192),
+ .pwr_sta_offs = 0x016c,
+ .pwr_sta2nd_offs = 0x0170,
+};
+
static const struct of_device_id scpsys_of_match[] = {
{
.compatible = "mediatek,mt8173-power-controller",
@@ -945,6 +1229,10 @@ static void scpsys_domain_cleanup(struct scpsys *scpsys)
.compatible = "mediatek,mt8183-power-controller",
.data = &mt8183_scpsys_data,
},
+ {
+ .compatible = "mediatek,mt8192-power-controller",
+ .data = &mt8192_scpsys_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
index 826ed51..122db6b 100644
--- a/include/linux/soc/mediatek/infracfg.h
+++ b/include/linux/soc/mediatek/infracfg.h
@@ -2,6 +2,62 @@
#ifndef __SOC_MEDIATEK_INFRACFG_H
#define __SOC_MEDIATEK_INFRACFG_H
+#define MT8192_TOP_AXI_PROT_EN_STA1 0x228
+#define MT8192_TOP_AXI_PROT_EN_1_STA1 0x258
+#define MT8192_TOP_AXI_PROT_EN_SET 0x2a0
+#define MT8192_TOP_AXI_PROT_EN_CLR 0x2a4
+#define MT8192_TOP_AXI_PROT_EN_1_SET 0x2a8
+#define MT8192_TOP_AXI_PROT_EN_1_CLR 0x2ac
+#define MT8192_TOP_AXI_PROT_EN_MM_SET 0x2d4
+#define MT8192_TOP_AXI_PROT_EN_MM_CLR 0x2d8
+#define MT8192_TOP_AXI_PROT_EN_MM_STA1 0x2ec
+#define MT8192_TOP_AXI_PROT_EN_2_SET 0x714
+#define MT8192_TOP_AXI_PROT_EN_2_CLR 0x718
+#define MT8192_TOP_AXI_PROT_EN_2_STA1 0x724
+#define MT8192_TOP_AXI_PROT_EN_VDNR_SET 0xb84
+#define MT8192_TOP_AXI_PROT_EN_VDNR_CLR 0xb88
+#define MT8192_TOP_AXI_PROT_EN_VDNR_STA1 0xb90
+#define MT8192_TOP_AXI_PROT_EN_MM_2_SET 0xdcc
+#define MT8192_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0
+#define MT8192_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8
+
+#define MT8192_TOP_AXI_PROT_EN_DISP (BIT(6) | BIT(23))
+#define MT8192_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(18))
+#define MT8192_TOP_AXI_PROT_EN_CONN_2ND BIT(14)
+#define MT8192_TOP_AXI_PROT_EN_MFG1 GENMASK(22, 21)
+#define MT8192_TOP_AXI_PROT_EN_1_CONN BIT(10)
+#define MT8192_TOP_AXI_PROT_EN_1_MFG1 BIT(21)
+#define MT8192_TOP_AXI_PROT_EN_1_CAM BIT(22)
+#define MT8192_TOP_AXI_PROT_EN_2_CAM BIT(0)
+#define MT8192_TOP_AXI_PROT_EN_2_ADSP BIT(3)
+#define MT8192_TOP_AXI_PROT_EN_2_AUDIO BIT(4)
+#define MT8192_TOP_AXI_PROT_EN_2_MFG1 GENMASK(6, 5)
+#define MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND BIT(7)
+#define MT8192_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2))
+#define MT8192_TOP_AXI_PROT_EN_MM_DISP (BIT(0) | BIT(2) | \
+ BIT(10) | BIT(12) | \
+ BIT(14) | BIT(16) | \
+ BIT(24) | BIT(26))
+#define MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND (BIT(1) | BIT(3))
+#define MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND (BIT(1) | BIT(3) | \
+ BIT(15) | BIT(17) | \
+ BIT(25) | BIT(27))
+#define MT8192_TOP_AXI_PROT_EN_MM_ISP2 BIT(14)
+#define MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND BIT(15)
+#define MT8192_TOP_AXI_PROT_EN_MM_IPE BIT(16)
+#define MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND BIT(17)
+#define MT8192_TOP_AXI_PROT_EN_MM_VDEC BIT(24)
+#define MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND BIT(25)
+#define MT8192_TOP_AXI_PROT_EN_MM_VENC BIT(26)
+#define MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(27)
+#define MT8192_TOP_AXI_PROT_EN_MM_2_ISP BIT(8)
+#define MT8192_TOP_AXI_PROT_EN_MM_2_DISP (BIT(8) | BIT(12))
+#define MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND BIT(9)
+#define MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND (BIT(9) | BIT(13))
+#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP BIT(12)
+#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13)
+#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21)
+
#define MT8183_TOP_AXI_PROT_EN_STA1 0x228
#define MT8183_TOP_AXI_PROT_EN_STA1_1 0x258
#define MT8183_TOP_AXI_PROT_EN_SET 0x2a0
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 4/4] arm64: dts: mediatek: Add mt8192 power domains controller
2020-10-22 12:47 [PATCH v2 0/4] Mediatek MT8192 scpsys support Weiyi Lu
` (2 preceding siblings ...)
2020-10-22 12:47 ` [PATCH v2 3/4] soc: mediatek: pm-domains: Add support for mt8192 Weiyi Lu
@ 2020-10-22 12:47 ` Weiyi Lu
3 siblings, 0 replies; 6+ messages in thread
From: Weiyi Lu @ 2020-10-22 12:47 UTC (permalink / raw)
To: Enric Balletbo Serra, Matthias Brugger, Nicolas Boichat, Rob Herring
Cc: devicetree, Weiyi Lu, srv_heupstream, linux-kernel,
linux-mediatek, linux-arm-kernel
Add power domains controller node for SoC mt8192
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 201 +++++++++++++++++++++++++++++++
1 file changed, 201 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index b3fab4f..9274291 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
+#include <dt-bindings/power/mt8192-power.h>
/ {
compatible = "mediatek,mt8192";
@@ -257,6 +258,206 @@
#interrupt-cells = <2>;
};
+ scpsys: syscon@10006000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+ #power-domain-cells = <1>;
+
+ /* System Power Manager */
+ spm: power-controller {
+ compatible = "mediatek,mt8192-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domain of the SoC */
+ audio@MT8192_POWER_DOMAIN_AUDIO {
+ reg = <MT8192_POWER_DOMAIN_AUDIO>;
+ clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+ <&infracfg CLK_INFRA_AUDIO_26M_B>,
+ <&infracfg CLK_INFRA_AUDIO>;
+ clock-names = "audio", "audio1", "audio2";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ conn@MT8192_POWER_DOMAIN_CONN {
+ reg = <MT8192_POWER_DOMAIN_CONN>;
+ clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
+ clock-names = "conn";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ mfg@MT8192_POWER_DOMAIN_MFG0 {
+ reg = <MT8192_POWER_DOMAIN_MFG0>;
+ clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
+ clock-names = "mfg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ mfg1@MT8192_POWER_DOMAIN_MFG1 {
+ reg = <MT8192_POWER_DOMAIN_MFG1>;
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ mfg2@MT8192_POWER_DOMAIN_MFG2 {
+ reg = <MT8192_POWER_DOMAIN_MFG2>;
+ #power-domain-cells = <0>;
+ };
+
+ mfg3@MT8192_POWER_DOMAIN_MFG3 {
+ reg = <MT8192_POWER_DOMAIN_MFG3>;
+ #power-domain-cells = <0>;
+ };
+
+ mfg4@MT8192_POWER_DOMAIN_MFG4 {
+ reg = <MT8192_POWER_DOMAIN_MFG4>;
+ #power-domain-cells = <0>;
+ };
+
+ mfg5@MT8192_POWER_DOMAIN_MFG5 {
+ reg = <MT8192_POWER_DOMAIN_MFG5>;
+ #power-domain-cells = <0>;
+ };
+
+ mfg6@MT8192_POWER_DOMAIN_MFG6 {
+ reg = <MT8192_POWER_DOMAIN_MFG6>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ disp@MT8192_POWER_DOMAIN_DISP {
+ reg = <MT8192_POWER_DOMAIN_DISP>;
+ clocks = <&topckgen CLK_TOP_DISP_SEL>,
+ <&mmsys CLK_MM_SMI_INFRA>,
+ <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_GALS>,
+ <&mmsys CLK_MM_SMI_IOMMU>;
+ clock-names = "disp", "disp-0", "disp-1", "disp-2",
+ "disp-3";
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ ipe@MT8192_POWER_DOMAIN_IPE {
+ reg = <MT8192_POWER_DOMAIN_IPE>;
+ clocks = <&topckgen CLK_TOP_IPE_SEL>,
+ <&ipesys CLK_IPE_LARB19>,
+ <&ipesys CLK_IPE_LARB20>,
+ <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_GALS>;
+ clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
+ "ipe-3";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ isp@MT8192_POWER_DOMAIN_ISP {
+ reg = <MT8192_POWER_DOMAIN_ISP>;
+ clocks = <&topckgen CLK_TOP_IMG1_SEL>,
+ <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_GALS>;
+ clock-names = "isp", "isp-0", "isp-1";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ isp2@MT8192_POWER_DOMAIN_ISP2 {
+ reg = <MT8192_POWER_DOMAIN_ISP2>;
+ clocks = <&topckgen CLK_TOP_IMG2_SEL>,
+ <&imgsys2 CLK_IMG2_LARB11>,
+ <&imgsys2 CLK_IMG2_GALS>;
+ clock-names = "isp2", "isp2-0", "isp2-1";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ mdp@MT8192_POWER_DOMAIN_MDP {
+ reg = <MT8192_POWER_DOMAIN_MDP>;
+ clocks = <&topckgen CLK_TOP_MDP_SEL>,
+ <&mdpsys CLK_MDP_SMI0>;
+ clock-names = "mdp", "mdp-0";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ venc@MT8192_POWER_DOMAIN_VENC {
+ reg = <MT8192_POWER_DOMAIN_VENC>;
+ clocks = <&topckgen CLK_TOP_VENC_SEL>,
+ <&vencsys CLK_VENC_SET1_VENC>;
+ clock-names = "venc", "venc-0";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
+
+ vdec@MT8192_POWER_DOMAIN_VDEC {
+ reg = <MT8192_POWER_DOMAIN_VDEC>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ vdec2@MT8192_POWER_DOMAIN_VDEC2 {
+ reg = <MT8192_POWER_DOMAIN_VDEC2>;
+ clocks = <&vdecsys CLK_VDEC_VDEC>,
+ <&vdecsys CLK_VDEC_LAT>,
+ <&vdecsys CLK_VDEC_LARB1>;
+ clock-names = "vdec2-0", "vdec2-1",
+ "vdec2-2";
+ #power-domain-cells = <0>;
+ };
+ };
+
+ cam@MT8192_POWER_DOMAIN_CAM {
+ reg = <MT8192_POWER_DOMAIN_CAM>;
+ clocks = <&topckgen CLK_TOP_CAM_SEL>,
+ <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_LARB14>,
+ <&camsys CLK_CAM_CCU_GALS>,
+ <&camsys CLK_CAM_CAM2MM_GALS>;
+ clock-names = "cam", "cam-0", "cam-1", "cam-2",
+ "cam-3";
+ mediatek,infracfg = <&infracfg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ cam_rawa@MT8192_POWER_DOMAIN_CAM_RAWA {
+ reg = <MT8192_POWER_DOMAIN_CAM_RAWA>;
+ clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+ clock-names = "cam_rawa-0";
+ #power-domain-cells = <0>;
+ };
+
+ cam_rawb@MT8192_POWER_DOMAIN_CAM_RAWB {
+ reg = <MT8192_POWER_DOMAIN_CAM_RAWB>;
+ clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+ clock-names = "cam_rawb-0";
+ #power-domain-cells = <0>;
+ };
+
+ cam_rawc@MT8192_POWER_DOMAIN_CAM_RAWC {
+ reg = <MT8192_POWER_DOMAIN_CAM_RAWC>;
+ clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>;
+ clock-names = "cam_rawc-0";
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8192-wdt";
reg = <0 0x10007000 0 0x100>;
--
1.8.1.1.dirty
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 2/4] soc: mediatek: pm-domains: Add default power off flag
2020-10-22 12:47 ` [PATCH v2 2/4] soc: mediatek: pm-domains: Add default power off flag Weiyi Lu
@ 2020-10-27 10:25 ` Matthias Brugger
0 siblings, 0 replies; 6+ messages in thread
From: Matthias Brugger @ 2020-10-27 10:25 UTC (permalink / raw)
To: Weiyi Lu, Enric Balletbo Serra, Nicolas Boichat, Rob Herring
Cc: devicetree, srv_heupstream, linux-mediatek, linux-kernel,
linux-arm-kernel
On 22/10/2020 14:47, Weiyi Lu wrote:
> For some power domain, like conn on MT8192, it should be default OFF.
> Because the power on/off control relies the function of connectivity chip
> and its firmware. And if project choose other chip vendor solution,
> those necessary connectivity functions will not provided.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-pm-domains.c | 23 +++++++++++++++++------
> 1 file changed, 17 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
> index b7ccf94..50a7ae1 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.c
> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> @@ -24,6 +24,7 @@
> #define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
> #define MTK_SCPD_FWAIT_SRAM BIT(1)
> #define MTK_SCPD_SRAM_ISO BIT(2)
> +#define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3)
> #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
>
> #define SPM_VDE_PWR_CON 0x0210
> @@ -506,17 +507,26 @@ static int scpsys_add_one_domain(struct scpsys *scpsys, struct device_node *node
> * software. The unused domains will be switched off during
> * late_init time.
> */
> - ret = scpsys_power_on(&pd->genpd);
> - if (ret < 0) {
> - dev_err_probe(scpsys->dev, ret, "failed to power on domain %pOFN\n", node);
> - goto err_unprepare_clocks;
> + if (MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF)) {
> + if (scpsys_domain_is_on(pd))
> + dev_warn(scpsys->dev,
> + "A default off power domain %pOFN has been ON\n", node);
> + } else {
> + ret = scpsys_power_on(&pd->genpd);
> + if (ret < 0) {
> + dev_err_probe(scpsys->dev, ret, "failed to power on domain %pOFN\n", node);
> + goto err_unprepare_clocks;
> + }
> }
>
> pd->genpd.name = node->name;
> pd->genpd.power_off = scpsys_power_off;
> pd->genpd.power_on = scpsys_power_on;
>
> - pm_genpd_init(&pd->genpd, NULL, false);
> + if (MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF))
> + pm_genpd_init(&pd->genpd, NULL, true);
> + else
> + pm_genpd_init(&pd->genpd, NULL, false);
>
> scpsys->domains[id] = &pd->genpd;
> return 0;
> @@ -603,7 +613,8 @@ static void scpsys_remove_one_domain(struct scpsys_domain *pd)
> "failed to remove domain '%s' : %d - state may be inconsistent\n",
> pd->genpd.name, ret);
>
> - scpsys_power_off(&pd->genpd);
> + if (!MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF))
> + scpsys_power_off(&pd->genpd);
Is that really needed? Turning the domain off when it's already off shouldn't hurt.
Regards,
Matthias
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-10-27 10:26 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-22 12:47 [PATCH v2 0/4] Mediatek MT8192 scpsys support Weiyi Lu
2020-10-22 12:47 ` [PATCH v2 1/4] dt-bindings: power: Add MT8192 power domains Weiyi Lu
2020-10-22 12:47 ` [PATCH v2 2/4] soc: mediatek: pm-domains: Add default power off flag Weiyi Lu
2020-10-27 10:25 ` Matthias Brugger
2020-10-22 12:47 ` [PATCH v2 3/4] soc: mediatek: pm-domains: Add support for mt8192 Weiyi Lu
2020-10-22 12:47 ` [PATCH v2 4/4] arm64: dts: mediatek: Add mt8192 power domains controller Weiyi Lu
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