* [PATCH v2 1/4] arm: mm: use strict p[gum]d types
2020-10-23 9:14 [PATCH v2 0/4] arm: support get_user_pages_fast Miles Chen
@ 2020-10-23 9:14 ` Miles Chen
2020-10-23 9:14 ` [PATCH v2 2/4] arm: mm: reordering memory type table Miles Chen
` (2 subsequent siblings)
3 siblings, 0 replies; 13+ messages in thread
From: Miles Chen @ 2020-10-23 9:14 UTC (permalink / raw)
To: Catalin Marinas, Russell King, Minchan Kim
Cc: wsd_upstream, linux-kernel, Miles Chen, linux-mediatek,
Suren Baghdasaryan, linux-arm-kernel
When use mm/gup.c, it is necessary to use strict p*d types.
Otherwise, we will get build breaks such as:
mm/gup.c:2589:9: error: incompatible pointer types passing 'pmdval_t **'
(aka 'unsigned int **') to parameter of type 'pgd_t *'
(aka 'pmdval_t (*)[2]') [-Werror,-Wincompatible-pointer-types]
mm/gup.c:2616:9: error: array initializer must be an initializer list
Fix some types errors in fixmap.h after using strict types.
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Minchan Kim <minchan@kernel.org>
Cc: Suren Baghdasaryan <surenb@google.com>
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
---
arch/arm/include/asm/fixmap.h | 6 ++---
arch/arm/include/asm/pgtable-2level-types.h | 26 ---------------------
arch/arm/include/asm/pgtable-2level.h | 1 +
3 files changed, 4 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/fixmap.h b/arch/arm/include/asm/fixmap.h
index fc56fc3e1931..3ea12b2da708 100644
--- a/arch/arm/include/asm/fixmap.h
+++ b/arch/arm/include/asm/fixmap.h
@@ -42,11 +42,11 @@ static const enum fixed_addresses __end_of_fixed_addresses =
#define FIXMAP_PAGE_COMMON (L_PTE_YOUNG | L_PTE_PRESENT | L_PTE_XN | L_PTE_DIRTY)
-#define FIXMAP_PAGE_NORMAL (pgprot_kernel | L_PTE_XN)
-#define FIXMAP_PAGE_RO (FIXMAP_PAGE_NORMAL | L_PTE_RDONLY)
+#define FIXMAP_PAGE_NORMAL __pgprot(pgprot_val(pgprot_kernel) | L_PTE_XN)
+#define FIXMAP_PAGE_RO __pgprot(pgprot_val(FIXMAP_PAGE_NORMAL) | L_PTE_RDONLY)
/* Used by set_fixmap_(io|nocache), both meant for mapping a device */
-#define FIXMAP_PAGE_IO (FIXMAP_PAGE_COMMON | L_PTE_MT_DEV_SHARED | L_PTE_SHARED)
+#define FIXMAP_PAGE_IO __pgprot(FIXMAP_PAGE_COMMON | L_PTE_MT_DEV_SHARED | L_PTE_SHARED)
#define FIXMAP_PAGE_NOCACHE FIXMAP_PAGE_IO
#define __early_set_fixmap __set_fixmap
diff --git a/arch/arm/include/asm/pgtable-2level-types.h b/arch/arm/include/asm/pgtable-2level-types.h
index 650e793f4142..64fd5b8d9dc2 100644
--- a/arch/arm/include/asm/pgtable-2level-types.h
+++ b/arch/arm/include/asm/pgtable-2level-types.h
@@ -12,12 +12,6 @@
typedef u32 pteval_t;
typedef u32 pmdval_t;
-#undef STRICT_MM_TYPECHECKS
-
-#ifdef STRICT_MM_TYPECHECKS
-/*
- * These are used to make use of C type-checking..
- */
typedef struct { pteval_t pte; } pte_t;
typedef struct { pmdval_t pmd; } pmd_t;
typedef struct { pmdval_t pgd[2]; } pgd_t;
@@ -32,24 +26,4 @@ typedef struct { pteval_t pgprot; } pgprot_t;
#define __pmd(x) ((pmd_t) { (x) } )
#define __pgprot(x) ((pgprot_t) { (x) } )
-#else
-/*
- * .. while these make it easier on the compiler
- */
-typedef pteval_t pte_t;
-typedef pmdval_t pmd_t;
-typedef pmdval_t pgd_t[2];
-typedef pteval_t pgprot_t;
-
-#define pte_val(x) (x)
-#define pmd_val(x) (x)
-#define pgd_val(x) ((x)[0])
-#define pgprot_val(x) (x)
-
-#define __pte(x) (x)
-#define __pmd(x) (x)
-#define __pgprot(x) (x)
-
-#endif /* STRICT_MM_TYPECHECKS */
-
#endif /* _ASM_PGTABLE_2LEVEL_TYPES_H */
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index 3502c2f746ca..27a8635abea0 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -180,6 +180,7 @@
#define pud_none(pud) (0)
#define pud_bad(pud) (0)
#define pud_present(pud) (1)
+#define pud_page(pud) pmd_page(__pmd(pud_val(pud)))
#define pud_clear(pudp) do { } while (0)
#define set_pud(pud,pudp) do { } while (0)
--
2.18.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v2 2/4] arm: mm: reordering memory type table
2020-10-23 9:14 [PATCH v2 0/4] arm: support get_user_pages_fast Miles Chen
2020-10-23 9:14 ` [PATCH v2 1/4] arm: mm: use strict p[gum]d types Miles Chen
@ 2020-10-23 9:14 ` Miles Chen
2020-10-23 10:16 ` Russell King - ARM Linux admin
2020-10-23 9:14 ` [PATCH v2 3/4] arm: mm: introduce L_PTE_SPECIAL Miles Chen
2020-10-23 9:14 ` [PATCH v2 4/4] arm: replace vector mem type with read-only type Miles Chen
3 siblings, 1 reply; 13+ messages in thread
From: Miles Chen @ 2020-10-23 9:14 UTC (permalink / raw)
To: Catalin Marinas, Russell King, Minchan Kim
Cc: Steve Capper, wsd_upstream, Will Deacon, linux-kernel,
Miles Chen, Simon Horman, linux-mediatek, Suren Baghdasaryan,
linux-arm-kernel
From: Minchan Kim <minchan@kernel.org>
To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that.
It seems we don't need 4 bits for the memory type with ARMv6+.
If it's true, let's reorder bits to make bit 5 free.
We will use the bit for L_PTE_SPECIAL in next patch.
A note from Catalin in [1]:
"
> Anyway, on ARMv7 or ARMv6+LPAE, the non-shared device gets mapped to
> shared device in hardware. Looking through the arm32 code, it seems that
> MT_DEVICE_NONSHARED is used by arch/arm/mach-shmobile/setup-r8a7779.c
> and IIUC that's a v7 platform (R-Car H1, Cortex-A9). I think the above
> should be defined to L_PTE_MT_DEV_SHARED, unless I miss any place where
> DEV_NONSHARED is relevant on ARMv6 (adding Simon to confirm on shmbile).
"
[1] https://lore.kernel.org/patchwork/patch/986574/
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Steve Capper <steve.capper@linaro.org>
Cc: Simon Horman <horms@verge.net.au>
Cc: Minchan Kim <minchan@kernel.org>
Cc: Suren Baghdasaryan <surenb@google.com>
Signed-off-by: Minchan Kim <minchan@kernel.org>
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
---
arch/arm/include/asm/pgtable-2level.h | 21 +++++++++++++++++----
arch/arm/mm/proc-macros.S | 4 ++--
2 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index 27a8635abea0..cdcd55cca37d 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -161,14 +161,27 @@
#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */
#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */
#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */
+#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
+#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x05) << 2) /* 0101 */
#define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */
#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */
-#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
-#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
+#if defined(CONFIG_CPU_V7) || defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
+/*
+ * On ARMv7 or ARMv7+LPAE, the non-shared and shared device types get
+ * mapped to the same TEX remapping index. On classic ARMv7, the
+ * shareability is controlled by the PRRR[17:16] field, indexed by
+ * L_PTE_SHARED. On ARMv7+LPAE the device mapping is always shareable.
+ */
+#define L_PTE_MT_DEV_NONSHARED L_PTE_MT_DEV_SHARED
+#define L_PTE_MT_DEV_WC L_PTE_MT_BUFFERABLE
+#define L_PTE_MT_DEV_CACHED L_PTE_MT_WRITEBACK
+#define L_PTE_MT_MASK (_AT(pteval_t, 0x07) << 2)
+#else
#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */
#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */
-#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x0f) << 2) /* 1111 */
-#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
+#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
+#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
+#endif
#ifndef __ASSEMBLY__
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index e2c743aa2eb2..dde1d6374250 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -137,7 +137,7 @@
.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
.long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
- .long 0x00 @ unused
+ .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS
.long 0x00 @ L_PTE_MT_MINICACHE (not present)
.long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
.long 0x00 @ unused
@@ -147,7 +147,7 @@
.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
.long 0x00 @ unused
.long 0x00 @ unused
- .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS
+ .long 0x00 @ unused
.endm
.macro armv6_set_pte_ext pfx
--
2.18.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/4] arm: mm: reordering memory type table
2020-10-23 9:14 ` [PATCH v2 2/4] arm: mm: reordering memory type table Miles Chen
@ 2020-10-23 10:16 ` Russell King - ARM Linux admin
2020-10-27 8:03 ` Miles Chen
0 siblings, 1 reply; 13+ messages in thread
From: Russell King - ARM Linux admin @ 2020-10-23 10:16 UTC (permalink / raw)
To: Miles Chen
Cc: Steve Capper, wsd_upstream, Catalin Marinas, Will Deacon,
linux-kernel, Minchan Kim, Simon Horman, linux-mediatek,
Suren Baghdasaryan, linux-arm-kernel
On Fri, Oct 23, 2020 at 05:14:35PM +0800, Miles Chen wrote:
> From: Minchan Kim <minchan@kernel.org>
>
> To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that.
> It seems we don't need 4 bits for the memory type with ARMv6+.
> If it's true, let's reorder bits to make bit 5 free.
>
> We will use the bit for L_PTE_SPECIAL in next patch.
>
> A note from Catalin in [1]:
> "
> > Anyway, on ARMv7 or ARMv6+LPAE, the non-shared device gets mapped to
> > shared device in hardware. Looking through the arm32 code, it seems that
> > MT_DEVICE_NONSHARED is used by arch/arm/mach-shmobile/setup-r8a7779.c
> > and IIUC that's a v7 platform (R-Car H1, Cortex-A9). I think the above
> > should be defined to L_PTE_MT_DEV_SHARED, unless I miss any place where
> > DEV_NONSHARED is relevant on ARMv6 (adding Simon to confirm on shmbile).
> "
>
> [1] https://lore.kernel.org/patchwork/patch/986574/
>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Steve Capper <steve.capper@linaro.org>
> Cc: Simon Horman <horms@verge.net.au>
> Cc: Minchan Kim <minchan@kernel.org>
> Cc: Suren Baghdasaryan <surenb@google.com>
> Signed-off-by: Minchan Kim <minchan@kernel.org>
> Signed-off-by: Miles Chen <miles.chen@mediatek.com>
> ---
> arch/arm/include/asm/pgtable-2level.h | 21 +++++++++++++++++----
> arch/arm/mm/proc-macros.S | 4 ++--
> 2 files changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
> index 27a8635abea0..cdcd55cca37d 100644
> --- a/arch/arm/include/asm/pgtable-2level.h
> +++ b/arch/arm/include/asm/pgtable-2level.h
> @@ -161,14 +161,27 @@
> #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */
> #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */
> #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */
> +#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
> +#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x05) << 2) /* 0101 */
> #define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */
> #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */
> -#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
> -#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
Sorry, no, this isn't going to work.
The lower two bits of this (bits 2 and 3) are explicitly designed to fit
the C and B bits used in older architectures. Changing L_PTE_MT_VECTORS
from having value '11' to '01' changes the functionality on older CPUs.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/4] arm: mm: reordering memory type table
2020-10-23 10:16 ` Russell King - ARM Linux admin
@ 2020-10-27 8:03 ` Miles Chen
0 siblings, 0 replies; 13+ messages in thread
From: Miles Chen @ 2020-10-27 8:03 UTC (permalink / raw)
To: Russell King - ARM Linux admin
Cc: Steve Capper, wsd_upstream, Catalin Marinas, Will Deacon,
linux-kernel, Minchan Kim, Simon Horman, linux-mediatek,
Suren Baghdasaryan, linux-arm-kernel
On Fri, 2020-10-23 at 11:16 +0100, Russell King - ARM Linux admin wrote:
> On Fri, Oct 23, 2020 at 05:14:35PM +0800, Miles Chen wrote:
> > From: Minchan Kim <minchan@kernel.org>
> >
> > To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that.
> > It seems we don't need 4 bits for the memory type with ARMv6+.
> > If it's true, let's reorder bits to make bit 5 free.
> >
> > We will use the bit for L_PTE_SPECIAL in next patch.
> >
> > A note from Catalin in [1]:
> > "
> > > Anyway, on ARMv7 or ARMv6+LPAE, the non-shared device gets mapped to
> > > shared device in hardware. Looking through the arm32 code, it seems that
> > > MT_DEVICE_NONSHARED is used by arch/arm/mach-shmobile/setup-r8a7779.c
> > > and IIUC that's a v7 platform (R-Car H1, Cortex-A9). I think the above
> > > should be defined to L_PTE_MT_DEV_SHARED, unless I miss any place where
> > > DEV_NONSHARED is relevant on ARMv6 (adding Simon to confirm on shmbile).
> > "
> >
> > [1] https://lore.kernel.org/patchwork/patch/986574/
> >
> > Cc: Russell King <linux@armlinux.org.uk>
> > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Will Deacon <will.deacon@arm.com>
> > Cc: Steve Capper <steve.capper@linaro.org>
> > Cc: Simon Horman <horms@verge.net.au>
> > Cc: Minchan Kim <minchan@kernel.org>
> > Cc: Suren Baghdasaryan <surenb@google.com>
> > Signed-off-by: Minchan Kim <minchan@kernel.org>
> > Signed-off-by: Miles Chen <miles.chen@mediatek.com>
> > ---
> > arch/arm/include/asm/pgtable-2level.h | 21 +++++++++++++++++----
> > arch/arm/mm/proc-macros.S | 4 ++--
> > 2 files changed, 19 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
> > index 27a8635abea0..cdcd55cca37d 100644
> > --- a/arch/arm/include/asm/pgtable-2level.h
> > +++ b/arch/arm/include/asm/pgtable-2level.h
> > @@ -161,14 +161,27 @@
> > #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */
> > #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */
> > #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */
> > +#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
> > +#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x05) << 2) /* 0101 */
> > #define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */
> > #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */
> > -#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
> > -#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
>
> Sorry, no, this isn't going to work.
>
> The lower two bits of this (bits 2 and 3) are explicitly designed to fit
> the C and B bits used in older architectures. Changing L_PTE_MT_VECTORS
> from having value '11' to '01' changes the functionality on older CPUs.
>
thanks for the comment.
Is is possible to find other order to fit this? e.g.,
+#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x07) << 2) /* 0111 */
#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x05) << 2) /* 0101 */
or only allow this types for the new CPUs?
Miles
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 3/4] arm: mm: introduce L_PTE_SPECIAL
2020-10-23 9:14 [PATCH v2 0/4] arm: support get_user_pages_fast Miles Chen
2020-10-23 9:14 ` [PATCH v2 1/4] arm: mm: use strict p[gum]d types Miles Chen
2020-10-23 9:14 ` [PATCH v2 2/4] arm: mm: reordering memory type table Miles Chen
@ 2020-10-23 9:14 ` Miles Chen
2020-10-23 10:08 ` Russell King - ARM Linux admin
2020-10-23 9:14 ` [PATCH v2 4/4] arm: replace vector mem type with read-only type Miles Chen
3 siblings, 1 reply; 13+ messages in thread
From: Miles Chen @ 2020-10-23 9:14 UTC (permalink / raw)
To: Catalin Marinas, Russell King, Minchan Kim
Cc: Steve Capper, wsd_upstream, Will Deacon, linux-kernel,
Miles Chen, linux-mediatek, Suren Baghdasaryan, linux-arm-kernel
From: Minchan Kim <minchan@kernel.org>
This patch introduces L_PTE_SPECIAL and pte functions for supporting
get_user_pages_fast.
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Steve Capper <steve.capper@linaro.org>
Cc: Minchan Kim <minchan@kernel.org>
Cc: Suren Baghdasaryan <surenb@google.com>
Signed-off-by: Minchan Kim <minchan@kernel.org>
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
---
arch/arm/Kconfig | 4 ++--
arch/arm/include/asm/pgtable-2level.h | 1 +
arch/arm/include/asm/pgtable-3level.h | 6 ------
arch/arm/include/asm/pgtable.h | 13 +++++++++++++
4 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c18fa9d382b7..1f75864b7c7a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -13,7 +13,7 @@ config ARM
select ARCH_HAS_KCOV
select ARCH_HAS_MEMBARRIER_SYNC_CORE
select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
- select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
+ select ARCH_HAS_PTE_SPECIAL if (ARM_LPAE || CPU_V7 || CPU_V6 || CPUV6K)
select ARCH_HAS_PHYS_TO_DMA
select ARCH_HAS_SETUP_DMA_OPS
select ARCH_HAS_SET_MEMORY
@@ -82,7 +82,7 @@ config ARM
select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
select HAVE_EXIT_THREAD
- select HAVE_FAST_GUP if ARM_LPAE
+ select HAVE_FAST_GUP if (ARM_LPAE || CPU_V7 || CPU_V6 || CPUV6K)
select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
select HAVE_FUNCTION_TRACER if !XIP_KERNEL
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index cdcd55cca37d..385e7a32394e 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -117,6 +117,7 @@
#define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */
#define L_PTE_PRESENT (_AT(pteval_t, 1) << 0)
#define L_PTE_YOUNG (_AT(pteval_t, 1) << 1)
+#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 5)
#define L_PTE_DIRTY (_AT(pteval_t, 1) << 6)
#define L_PTE_RDONLY (_AT(pteval_t, 1) << 7)
#define L_PTE_USER (_AT(pteval_t, 1) << 8)
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index fbb6693c3352..46fcc6725d3e 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -175,12 +175,6 @@ static inline pmd_t *pud_page_vaddr(pud_t pud)
#define pmd_present(pmd) (pmd_isset((pmd), L_PMD_SECT_VALID))
#define pmd_young(pmd) (pmd_isset((pmd), PMD_SECT_AF))
-#define pte_special(pte) (pte_isset((pte), L_PTE_SPECIAL))
-static inline pte_t pte_mkspecial(pte_t pte)
-{
- pte_val(pte) |= L_PTE_SPECIAL;
- return pte;
-}
#define pmd_write(pmd) (pmd_isclear((pmd), L_PMD_SECT_RDONLY))
#define pmd_dirty(pmd) (pmd_isset((pmd), L_PMD_SECT_DIRTY))
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index c02f24400369..4092154ca779 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -195,6 +195,11 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
#define pte_dirty(pte) (pte_isset((pte), L_PTE_DIRTY))
#define pte_young(pte) (pte_isset((pte), L_PTE_YOUNG))
#define pte_exec(pte) (pte_isclear((pte), L_PTE_XN))
+#ifdef CONFIG_ARCH_HAS_PTE_SPECIAL
+#define pte_special(pte) (pte_isset((pte), L_PTE_SPECIAL))
+#else
+#define pte_special(pte) (0)
+#endif
#define pte_valid_user(pte) \
(pte_valid(pte) && pte_isset((pte), L_PTE_USER) && pte_young(pte))
@@ -274,6 +279,14 @@ static inline pte_t pte_mknexec(pte_t pte)
return set_pte_bit(pte, __pgprot(L_PTE_XN));
}
+#ifdef CONFIG_ARCH_HAS_PTE_SPECIAL
+static inline pte_t pte_mkspecial(pte_t pte)
+{
+ return set_pte_bit(pte, __pgprot(L_PTE_SPECIAL));
+}
+#else
+static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
+#endif
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER |
--
2.18.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 3/4] arm: mm: introduce L_PTE_SPECIAL
2020-10-23 9:14 ` [PATCH v2 3/4] arm: mm: introduce L_PTE_SPECIAL Miles Chen
@ 2020-10-23 10:08 ` Russell King - ARM Linux admin
2020-10-27 7:45 ` Miles Chen
0 siblings, 1 reply; 13+ messages in thread
From: Russell King - ARM Linux admin @ 2020-10-23 10:08 UTC (permalink / raw)
To: Miles Chen
Cc: Steve Capper, wsd_upstream, Catalin Marinas, Will Deacon,
linux-kernel, Minchan Kim, linux-mediatek, Suren Baghdasaryan,
linux-arm-kernel
On Fri, Oct 23, 2020 at 05:14:36PM +0800, Miles Chen wrote:
> From: Minchan Kim <minchan@kernel.org>
>
> This patch introduces L_PTE_SPECIAL and pte functions for supporting
> get_user_pages_fast.
>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Steve Capper <steve.capper@linaro.org>
> Cc: Minchan Kim <minchan@kernel.org>
> Cc: Suren Baghdasaryan <surenb@google.com>
> Signed-off-by: Minchan Kim <minchan@kernel.org>
> Signed-off-by: Miles Chen <miles.chen@mediatek.com>
> ---
> arch/arm/Kconfig | 4 ++--
> arch/arm/include/asm/pgtable-2level.h | 1 +
> arch/arm/include/asm/pgtable-3level.h | 6 ------
> arch/arm/include/asm/pgtable.h | 13 +++++++++++++
> 4 files changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index c18fa9d382b7..1f75864b7c7a 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -13,7 +13,7 @@ config ARM
> select ARCH_HAS_KCOV
> select ARCH_HAS_MEMBARRIER_SYNC_CORE
> select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
> - select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
> + select ARCH_HAS_PTE_SPECIAL if (ARM_LPAE || CPU_V7 || CPU_V6 || CPUV6K)
> select ARCH_HAS_PHYS_TO_DMA
> select ARCH_HAS_SETUP_DMA_OPS
> select ARCH_HAS_SET_MEMORY
> @@ -82,7 +82,7 @@ config ARM
> select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
> select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
> select HAVE_EXIT_THREAD
> - select HAVE_FAST_GUP if ARM_LPAE
> + select HAVE_FAST_GUP if (ARM_LPAE || CPU_V7 || CPU_V6 || CPUV6K)
> select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
> select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
> select HAVE_FUNCTION_TRACER if !XIP_KERNEL
> diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
> index cdcd55cca37d..385e7a32394e 100644
> --- a/arch/arm/include/asm/pgtable-2level.h
> +++ b/arch/arm/include/asm/pgtable-2level.h
> @@ -117,6 +117,7 @@
> #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */
> #define L_PTE_PRESENT (_AT(pteval_t, 1) << 0)
> #define L_PTE_YOUNG (_AT(pteval_t, 1) << 1)
> +#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 5)
How does this work? Bits 2 through 5 are already in use for the memory
type.
Repurposing this bit means that L_PTE_MT_DEV_NONSHARED,
L_PTE_MT_DEV_WC, L_PTE_MT_DEV_CACHED and L_PTE_MT_VECTORS clash with
it.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 3/4] arm: mm: introduce L_PTE_SPECIAL
2020-10-23 10:08 ` Russell King - ARM Linux admin
@ 2020-10-27 7:45 ` Miles Chen
2020-10-27 9:11 ` Russell King - ARM Linux admin
0 siblings, 1 reply; 13+ messages in thread
From: Miles Chen @ 2020-10-27 7:45 UTC (permalink / raw)
To: Russell King - ARM Linux admin
Cc: Steve Capper, wsd_upstream, Catalin Marinas, Will Deacon,
linux-kernel, Minchan Kim, linux-mediatek, Suren Baghdasaryan,
linux-arm-kernel
On Fri, 2020-10-23 at 11:08 +0100, Russell King - ARM Linux admin wrote:
> On Fri, Oct 23, 2020 at 05:14:36PM +0800, Miles Chen wrote:
> > From: Minchan Kim <minchan@kernel.org>
> >
> > This patch introduces L_PTE_SPECIAL and pte functions for supporting
> > get_user_pages_fast.
> >
> > Cc: Russell King <linux@armlinux.org.uk>
> > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Will Deacon <will.deacon@arm.com>
> > Cc: Steve Capper <steve.capper@linaro.org>
> > Cc: Minchan Kim <minchan@kernel.org>
> > Cc: Suren Baghdasaryan <surenb@google.com>
> > Signed-off-by: Minchan Kim <minchan@kernel.org>
> > Signed-off-by: Miles Chen <miles.chen@mediatek.com>
> > ---
> > arch/arm/Kconfig | 4 ++--
> > arch/arm/include/asm/pgtable-2level.h | 1 +
> > arch/arm/include/asm/pgtable-3level.h | 6 ------
> > arch/arm/include/asm/pgtable.h | 13 +++++++++++++
> > 4 files changed, 16 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index c18fa9d382b7..1f75864b7c7a 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -13,7 +13,7 @@ config ARM
> > select ARCH_HAS_KCOV
> > select ARCH_HAS_MEMBARRIER_SYNC_CORE
> > select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
> > - select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
> > + select ARCH_HAS_PTE_SPECIAL if (ARM_LPAE || CPU_V7 || CPU_V6 || CPUV6K)
> > select ARCH_HAS_PHYS_TO_DMA
> > select ARCH_HAS_SETUP_DMA_OPS
> > select ARCH_HAS_SET_MEMORY
> > @@ -82,7 +82,7 @@ config ARM
> > select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
> > select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
> > select HAVE_EXIT_THREAD
> > - select HAVE_FAST_GUP if ARM_LPAE
> > + select HAVE_FAST_GUP if (ARM_LPAE || CPU_V7 || CPU_V6 || CPUV6K)
> > select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
> > select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
> > select HAVE_FUNCTION_TRACER if !XIP_KERNEL
> > diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
> > index cdcd55cca37d..385e7a32394e 100644
> > --- a/arch/arm/include/asm/pgtable-2level.h
> > +++ b/arch/arm/include/asm/pgtable-2level.h
> > @@ -117,6 +117,7 @@
> > #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */
> > #define L_PTE_PRESENT (_AT(pteval_t, 1) << 0)
> > #define L_PTE_YOUNG (_AT(pteval_t, 1) << 1)
> > +#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 5)
>
> How does this work? Bits 2 through 5 are already in use for the memory
> type.
>
> Repurposing this bit means that L_PTE_MT_DEV_NONSHARED,
> L_PTE_MT_DEV_WC, L_PTE_MT_DEV_CACHED and L_PTE_MT_VECTORS clash with
> it.
Thanks for the comment.
The idea is to re-order the memory type table in [1] (patch v2/4) and
use bit 5 for L_PTE_SPECIAL.
[1] https://lore.kernel.org/patchwork/patch/1323893/
Miles
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 3/4] arm: mm: introduce L_PTE_SPECIAL
2020-10-27 7:45 ` Miles Chen
@ 2020-10-27 9:11 ` Russell King - ARM Linux admin
2020-11-01 12:48 ` Miles Chen
0 siblings, 1 reply; 13+ messages in thread
From: Russell King - ARM Linux admin @ 2020-10-27 9:11 UTC (permalink / raw)
To: Miles Chen
Cc: Steve Capper, wsd_upstream, Catalin Marinas, Will Deacon,
linux-kernel, Minchan Kim, linux-mediatek, Suren Baghdasaryan,
linux-arm-kernel
On Tue, Oct 27, 2020 at 03:45:12PM +0800, Miles Chen wrote:
> On Fri, 2020-10-23 at 11:08 +0100, Russell King - ARM Linux admin wrote:
> > On Fri, Oct 23, 2020 at 05:14:36PM +0800, Miles Chen wrote:
> > > From: Minchan Kim <minchan@kernel.org>
> > >
> > > This patch introduces L_PTE_SPECIAL and pte functions for supporting
> > > get_user_pages_fast.
> > >
> > > Cc: Russell King <linux@armlinux.org.uk>
> > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > Cc: Will Deacon <will.deacon@arm.com>
> > > Cc: Steve Capper <steve.capper@linaro.org>
> > > Cc: Minchan Kim <minchan@kernel.org>
> > > Cc: Suren Baghdasaryan <surenb@google.com>
> > > Signed-off-by: Minchan Kim <minchan@kernel.org>
> > > Signed-off-by: Miles Chen <miles.chen@mediatek.com>
> > > ---
> > > arch/arm/Kconfig | 4 ++--
> > > arch/arm/include/asm/pgtable-2level.h | 1 +
> > > arch/arm/include/asm/pgtable-3level.h | 6 ------
> > > arch/arm/include/asm/pgtable.h | 13 +++++++++++++
> > > 4 files changed, 16 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > > index c18fa9d382b7..1f75864b7c7a 100644
> > > --- a/arch/arm/Kconfig
> > > +++ b/arch/arm/Kconfig
> > > @@ -13,7 +13,7 @@ config ARM
> > > select ARCH_HAS_KCOV
> > > select ARCH_HAS_MEMBARRIER_SYNC_CORE
> > > select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
> > > - select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
> > > + select ARCH_HAS_PTE_SPECIAL if (ARM_LPAE || CPU_V7 || CPU_V6 || CPUV6K)
> > > select ARCH_HAS_PHYS_TO_DMA
> > > select ARCH_HAS_SETUP_DMA_OPS
> > > select ARCH_HAS_SET_MEMORY
> > > @@ -82,7 +82,7 @@ config ARM
> > > select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
> > > select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
> > > select HAVE_EXIT_THREAD
> > > - select HAVE_FAST_GUP if ARM_LPAE
> > > + select HAVE_FAST_GUP if (ARM_LPAE || CPU_V7 || CPU_V6 || CPUV6K)
> > > select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
> > > select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
> > > select HAVE_FUNCTION_TRACER if !XIP_KERNEL
> > > diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
> > > index cdcd55cca37d..385e7a32394e 100644
> > > --- a/arch/arm/include/asm/pgtable-2level.h
> > > +++ b/arch/arm/include/asm/pgtable-2level.h
> > > @@ -117,6 +117,7 @@
> > > #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */
> > > #define L_PTE_PRESENT (_AT(pteval_t, 1) << 0)
> > > #define L_PTE_YOUNG (_AT(pteval_t, 1) << 1)
> > > +#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 5)
> >
> > How does this work? Bits 2 through 5 are already in use for the memory
> > type.
> >
> > Repurposing this bit means that L_PTE_MT_DEV_NONSHARED,
> > L_PTE_MT_DEV_WC, L_PTE_MT_DEV_CACHED and L_PTE_MT_VECTORS clash with
> > it.
>
> Thanks for the comment.
> The idea is to re-order the memory type table in [1] (patch v2/4) and
> use bit 5 for L_PTE_SPECIAL.
Thanks, I know what you are trying to achieve. I don't think it's
possible without breaking the kernel on some CPUs and configurations.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 3/4] arm: mm: introduce L_PTE_SPECIAL
2020-10-27 9:11 ` Russell King - ARM Linux admin
@ 2020-11-01 12:48 ` Miles Chen
0 siblings, 0 replies; 13+ messages in thread
From: Miles Chen @ 2020-11-01 12:48 UTC (permalink / raw)
To: Russell King - ARM Linux admin
Cc: Steve Capper, wsd_upstream, Catalin Marinas, Will Deacon,
linux-kernel, Minchan Kim, linux-mediatek, Suren Baghdasaryan,
linux-arm-kernel
On Tue, 2020-10-27 at 09:11 +0000, Russell King - ARM Linux admin wrote:
> On Tue, Oct 27, 2020 at 03:45:12PM +0800, Miles Chen wrote:
> > On Fri, 2020-10-23 at 11:08 +0100, Russell King - ARM Linux admin wrote:
> > > On Fri, Oct 23, 2020 at 05:14:36PM +0800, Miles Chen wrote:
> > > > From: Minchan Kim <minchan@kernel.org>
> > > >
> > > > This patch introduces L_PTE_SPECIAL and pte functions for supporting
> > > > get_user_pages_fast.
> > > >
> > > > Cc: Russell King <linux@armlinux.org.uk>
> > > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > > Cc: Will Deacon <will.deacon@arm.com>
> > > > Cc: Steve Capper <steve.capper@linaro.org>
> > > > Cc: Minchan Kim <minchan@kernel.org>
> > > > Cc: Suren Baghdasaryan <surenb@google.com>
> > > > Signed-off-by: Minchan Kim <minchan@kernel.org>
> > > > Signed-off-by: Miles Chen <miles.chen@mediatek.com>
> > > > ---
> > > > arch/arm/Kconfig | 4 ++--
> > > > arch/arm/include/asm/pgtable-2level.h | 1 +
> > > > arch/arm/include/asm/pgtable-3level.h | 6 ------
> > > > arch/arm/include/asm/pgtable.h | 13 +++++++++++++
> > > > 4 files changed, 16 insertions(+), 8 deletions(-)
> > > >
> > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > > > index c18fa9d382b7..1f75864b7c7a 100644
> > > > --- a/arch/arm/Kconfig
> > > > +++ b/arch/arm/Kconfig
> > > > @@ -13,7 +13,7 @@ config ARM
> > > > select ARCH_HAS_KCOV
> > > > select ARCH_HAS_MEMBARRIER_SYNC_CORE
> > > > select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
> > > > - select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
> > > > + select ARCH_HAS_PTE_SPECIAL if (ARM_LPAE || CPU_V7 || CPU_V6 || CPUV6K)
> > > > select ARCH_HAS_PHYS_TO_DMA
> > > > select ARCH_HAS_SETUP_DMA_OPS
> > > > select ARCH_HAS_SET_MEMORY
> > > > @@ -82,7 +82,7 @@ config ARM
> > > > select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
> > > > select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
> > > > select HAVE_EXIT_THREAD
> > > > - select HAVE_FAST_GUP if ARM_LPAE
> > > > + select HAVE_FAST_GUP if (ARM_LPAE || CPU_V7 || CPU_V6 || CPUV6K)
> > > > select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
> > > > select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
> > > > select HAVE_FUNCTION_TRACER if !XIP_KERNEL
> > > > diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
> > > > index cdcd55cca37d..385e7a32394e 100644
> > > > --- a/arch/arm/include/asm/pgtable-2level.h
> > > > +++ b/arch/arm/include/asm/pgtable-2level.h
> > > > @@ -117,6 +117,7 @@
> > > > #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */
> > > > #define L_PTE_PRESENT (_AT(pteval_t, 1) << 0)
> > > > #define L_PTE_YOUNG (_AT(pteval_t, 1) << 1)
> > > > +#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 5)
> > >
> > > How does this work? Bits 2 through 5 are already in use for the memory
> > > type.
> > >
> > > Repurposing this bit means that L_PTE_MT_DEV_NONSHARED,
> > > L_PTE_MT_DEV_WC, L_PTE_MT_DEV_CACHED and L_PTE_MT_VECTORS clash with
> > > it.
> >
> > Thanks for the comment.
> > The idea is to re-order the memory type table in [1] (patch v2/4) and
> > use bit 5 for L_PTE_SPECIAL.
>
> Thanks, I know what you are trying to achieve. I don't think it's
> possible without breaking the kernel on some CPUs and configurations.
>
Got it. Thanks for your review.
Miles
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 4/4] arm: replace vector mem type with read-only type
2020-10-23 9:14 [PATCH v2 0/4] arm: support get_user_pages_fast Miles Chen
` (2 preceding siblings ...)
2020-10-23 9:14 ` [PATCH v2 3/4] arm: mm: introduce L_PTE_SPECIAL Miles Chen
@ 2020-10-23 9:14 ` Miles Chen
2020-10-23 10:12 ` Russell King - ARM Linux admin
3 siblings, 1 reply; 13+ messages in thread
From: Miles Chen @ 2020-10-23 9:14 UTC (permalink / raw)
To: Catalin Marinas, Russell King, Minchan Kim
Cc: wsd_upstream, linux-kernel, Miles Chen, linux-mediatek,
Suren Baghdasaryan, linux-arm-kernel
Since kernel no longer writes to the vector, try to replace
the vector mem type with read-only type and remove L_PTE_MT_VECTORS.
from Catalin in [1]:
"
> I don't think this matters since the kernel no longer writes to the
> vectors page at run-time but it needs cleaning up a bit (and testing in
> case I missed something). IOW, do we still need a dedicated mapping type
> for the vectors or we can simply use the read-only user page attributes?
"
[1] https://lore.kernel.org/patchwork/patch/986574/
Cc: Russell King <linux@armlinux.org.uk>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Minchan Kim <minchan@kernel.org>
Cc: Suren Baghdasaryan <surenb@google.com>
Signed-off-by: Miles Chen <miles.chen@mediatek.com>
---
arch/arm/include/asm/pgtable-2level.h | 1 -
arch/arm/mm/mmu.c | 7 +++----
arch/arm/mm/proc-macros.S | 2 +-
3 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index 385e7a32394e..438359d3675f 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -163,7 +163,6 @@
#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */
#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */
#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
-#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x05) << 2) /* 0101 */
#define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */
#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */
#if defined(CONFIG_CPU_V7) || defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index ab69250a86bc..0b6b377e2cce 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -536,12 +536,11 @@ static void __init build_mem_type_table(void)
#ifndef CONFIG_ARM_LPAE
/*
- * We don't use domains on ARMv6 (since this causes problems with
- * v6/v7 kernels), so we must use a separate memory type for user
- * r/o, kernel r/w to map the vectors page.
+ * We no longer write to the vector pages ar run-time, to
+ * use read-only user page attribute for vector.
*/
if (cpu_arch == CPU_ARCH_ARMv6)
- vecs_pgprot |= L_PTE_MT_VECTORS;
+ vecs_pgprot |= L_PTE_RDONLY;
/*
* Check is it with support for the PXN bit
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index dde1d6374250..f3e6551b4a7e 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -137,7 +137,7 @@
.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
.long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
- .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS
+ .long 0x00 @ unused
.long 0x00 @ L_PTE_MT_MINICACHE (not present)
.long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
.long 0x00 @ unused
--
2.18.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 4/4] arm: replace vector mem type with read-only type
2020-10-23 9:14 ` [PATCH v2 4/4] arm: replace vector mem type with read-only type Miles Chen
@ 2020-10-23 10:12 ` Russell King - ARM Linux admin
2020-10-27 7:41 ` Miles Chen
0 siblings, 1 reply; 13+ messages in thread
From: Russell King - ARM Linux admin @ 2020-10-23 10:12 UTC (permalink / raw)
To: Miles Chen
Cc: wsd_upstream, Catalin Marinas, linux-kernel, Minchan Kim,
linux-mediatek, Suren Baghdasaryan, linux-arm-kernel
On Fri, Oct 23, 2020 at 05:14:37PM +0800, Miles Chen wrote:
> Since kernel no longer writes to the vector, try to replace
> the vector mem type with read-only type and remove L_PTE_MT_VECTORS.
>
> from Catalin in [1]:
> "
> > I don't think this matters since the kernel no longer writes to the
> > vectors page at run-time but it needs cleaning up a bit (and testing in
> > case I missed something). IOW, do we still need a dedicated mapping type
> > for the vectors or we can simply use the read-only user page attributes?
> "
Catalin is incorrect. If CONFIG_KUSER_HELPERS is enabled, then the
vectors page is definitely written to - it's a user interface, so
it's not going to change:
#ifdef CONFIG_KUSER_HELPERS
/*
* User space must never try to access this
* directly. Expect your app to break
* eventually if you do so. The user helper
* at 0xffff0fe0 must be used instead. (see
* entry-armv.S for details)
*/
*((unsigned int *)0xffff0ff0) = val;
#endif
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 4/4] arm: replace vector mem type with read-only type
2020-10-23 10:12 ` Russell King - ARM Linux admin
@ 2020-10-27 7:41 ` Miles Chen
0 siblings, 0 replies; 13+ messages in thread
From: Miles Chen @ 2020-10-27 7:41 UTC (permalink / raw)
To: Russell King - ARM Linux admin
Cc: wsd_upstream, Catalin Marinas, linux-kernel, Minchan Kim,
linux-mediatek, Suren Baghdasaryan, linux-arm-kernel
On Fri, 2020-10-23 at 11:12 +0100, Russell King - ARM Linux admin wrote:
> On Fri, Oct 23, 2020 at 05:14:37PM +0800, Miles Chen wrote:
> > Since kernel no longer writes to the vector, try to replace
> > the vector mem type with read-only type and remove L_PTE_MT_VECTORS.
> >
> > from Catalin in [1]:
> > "
> > > I don't think this matters since the kernel no longer writes to the
> > > vectors page at run-time but it needs cleaning up a bit (and testing in
> > > case I missed something). IOW, do we still need a dedicated mapping type
> > > for the vectors or we can simply use the read-only user page attributes?
> > "
>
> Catalin is incorrect. If CONFIG_KUSER_HELPERS is enabled, then the
> vectors page is definitely written to - it's a user interface, so
> it's not going to change:
>
> #ifdef CONFIG_KUSER_HELPERS
> /*
> * User space must never try to access this
> * directly. Expect your app to break
> * eventually if you do so. The user helper
> * at 0xffff0fe0 must be used instead. (see
> * entry-armv.S for details)
> */
> *((unsigned int *)0xffff0ff0) = val;
> #endif
>
Thanks for the comment.
We have to keep L_PTE_MT_VECTORS for KUSER_HELPERS.
Miles
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^ permalink raw reply [flat|nested] 13+ messages in thread