* [PATCH v6 0/8] Add basic SoC support for mt6765 @ 2019-07-12 9:43 Macpaul Lin 2019-07-12 9:43 ` [PATCH v6 1/8] dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC Macpaul Lin ` (7 more replies) 0 siblings, 8 replies; 18+ messages in thread From: Macpaul Lin @ 2019-07-12 9:43 UTC (permalink / raw) To: Rob Herring, Marc Zyngier, Ryder Lee, Stephen Boyd, Sean Wang, Mars Cheng, Owen Chen, Matthias Brugger, linux-arm-kernel, linux-mediatek, linux-kernel Cc: wsd_upstream, CC Hwang, Loda Chou, devicetree, linux-serial, linux-clk, Macpaul Lin This patch adds basic SoC support for Mediatek's new 8-core SoC, MT6765, which is mainly for smartphone application. Changes in V6: 1. Adapt V5's patchset to latest kernel tree. Origin V5 patchset. https://lore.kernel.org/patchwork/cover/963612/ 2. Due to clk's common code has been submit by other platform, this patch set will have dependencies with the following patchsets as the following orders. 2.a. [v8,00/21] MT8183 IOMMU SUPPORT https://patchwork.kernel.org/cover/11023585/ 2.b. [v11,0/6] Add basic node support for Mediatek MT8183 SoC https://patchwork.kernel.org/cover/10962385/ 2.c. [v6,00/14] Mediatek MT8183 scpsys support https://patchwork.kernel.org/cover/11005751/ 3. Correct power related patches into dt-binding patches. 4. Re-order V5's 4/11, 6/11, and 7/11 due clk common code change and make dependencies in order. 5. Update some commit message in clk related patches. Changes in V5: 1. add clk support Changes in V4: 1. add gic's settings in reg properties 2. remove some patches about dt-bindings since GKH already took them Changes in V3: 1. split dt-binding document patchs 2. fix mt6765.dtsi warnings with W=12 3. remove uncessary PPI affinity for timer 4. add gicc base for gic dt node Changes in V2: 1. fix clk properties in uart dts node 2. fix typo in submit title 3. add simple-bus in mt6765.dtsi 4. use correct SPDX license format Mars Cheng (6): dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC dt-bindings: mediatek: add MT6765 power dt-bindings clk: mediatek: add mt6765 clock IDs soc: mediatek: add MT6765 scpsys and subdomain support arm64: dts: mediatek: add mt6765 support Owen Chen (2): clk: mediatek: Add MT6765 clock support arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks .../arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings/arm/mediatek/mediatek,audsys.txt | 1 + .../bindings/arm/mediatek/mediatek,camsys.txt | 1 + .../bindings/arm/mediatek/mediatek,imgsys.txt | 1 + .../arm/mediatek/mediatek,infracfg.txt | 1 + .../bindings/arm/mediatek/mediatek,mipi0a.txt | 28 + .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 + .../arm/mediatek/mediatek,pericfg.txt | 1 + .../arm/mediatek/mediatek,topckgen.txt | 1 + .../arm/mediatek/mediatek,vcodecsys.txt | 27 + .../mediatek,smi-common.txt | 1 + .../bindings/soc/mediatek/scpsys.txt | 6 + arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 + arch/arm64/boot/dts/mediatek/mt6765.dtsi | 253 +++++ arch/arm64/configs/defconfig | 6 + drivers/clk/mediatek/Kconfig | 86 ++ drivers/clk/mediatek/Makefile | 7 + drivers/clk/mediatek/clk-mt6765-audio.c | 109 ++ drivers/clk/mediatek/clk-mt6765-cam.c | 83 ++ drivers/clk/mediatek/clk-mt6765-img.c | 79 ++ drivers/clk/mediatek/clk-mt6765-mipi0a.c | 77 ++ drivers/clk/mediatek/clk-mt6765-mm.c | 105 ++ drivers/clk/mediatek/clk-mt6765-vcodec.c | 79 ++ drivers/clk/mediatek/clk-mt6765.c | 961 ++++++++++++++++++ drivers/soc/mediatek/mtk-scpsys.c | 130 +++ include/dt-bindings/clock/mt6765-clk.h | 313 ++++++ include/dt-bindings/power/mt6765-power.h | 14 + 28 files changed, 2406 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi create mode 100644 drivers/clk/mediatek/clk-mt6765-audio.c create mode 100644 drivers/clk/mediatek/clk-mt6765-cam.c create mode 100644 drivers/clk/mediatek/clk-mt6765-img.c create mode 100644 drivers/clk/mediatek/clk-mt6765-mipi0a.c create mode 100644 drivers/clk/mediatek/clk-mt6765-mm.c create mode 100644 drivers/clk/mediatek/clk-mt6765-vcodec.c create mode 100644 drivers/clk/mediatek/clk-mt6765.c create mode 100644 include/dt-bindings/clock/mt6765-clk.h create mode 100644 include/dt-bindings/power/mt6765-power.h -- 2.18.0 ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v6 1/8] dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC 2019-07-12 9:43 [PATCH v6 0/8] Add basic SoC support for mt6765 Macpaul Lin @ 2019-07-12 9:43 ` Macpaul Lin 2019-07-24 20:45 ` Rob Herring 2019-07-12 9:43 ` [PATCH v6 2/8] dt-bindings: mediatek: Add smi dts binding " Macpaul Lin ` (6 subsequent siblings) 7 siblings, 1 reply; 18+ messages in thread From: Macpaul Lin @ 2019-07-12 9:43 UTC (permalink / raw) To: Rob Herring, Marc Zyngier, Ryder Lee, Stephen Boyd, Sean Wang, Mars Cheng, Owen Chen, Matthias Brugger, linux-arm-kernel, linux-mediatek, linux-kernel Cc: wsd_upstream, CC Hwang, Loda Chou, devicetree, linux-serial, linux-clk, Macpaul Lin From: Mars Cheng <mars.cheng@mediatek.com> This patch adds the binding documentation for apmixedsys, audsys, camsys, imgsys, infracfg, mipi0a, topckgen, vcodecsys Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Owen Chen <owen.chen@mediatek.com> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> --- .../arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings/arm/mediatek/mediatek,audsys.txt | 1 + .../bindings/arm/mediatek/mediatek,camsys.txt | 1 + .../bindings/arm/mediatek/mediatek,imgsys.txt | 1 + .../arm/mediatek/mediatek,infracfg.txt | 1 + .../bindings/arm/mediatek/mediatek,mipi0a.txt | 28 +++++++++++++++++++ .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 + .../arm/mediatek/mediatek,pericfg.txt | 1 + .../arm/mediatek/mediatek,topckgen.txt | 1 + .../arm/mediatek/mediatek,vcodecsys.txt | 27 ++++++++++++++++++ 10 files changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt index 161e63a6c254..5f2757e0f844 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-apmixedsys" - "mediatek,mt2712-apmixedsys", "syscon" + - "mediatek,mt6765-apmixedsys", "syscon" - "mediatek,mt6797-apmixedsys" - "mediatek,mt7622-apmixedsys" - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt index f3cef1a6d95c..243db5275438 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-audsys", "syscon" + - "mediatek,mt6765-audsys", "syscon" - "mediatek,mt7622-audsys", "syscon" - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" - "mediatek,mt8183-audiosys", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt index d8930f64aa98..17acc4c5402c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt @@ -6,6 +6,7 @@ The MediaTek camsys controller provides various clocks to the system. Required Properties: - compatible: Should be one of: + - "mediatek,mt6765-camsys", "syscon" - "mediatek,mt8183-camsys", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt index e3bc4a1e7a6e..4e7b617acfb6 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-imgsys", "syscon" - "mediatek,mt2712-imgsys", "syscon" + - "mediatek,mt6765-imgsys", "syscon" - "mediatek,mt6797-imgsys", "syscon" - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon" - "mediatek,mt8173-imgsys", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt index a90913988d7e..6a6ffb61dd29 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt @@ -9,6 +9,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-infracfg", "syscon" - "mediatek,mt2712-infracfg", "syscon" + - "mediatek,mt6765-infracfg", "syscon" - "mediatek,mt6797-infracfg", "syscon" - "mediatek,mt7622-infracfg", "syscon" - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt new file mode 100644 index 000000000000..49313055e574 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt @@ -0,0 +1,28 @@ +Mediatek mipi0a (mipi_rx_ana_csi0a) controller +============================ + +The Mediatek mipi0a controller provides various clocks +to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt6765-mipi0a", "syscon" +- #clock-cells: Must be 1 + +The mipi0a controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +The mipi0a controller also uses the common power domain from +Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +The available power doamins are defined in dt-bindings/power/mt*-power.h. + +Example: + +mipi0a: mipi0a@11c10000 { + compatible = "mediatek,mt6765-mipi0a", "syscon"; + reg = <0 0x11c10000 0 0x1000>; + power-domains = <&scpsys MT6765_POWER_DOMAIN_CAM>; + #clock-cells = <1>; +}; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt index 545eab717c96..0c7b1698b98e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-mmsys", "syscon" - "mediatek,mt2712-mmsys", "syscon" + - "mediatek,mt6765-mmsys", "syscon" - "mediatek,mt6797-mmsys", "syscon" - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon" - "mediatek,mt8173-mmsys", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt index 4c7e478117a0..b49b40741be1 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt @@ -9,6 +9,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-pericfg", "syscon" - "mediatek,mt2712-pericfg", "syscon" + - "mediatek,mt6765-pericfg", "syscon" - "mediatek,mt7622-pericfg", "syscon" - "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon" - "mediatek,mt7629-pericfg", "syscon" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt index a023b8338960..21ad416bfeec 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-topckgen" - "mediatek,mt2712-topckgen", "syscon" + - "mediatek,mt6765-topckgen", "syscon" - "mediatek,mt6797-topckgen" - "mediatek,mt7622-topckgen" - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt new file mode 100644 index 000000000000..83f7f8634943 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt @@ -0,0 +1,27 @@ +Mediatek vcodecsys controller +============================ + +The Mediatek vcodecsys controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt6765-vcodecsys", "syscon" +- #clock-cells: Must be 1 + +The vcodecsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +The vcodecsys controller also uses the common power domain from +Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +The available power doamins are defined in dt-bindings/power/mt*-power.h. + +Example: + +venc_gcon: venc_gcon@17000000 { + compatible = "mediatek,mt6765-vcodecsys", "syscon"; + reg = <0 0x17000000 0 0x10000>; + power-domains = <&scpsys MT6765_POWER_DOMAIN_VCODEC>; + #clock-cells = <1>; +}; -- 2.18.0 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v6 1/8] dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC 2019-07-12 9:43 ` [PATCH v6 1/8] dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC Macpaul Lin @ 2019-07-24 20:45 ` Rob Herring 0 siblings, 0 replies; 18+ messages in thread From: Rob Herring @ 2019-07-24 20:45 UTC (permalink / raw) To: Macpaul Lin Cc: Marc Zyngier, Ryder Lee, Stephen Boyd, Sean Wang, Mars Cheng, Owen Chen, Matthias Brugger, linux-arm-kernel, linux-mediatek, linux-kernel, wsd_upstream, CC Hwang, Loda Chou, devicetree, linux-serial, linux-clk On Fri, Jul 12, 2019 at 05:43:37PM +0800, Macpaul Lin wrote: > From: Mars Cheng <mars.cheng@mediatek.com> > > This patch adds the binding documentation for apmixedsys, audsys, camsys, > imgsys, infracfg, mipi0a, topckgen, vcodecsys > > Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> > Signed-off-by: Owen Chen <owen.chen@mediatek.com> > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> > --- > .../arm/mediatek/mediatek,apmixedsys.txt | 1 + > .../bindings/arm/mediatek/mediatek,audsys.txt | 1 + > .../bindings/arm/mediatek/mediatek,camsys.txt | 1 + > .../bindings/arm/mediatek/mediatek,imgsys.txt | 1 + > .../arm/mediatek/mediatek,infracfg.txt | 1 + > .../bindings/arm/mediatek/mediatek,mipi0a.txt | 28 +++++++++++++++++++ > .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 + > .../arm/mediatek/mediatek,pericfg.txt | 1 + > .../arm/mediatek/mediatek,topckgen.txt | 1 + > .../arm/mediatek/mediatek,vcodecsys.txt | 27 ++++++++++++++++++ > 10 files changed, 63 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt > index 161e63a6c254..5f2757e0f844 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt > @@ -8,6 +8,7 @@ Required Properties: > - compatible: Should be one of: > - "mediatek,mt2701-apmixedsys" > - "mediatek,mt2712-apmixedsys", "syscon" > + - "mediatek,mt6765-apmixedsys", "syscon" > - "mediatek,mt6797-apmixedsys" > - "mediatek,mt7622-apmixedsys" > - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt > index f3cef1a6d95c..243db5275438 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt > @@ -7,6 +7,7 @@ Required Properties: > > - compatible: Should be one of: > - "mediatek,mt2701-audsys", "syscon" > + - "mediatek,mt6765-audsys", "syscon" > - "mediatek,mt7622-audsys", "syscon" > - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" > - "mediatek,mt8183-audiosys", "syscon" > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt > index d8930f64aa98..17acc4c5402c 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt > @@ -6,6 +6,7 @@ The MediaTek camsys controller provides various clocks to the system. > Required Properties: > > - compatible: Should be one of: > + - "mediatek,mt6765-camsys", "syscon" > - "mediatek,mt8183-camsys", "syscon" > - #clock-cells: Must be 1 > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt > index e3bc4a1e7a6e..4e7b617acfb6 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt > @@ -8,6 +8,7 @@ Required Properties: > - compatible: Should be one of: > - "mediatek,mt2701-imgsys", "syscon" > - "mediatek,mt2712-imgsys", "syscon" > + - "mediatek,mt6765-imgsys", "syscon" > - "mediatek,mt6797-imgsys", "syscon" > - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon" > - "mediatek,mt8173-imgsys", "syscon" > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt > index a90913988d7e..6a6ffb61dd29 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt > @@ -9,6 +9,7 @@ Required Properties: > - compatible: Should be one of: > - "mediatek,mt2701-infracfg", "syscon" > - "mediatek,mt2712-infracfg", "syscon" > + - "mediatek,mt6765-infracfg", "syscon" > - "mediatek,mt6797-infracfg", "syscon" > - "mediatek,mt7622-infracfg", "syscon" > - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt > new file mode 100644 > index 000000000000..49313055e574 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt > @@ -0,0 +1,28 @@ > +Mediatek mipi0a (mipi_rx_ana_csi0a) controller > +============================ > + > +The Mediatek mipi0a controller provides various clocks > +to the system. Is that all it does? > + > +Required Properties: > + > +- compatible: Should be one of: > + - "mediatek,mt6765-mipi0a", "syscon" > +- #clock-cells: Must be 1 > + > +The mipi0a controller uses the common clk binding from > +Documentation/devicetree/bindings/clock/clock-bindings.txt > +The available clocks are defined in dt-bindings/clock/mt*-clk.h. > + > +The mipi0a controller also uses the common power domain from > +Documentation/devicetree/bindings/soc/mediatek/scpsys.txt > +The available power doamins are defined in dt-bindings/power/mt*-power.h. > + > +Example: > + > +mipi0a: mipi0a@11c10000 { if so, then clock-controller@... Same question on the next one. > + compatible = "mediatek,mt6765-mipi0a", "syscon"; > + reg = <0 0x11c10000 0 0x1000>; > + power-domains = <&scpsys MT6765_POWER_DOMAIN_CAM>; > + #clock-cells = <1>; > +}; > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt > index 545eab717c96..0c7b1698b98e 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt > @@ -8,6 +8,7 @@ Required Properties: > - compatible: Should be one of: > - "mediatek,mt2701-mmsys", "syscon" > - "mediatek,mt2712-mmsys", "syscon" > + - "mediatek,mt6765-mmsys", "syscon" > - "mediatek,mt6797-mmsys", "syscon" > - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon" > - "mediatek,mt8173-mmsys", "syscon" > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt > index 4c7e478117a0..b49b40741be1 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt > @@ -9,6 +9,7 @@ Required Properties: > - compatible: Should be one of: > - "mediatek,mt2701-pericfg", "syscon" > - "mediatek,mt2712-pericfg", "syscon" > + - "mediatek,mt6765-pericfg", "syscon" > - "mediatek,mt7622-pericfg", "syscon" > - "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon" > - "mediatek,mt7629-pericfg", "syscon" > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt > index a023b8338960..21ad416bfeec 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt > @@ -8,6 +8,7 @@ Required Properties: > - compatible: Should be one of: > - "mediatek,mt2701-topckgen" > - "mediatek,mt2712-topckgen", "syscon" > + - "mediatek,mt6765-topckgen", "syscon" > - "mediatek,mt6797-topckgen" > - "mediatek,mt7622-topckgen" > - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt > new file mode 100644 > index 000000000000..83f7f8634943 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt > @@ -0,0 +1,27 @@ > +Mediatek vcodecsys controller > +============================ > + > +The Mediatek vcodecsys controller provides various clocks to the system. > + > +Required Properties: > + > +- compatible: Should be one of: > + - "mediatek,mt6765-vcodecsys", "syscon" > +- #clock-cells: Must be 1 > + > +The vcodecsys controller uses the common clk binding from > +Documentation/devicetree/bindings/clock/clock-bindings.txt > +The available clocks are defined in dt-bindings/clock/mt*-clk.h. > + > +The vcodecsys controller also uses the common power domain from > +Documentation/devicetree/bindings/soc/mediatek/scpsys.txt > +The available power doamins are defined in dt-bindings/power/mt*-power.h. > + > +Example: > + > +venc_gcon: venc_gcon@17000000 { > + compatible = "mediatek,mt6765-vcodecsys", "syscon"; > + reg = <0 0x17000000 0 0x10000>; > + power-domains = <&scpsys MT6765_POWER_DOMAIN_VCODEC>; > + #clock-cells = <1>; > +}; > -- > 2.18.0 > ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v6 2/8] dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC 2019-07-12 9:43 [PATCH v6 0/8] Add basic SoC support for mt6765 Macpaul Lin 2019-07-12 9:43 ` [PATCH v6 1/8] dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC Macpaul Lin @ 2019-07-12 9:43 ` Macpaul Lin 2019-07-12 9:43 ` [PATCH v6 3/8] dt-bindings: mediatek: add MT6765 power dt-bindings Macpaul Lin ` (5 subsequent siblings) 7 siblings, 0 replies; 18+ messages in thread From: Macpaul Lin @ 2019-07-12 9:43 UTC (permalink / raw) To: Rob Herring, Marc Zyngier, Ryder Lee, Stephen Boyd, Sean Wang, Mars Cheng, Owen Chen, Matthias Brugger, linux-arm-kernel, linux-mediatek, linux-kernel Cc: wsd_upstream, CC Hwang, Loda Chou, devicetree, linux-serial, linux-clk, Macpaul Lin From: Mars Cheng <mars.cheng@mediatek.com> This patch adds MT6765 smi binding document Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Owen Chen <owen.chen@mediatek.com> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> --- .../bindings/memory-controllers/mediatek,smi-common.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt index 01744ec6a75b..f7122d88a885 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt @@ -18,6 +18,7 @@ Required properties: - compatible : must be one of : "mediatek,mt2701-smi-common" "mediatek,mt2712-smi-common" + "mediatek,mt6765-smi-common", "syscon" "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common" "mediatek,mt8173-smi-common" "mediatek,mt8183-smi-common", "syscon" -- 2.18.0 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v6 3/8] dt-bindings: mediatek: add MT6765 power dt-bindings 2019-07-12 9:43 [PATCH v6 0/8] Add basic SoC support for mt6765 Macpaul Lin 2019-07-12 9:43 ` [PATCH v6 1/8] dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC Macpaul Lin 2019-07-12 9:43 ` [PATCH v6 2/8] dt-bindings: mediatek: Add smi dts binding " Macpaul Lin @ 2019-07-12 9:43 ` Macpaul Lin 2019-12-14 23:40 ` Matthias Brugger 2019-07-12 9:43 ` [PATCH v6 4/8] clk: mediatek: add mt6765 clock IDs Macpaul Lin ` (4 subsequent siblings) 7 siblings, 1 reply; 18+ messages in thread From: Macpaul Lin @ 2019-07-12 9:43 UTC (permalink / raw) To: Rob Herring, Marc Zyngier, Ryder Lee, Stephen Boyd, Sean Wang, Mars Cheng, Owen Chen, Matthias Brugger, linux-arm-kernel, linux-mediatek, linux-kernel Cc: wsd_upstream, CC Hwang, Loda Chou, devicetree, linux-serial, linux-clk, Macpaul Lin From: Mars Cheng <mars.cheng@mediatek.com> This adds power dt-bindings for MT6765 Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Owen Chen <owen.chen@mediatek.com> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> --- .../devicetree/bindings/soc/mediatek/scpsys.txt | 6 ++++++ include/dt-bindings/power/mt6765-power.h | 14 ++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 include/dt-bindings/power/mt6765-power.h diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt index 00eab7e6ff22..6109b4992522 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt @@ -10,6 +10,7 @@ domain control. The driver implements the Generic PM domain bindings described in power/power_domain.txt. It provides the power domains defined in - include/dt-bindings/power/mt8173-power.h +- include/dt-bindings/power/mt6765-power.h - include/dt-bindings/power/mt6797-power.h - include/dt-bindings/power/mt2701-power.h - include/dt-bindings/power/mt2712-power.h @@ -20,6 +21,7 @@ Required properties: - compatible: Should be one of: - "mediatek,mt2701-scpsys" - "mediatek,mt2712-scpsys" + - "mediatek,mt6765-scpsys" - "mediatek,mt6797-scpsys" - "mediatek,mt7622-scpsys" - "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC @@ -38,6 +40,10 @@ Required properties: enabled before releasing bus protection. Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif" Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec" + Required clocks for MT6765: MUX: "mm", "mfg" + CG: "mm-0", "mm-1", "mm-2", "mm-3", "isp-0", + "isp-1", "cam-0", "cam-1", "cam-2", + "cam-3","cam-4" Required clocks for MT6797: "mm", "mfg", "vdec" Required clocks for MT7622 or MT7629: "hif_sel" Required clocks for MT7623A: "ethif" diff --git a/include/dt-bindings/power/mt6765-power.h b/include/dt-bindings/power/mt6765-power.h new file mode 100644 index 000000000000..d347b4ee9eed --- /dev/null +++ b/include/dt-bindings/power/mt6765-power.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_POWER_MT6765_POWER_H +#define _DT_BINDINGS_POWER_MT6765_POWER_H + +#define MT6765_POWER_DOMAIN_CONN 0 +#define MT6765_POWER_DOMAIN_MM 1 +#define MT6765_POWER_DOMAIN_MFG_ASYNC 2 +#define MT6765_POWER_DOMAIN_ISP 3 +#define MT6765_POWER_DOMAIN_MFG 4 +#define MT6765_POWER_DOMAIN_MFG_CORE0 5 +#define MT6765_POWER_DOMAIN_CAM 6 +#define MT6765_POWER_DOMAIN_VCODEC 7 + +#endif /* _DT_BINDINGS_POWER_MT6765_POWER_H */ -- 2.18.0 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v6 3/8] dt-bindings: mediatek: add MT6765 power dt-bindings 2019-07-12 9:43 ` [PATCH v6 3/8] dt-bindings: mediatek: add MT6765 power dt-bindings Macpaul Lin @ 2019-12-14 23:40 ` Matthias Brugger 0 siblings, 0 replies; 18+ messages in thread From: Matthias Brugger @ 2019-12-14 23:40 UTC (permalink / raw) To: Macpaul Lin, Rob Herring, Marc Zyngier, Ryder Lee, Stephen Boyd, Sean Wang, Mars Cheng, Owen Chen, linux-arm-kernel, linux-mediatek, linux-kernel Cc: devicetree, CC Hwang, wsd_upstream, Loda Chou, linux-serial, linux-clk On 12/07/2019 11:43, Macpaul Lin wrote: > From: Mars Cheng <mars.cheng@mediatek.com> > > This adds power dt-bindings for MT6765 > > Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> > Signed-off-by: Owen Chen <owen.chen@mediatek.com> > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> > Reviewed-by: Rob Herring <robh@kernel.org> Applied to v5.5-next/soc Sorry for the delay > --- > .../devicetree/bindings/soc/mediatek/scpsys.txt | 6 ++++++ > include/dt-bindings/power/mt6765-power.h | 14 ++++++++++++++ > 2 files changed, 20 insertions(+) > create mode 100644 include/dt-bindings/power/mt6765-power.h > > diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt > index 00eab7e6ff22..6109b4992522 100644 > --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt > +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt > @@ -10,6 +10,7 @@ domain control. > The driver implements the Generic PM domain bindings described in > power/power_domain.txt. It provides the power domains defined in > - include/dt-bindings/power/mt8173-power.h > +- include/dt-bindings/power/mt6765-power.h > - include/dt-bindings/power/mt6797-power.h > - include/dt-bindings/power/mt2701-power.h > - include/dt-bindings/power/mt2712-power.h > @@ -20,6 +21,7 @@ Required properties: > - compatible: Should be one of: > - "mediatek,mt2701-scpsys" > - "mediatek,mt2712-scpsys" > + - "mediatek,mt6765-scpsys" > - "mediatek,mt6797-scpsys" > - "mediatek,mt7622-scpsys" > - "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC > @@ -38,6 +40,10 @@ Required properties: > enabled before releasing bus protection. > Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif" > Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec" > + Required clocks for MT6765: MUX: "mm", "mfg" > + CG: "mm-0", "mm-1", "mm-2", "mm-3", "isp-0", > + "isp-1", "cam-0", "cam-1", "cam-2", > + "cam-3","cam-4" > Required clocks for MT6797: "mm", "mfg", "vdec" > Required clocks for MT7622 or MT7629: "hif_sel" > Required clocks for MT7623A: "ethif" > diff --git a/include/dt-bindings/power/mt6765-power.h b/include/dt-bindings/power/mt6765-power.h > new file mode 100644 > index 000000000000..d347b4ee9eed > --- /dev/null > +++ b/include/dt-bindings/power/mt6765-power.h > @@ -0,0 +1,14 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef _DT_BINDINGS_POWER_MT6765_POWER_H > +#define _DT_BINDINGS_POWER_MT6765_POWER_H > + > +#define MT6765_POWER_DOMAIN_CONN 0 > +#define MT6765_POWER_DOMAIN_MM 1 > +#define MT6765_POWER_DOMAIN_MFG_ASYNC 2 > +#define MT6765_POWER_DOMAIN_ISP 3 > +#define MT6765_POWER_DOMAIN_MFG 4 > +#define MT6765_POWER_DOMAIN_MFG_CORE0 5 > +#define MT6765_POWER_DOMAIN_CAM 6 > +#define MT6765_POWER_DOMAIN_VCODEC 7 > + > +#endif /* _DT_BINDINGS_POWER_MT6765_POWER_H */ > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v6 4/8] clk: mediatek: add mt6765 clock IDs 2019-07-12 9:43 [PATCH v6 0/8] Add basic SoC support for mt6765 Macpaul Lin ` (2 preceding siblings ...) 2019-07-12 9:43 ` [PATCH v6 3/8] dt-bindings: mediatek: add MT6765 power dt-bindings Macpaul Lin @ 2019-07-12 9:43 ` Macpaul Lin 2019-07-24 20:46 ` Rob Herring 2019-07-12 9:43 ` [PATCH v6 5/8] clk: mediatek: Add MT6765 clock support Macpaul Lin ` (3 subsequent siblings) 7 siblings, 1 reply; 18+ messages in thread From: Macpaul Lin @ 2019-07-12 9:43 UTC (permalink / raw) To: Rob Herring, Marc Zyngier, Ryder Lee, Stephen Boyd, Sean Wang, Mars Cheng, Owen Chen, Matthias Brugger, linux-arm-kernel, linux-mediatek, linux-kernel Cc: wsd_upstream, CC Hwang, Loda Chou, devicetree, linux-serial, linux-clk, Macpaul Lin From: Mars Cheng <mars.cheng@mediatek.com> Add MT6765 clock dt-bindings, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Owen Chen <owen.chen@mediatek.com> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> --- include/dt-bindings/clock/mt6765-clk.h | 313 +++++++++++++++++++++++++ 1 file changed, 313 insertions(+) create mode 100644 include/dt-bindings/clock/mt6765-clk.h diff --git a/include/dt-bindings/clock/mt6765-clk.h b/include/dt-bindings/clock/mt6765-clk.h new file mode 100644 index 000000000000..eb97e568518e --- /dev/null +++ b/include/dt-bindings/clock/mt6765-clk.h @@ -0,0 +1,313 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_CLK_MT6765_H +#define _DT_BINDINGS_CLK_MT6765_H + +/* FIX Clks */ +#define CLK_TOP_CLK26M 0 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL_L 0 +#define CLK_APMIXED_ARMPLL 1 +#define CLK_APMIXED_CCIPLL 2 +#define CLK_APMIXED_MAINPLL 3 +#define CLK_APMIXED_MFGPLL 4 +#define CLK_APMIXED_MMPLL 5 +#define CLK_APMIXED_UNIV2PLL 6 +#define CLK_APMIXED_MSDCPLL 7 +#define CLK_APMIXED_APLL1 8 +#define CLK_APMIXED_MPLL 9 +#define CLK_APMIXED_ULPOSC1 10 +#define CLK_APMIXED_ULPOSC2 11 +#define CLK_APMIXED_SSUSB26M 12 +#define CLK_APMIXED_APPLL26M 13 +#define CLK_APMIXED_MIPIC0_26M 14 +#define CLK_APMIXED_MDPLLGP26M 15 +#define CLK_APMIXED_MMSYS_F26M 16 +#define CLK_APMIXED_UFS26M 17 +#define CLK_APMIXED_MIPIC1_26M 18 +#define CLK_APMIXED_MEMPLL26M 19 +#define CLK_APMIXED_CLKSQ_LVPLL_26M 20 +#define CLK_APMIXED_MIPID0_26M 21 +#define CLK_APMIXED_NR_CLK 22 + +/* TOPCKGEN */ +#define CLK_TOP_SYSPLL 0 +#define CLK_TOP_SYSPLL_D2 1 +#define CLK_TOP_SYSPLL1_D2 2 +#define CLK_TOP_SYSPLL1_D4 3 +#define CLK_TOP_SYSPLL1_D8 4 +#define CLK_TOP_SYSPLL1_D16 5 +#define CLK_TOP_SYSPLL_D3 6 +#define CLK_TOP_SYSPLL2_D2 7 +#define CLK_TOP_SYSPLL2_D4 8 +#define CLK_TOP_SYSPLL2_D8 9 +#define CLK_TOP_SYSPLL_D5 10 +#define CLK_TOP_SYSPLL3_D2 11 +#define CLK_TOP_SYSPLL3_D4 12 +#define CLK_TOP_SYSPLL_D7 13 +#define CLK_TOP_SYSPLL4_D2 14 +#define CLK_TOP_SYSPLL4_D4 15 +#define CLK_TOP_USB20_192M 16 +#define CLK_TOP_USB20_192M_D4 17 +#define CLK_TOP_USB20_192M_D8 18 +#define CLK_TOP_USB20_192M_D16 19 +#define CLK_TOP_USB20_192M_D32 20 +#define CLK_TOP_UNIVPLL 21 +#define CLK_TOP_UNIVPLL_D2 22 +#define CLK_TOP_UNIVPLL1_D2 23 +#define CLK_TOP_UNIVPLL1_D4 24 +#define CLK_TOP_UNIVPLL_D3 25 +#define CLK_TOP_UNIVPLL2_D2 26 +#define CLK_TOP_UNIVPLL2_D4 27 +#define CLK_TOP_UNIVPLL2_D8 28 +#define CLK_TOP_UNIVPLL2_D32 29 +#define CLK_TOP_UNIVPLL_D5 30 +#define CLK_TOP_UNIVPLL3_D2 31 +#define CLK_TOP_UNIVPLL3_D4 32 +#define CLK_TOP_MMPLL 33 +#define CLK_TOP_MMPLL_D2 34 +#define CLK_TOP_MPLL 35 +#define CLK_TOP_DA_MPLL_104M_DIV 36 +#define CLK_TOP_DA_MPLL_52M_DIV 37 +#define CLK_TOP_MFGPLL 38 +#define CLK_TOP_MSDCPLL 39 +#define CLK_TOP_MSDCPLL_D2 40 +#define CLK_TOP_APLL1 41 +#define CLK_TOP_APLL1_D2 42 +#define CLK_TOP_APLL1_D4 43 +#define CLK_TOP_APLL1_D8 44 +#define CLK_TOP_ULPOSC1 45 +#define CLK_TOP_ULPOSC1_D2 46 +#define CLK_TOP_ULPOSC1_D4 47 +#define CLK_TOP_ULPOSC1_D8 48 +#define CLK_TOP_ULPOSC1_D16 49 +#define CLK_TOP_ULPOSC1_D32 50 +#define CLK_TOP_DMPLL 51 +#define CLK_TOP_F_FRTC 52 +#define CLK_TOP_F_F26M 53 +#define CLK_TOP_AXI 54 +#define CLK_TOP_MM 55 +#define CLK_TOP_SCP 56 +#define CLK_TOP_MFG 57 +#define CLK_TOP_F_FUART 58 +#define CLK_TOP_SPI 59 +#define CLK_TOP_MSDC50_0 60 +#define CLK_TOP_MSDC30_1 61 +#define CLK_TOP_AUDIO 62 +#define CLK_TOP_AUD_1 63 +#define CLK_TOP_AUD_ENGEN1 64 +#define CLK_TOP_F_FDISP_PWM 65 +#define CLK_TOP_SSPM 66 +#define CLK_TOP_DXCC 67 +#define CLK_TOP_I2C 68 +#define CLK_TOP_F_FPWM 69 +#define CLK_TOP_F_FSENINF 70 +#define CLK_TOP_AES_FDE 71 +#define CLK_TOP_F_BIST2FPC 72 +#define CLK_TOP_ARMPLL_DIVIDER_PLL0 73 +#define CLK_TOP_ARMPLL_DIVIDER_PLL1 74 +#define CLK_TOP_ARMPLL_DIVIDER_PLL2 75 +#define CLK_TOP_DA_USB20_48M_DIV 76 +#define CLK_TOP_DA_UNIV_48M_DIV 77 +#define CLK_TOP_APLL12_DIV0 78 +#define CLK_TOP_APLL12_DIV1 79 +#define CLK_TOP_APLL12_DIV2 80 +#define CLK_TOP_APLL12_DIV3 81 +#define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN 82 +#define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN 83 +#define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN 84 +#define CLK_TOP_FMEM_OCC_DRC_EN 85 +#define CLK_TOP_USB20_48M_EN 86 +#define CLK_TOP_UNIVPLL_48M_EN 87 +#define CLK_TOP_MPLL_104M_EN 88 +#define CLK_TOP_MPLL_52M_EN 89 +#define CLK_TOP_F_UFS_MP_SAP_CFG_EN 90 +#define CLK_TOP_F_BIST2FPC_EN 91 +#define CLK_TOP_MD_32K 92 +#define CLK_TOP_MD_26M 93 +#define CLK_TOP_MD2_32K 94 +#define CLK_TOP_MD2_26M 95 +#define CLK_TOP_AXI_SEL 96 +#define CLK_TOP_MEM_SEL 97 +#define CLK_TOP_MM_SEL 98 +#define CLK_TOP_SCP_SEL 99 +#define CLK_TOP_MFG_SEL 100 +#define CLK_TOP_ATB_SEL 101 +#define CLK_TOP_CAMTG_SEL 102 +#define CLK_TOP_CAMTG1_SEL 103 +#define CLK_TOP_CAMTG2_SEL 104 +#define CLK_TOP_CAMTG3_SEL 105 +#define CLK_TOP_UART_SEL 106 +#define CLK_TOP_SPI_SEL 107 +#define CLK_TOP_MSDC50_0_HCLK_SEL 108 +#define CLK_TOP_MSDC50_0_SEL 109 +#define CLK_TOP_MSDC30_1_SEL 110 +#define CLK_TOP_AUDIO_SEL 111 +#define CLK_TOP_AUD_INTBUS_SEL 112 +#define CLK_TOP_AUD_1_SEL 113 +#define CLK_TOP_AUD_ENGEN1_SEL 114 +#define CLK_TOP_DISP_PWM_SEL 115 +#define CLK_TOP_SSPM_SEL 116 +#define CLK_TOP_DXCC_SEL 117 +#define CLK_TOP_USB_TOP_SEL 118 +#define CLK_TOP_SPM_SEL 119 +#define CLK_TOP_I2C_SEL 120 +#define CLK_TOP_PWM_SEL 121 +#define CLK_TOP_SENINF_SEL 122 +#define CLK_TOP_AES_FDE_SEL 123 +#define CLK_TOP_PWRAP_ULPOSC_SEL 124 +#define CLK_TOP_CAMTM_SEL 125 +#define CLK_TOP_NR_CLK 126 + +/* INFRACFG */ +#define CLK_IFR_ICUSB 0 +#define CLK_IFR_GCE 1 +#define CLK_IFR_THERM 2 +#define CLK_IFR_I2C_AP 3 +#define CLK_IFR_I2C_CCU 4 +#define CLK_IFR_I2C_SSPM 5 +#define CLK_IFR_I2C_RSV 6 +#define CLK_IFR_PWM_HCLK 7 +#define CLK_IFR_PWM1 8 +#define CLK_IFR_PWM2 9 +#define CLK_IFR_PWM3 10 +#define CLK_IFR_PWM4 11 +#define CLK_IFR_PWM5 12 +#define CLK_IFR_PWM 13 +#define CLK_IFR_UART0 14 +#define CLK_IFR_UART1 15 +#define CLK_IFR_GCE_26M 16 +#define CLK_IFR_CQ_DMA_FPC 17 +#define CLK_IFR_BTIF 18 +#define CLK_IFR_SPI0 19 +#define CLK_IFR_MSDC0 20 +#define CLK_IFR_MSDC1 21 +#define CLK_IFR_TRNG 22 +#define CLK_IFR_AUXADC 23 +#define CLK_IFR_CCIF1_AP 24 +#define CLK_IFR_CCIF1_MD 25 +#define CLK_IFR_AUXADC_MD 26 +#define CLK_IFR_AP_DMA 27 +#define CLK_IFR_DEVICE_APC 28 +#define CLK_IFR_CCIF_AP 29 +#define CLK_IFR_AUDIO 30 +#define CLK_IFR_CCIF_MD 31 +#define CLK_IFR_RG_PWM_FBCLK6 32 +#define CLK_IFR_DISP_PWM 33 +#define CLK_IFR_CLDMA_BCLK 34 +#define CLK_IFR_AUDIO_26M_BCLK 35 +#define CLK_IFR_SPI1 36 +#define CLK_IFR_I2C4 37 +#define CLK_IFR_SPI2 38 +#define CLK_IFR_SPI3 39 +#define CLK_IFR_I2C5 40 +#define CLK_IFR_I2C5_ARBITER 41 +#define CLK_IFR_I2C5_IMM 42 +#define CLK_IFR_I2C1_ARBITER 43 +#define CLK_IFR_I2C1_IMM 44 +#define CLK_IFR_I2C2_ARBITER 45 +#define CLK_IFR_I2C2_IMM 46 +#define CLK_IFR_SPI4 47 +#define CLK_IFR_SPI5 48 +#define CLK_IFR_CQ_DMA 49 +#define CLK_IFR_FAES_FDE 50 +#define CLK_IFR_MSDC0_SELF 51 +#define CLK_IFR_MSDC1_SELF 52 +#define CLK_IFR_I2C6 53 +#define CLK_IFR_AP_MSDC0 54 +#define CLK_IFR_MD_MSDC0 55 +#define CLK_IFR_MSDC0_SRC 56 +#define CLK_IFR_MSDC1_SRC 57 +#define CLK_IFR_AES_TOP0_BCLK 58 +#define CLK_IFR_MCU_PM_BCLK 59 +#define CLK_IFR_CCIF2_AP 60 +#define CLK_IFR_CCIF2_MD 61 +#define CLK_IFR_CCIF3_AP 62 +#define CLK_IFR_CCIF3_MD 63 +#define CLK_IFR_NR_CLK 64 + +/* AUDIO */ +#define CLK_AUDIO_AFE 0 +#define CLK_AUDIO_22M 1 +#define CLK_AUDIO_APLL_TUNER 2 +#define CLK_AUDIO_ADC 3 +#define CLK_AUDIO_DAC 4 +#define CLK_AUDIO_DAC_PREDIS 5 +#define CLK_AUDIO_TML 6 +#define CLK_AUDIO_I2S1_BCLK 7 +#define CLK_AUDIO_I2S2_BCLK 8 +#define CLK_AUDIO_I2S3_BCLK 9 +#define CLK_AUDIO_I2S4_BCLK 10 +#define CLK_AUDIO_NR_CLK 11 + +/* MIPI_RX_ANA_CSI0A */ + +#define CLK_MIPI0A_CSR_CSI_EN_0A 0 +#define CLK_MIPI0A_NR_CLK 1 + +/* MMSYS_CONFIG */ + +#define CLK_MM_MDP_RDMA0 0 +#define CLK_MM_MDP_CCORR0 1 +#define CLK_MM_MDP_RSZ0 2 +#define CLK_MM_MDP_RSZ1 3 +#define CLK_MM_MDP_TDSHP0 4 +#define CLK_MM_MDP_WROT0 5 +#define CLK_MM_MDP_WDMA0 6 +#define CLK_MM_DISP_OVL0 7 +#define CLK_MM_DISP_OVL0_2L 8 +#define CLK_MM_DISP_RSZ0 9 +#define CLK_MM_DISP_RDMA0 10 +#define CLK_MM_DISP_WDMA0 11 +#define CLK_MM_DISP_COLOR0 12 +#define CLK_MM_DISP_CCORR0 13 +#define CLK_MM_DISP_AAL0 14 +#define CLK_MM_DISP_GAMMA0 15 +#define CLK_MM_DISP_DITHER0 16 +#define CLK_MM_DSI0 17 +#define CLK_MM_FAKE_ENG 18 +#define CLK_MM_SMI_COMMON 19 +#define CLK_MM_SMI_LARB0 20 +#define CLK_MM_SMI_COMM0 21 +#define CLK_MM_SMI_COMM1 22 +#define CLK_MM_CAM_MDP 23 +#define CLK_MM_SMI_IMG 24 +#define CLK_MM_SMI_CAM 25 +#define CLK_MM_IMG_DL_RELAY 26 +#define CLK_MM_IMG_DL_ASYNC_TOP 27 +#define CLK_MM_DIG_DSI 28 +#define CLK_MM_F26M_HRTWT 29 +#define CLK_MM_NR_CLK 30 + +/* IMGSYS */ + +#define CLK_IMG_LARB2 0 +#define CLK_IMG_DIP 1 +#define CLK_IMG_FDVT 2 +#define CLK_IMG_DPE 3 +#define CLK_IMG_RSC 4 +#define CLK_IMG_NR_CLK 5 + +/* VENCSYS */ + +#define CLK_VENC_SET0_LARB 0 +#define CLK_VENC_SET1_VENC 1 +#define CLK_VENC_SET2_JPGENC 2 +#define CLK_VENC_SET3_VDEC 3 +#define CLK_VENC_NR_CLK 4 + +/* CAMSYS */ + +#define CLK_CAM_LARB3 0 +#define CLK_CAM_DFP_VAD 1 +#define CLK_CAM 2 +#define CLK_CAMTG 3 +#define CLK_CAM_SENINF 4 +#define CLK_CAMSV0 5 +#define CLK_CAMSV1 6 +#define CLK_CAMSV2 7 +#define CLK_CAM_CCU 8 +#define CLK_CAM_NR_CLK 9 + +#endif /* _DT_BINDINGS_CLK_MT6765_H */ -- 2.18.0 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v6 4/8] clk: mediatek: add mt6765 clock IDs 2019-07-12 9:43 ` [PATCH v6 4/8] clk: mediatek: add mt6765 clock IDs Macpaul Lin @ 2019-07-24 20:46 ` Rob Herring 0 siblings, 0 replies; 18+ messages in thread From: Rob Herring @ 2019-07-24 20:46 UTC (permalink / raw) Cc: Sean Wang, Mars Cheng, Owen Chen, Matthias Brugger, linux-arm-kernel, linux-mediatek, linux-kernel, wsd_upstream, CC Hwang, Loda Chou, devicetree, linux-serial, linux-clk, Macpaul Lin On Fri, 12 Jul 2019 17:43:40 +0800, Macpaul Lin wrote: > From: Mars Cheng <mars.cheng@mediatek.com> > > Add MT6765 clock dt-bindings, include topckgen, apmixedsys, > infracfg, mcucfg and subsystem clocks. > > Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> > Signed-off-by: Owen Chen <owen.chen@mediatek.com> > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> > --- > include/dt-bindings/clock/mt6765-clk.h | 313 +++++++++++++++++++++++++ > 1 file changed, 313 insertions(+) > create mode 100644 include/dt-bindings/clock/mt6765-clk.h > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v6 5/8] clk: mediatek: Add MT6765 clock support 2019-07-12 9:43 [PATCH v6 0/8] Add basic SoC support for mt6765 Macpaul Lin ` (3 preceding siblings ...) 2019-07-12 9:43 ` [PATCH v6 4/8] clk: mediatek: add mt6765 clock IDs Macpaul Lin @ 2019-07-12 9:43 ` Macpaul Lin 2019-08-15 0:27 ` Stephen Boyd 2019-07-12 9:43 ` [PATCH v6 6/8] soc: mediatek: add MT6765 scpsys and subdomain support Macpaul Lin ` (2 subsequent siblings) 7 siblings, 1 reply; 18+ messages in thread From: Macpaul Lin @ 2019-07-12 9:43 UTC (permalink / raw) To: Rob Herring, Marc Zyngier, Ryder Lee, Stephen Boyd, Sean Wang, Mars Cheng, Owen Chen, Matthias Brugger, linux-arm-kernel, linux-mediatek, linux-kernel Cc: wsd_upstream, CC Hwang, Loda Chou, devicetree, linux-serial, linux-clk, Macpaul Lin From: Owen Chen <owen.chen@mediatek.com> Add MT6765 clock support, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Owen Chen <owen.chen@mediatek.com> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> --- drivers/clk/mediatek/Kconfig | 86 ++ drivers/clk/mediatek/Makefile | 7 + drivers/clk/mediatek/clk-mt6765-audio.c | 109 +++ drivers/clk/mediatek/clk-mt6765-cam.c | 83 ++ drivers/clk/mediatek/clk-mt6765-img.c | 79 ++ drivers/clk/mediatek/clk-mt6765-mipi0a.c | 77 ++ drivers/clk/mediatek/clk-mt6765-mm.c | 105 +++ drivers/clk/mediatek/clk-mt6765-vcodec.c | 79 ++ drivers/clk/mediatek/clk-mt6765.c | 961 +++++++++++++++++++++++ 9 files changed, 1586 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6765-audio.c create mode 100644 drivers/clk/mediatek/clk-mt6765-cam.c create mode 100644 drivers/clk/mediatek/clk-mt6765-img.c create mode 100644 drivers/clk/mediatek/clk-mt6765-mipi0a.c create mode 100644 drivers/clk/mediatek/clk-mt6765-mm.c create mode 100644 drivers/clk/mediatek/clk-mt6765-vcodec.c create mode 100644 drivers/clk/mediatek/clk-mt6765.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 4d8a9aef95f6..1a8db28f9d10 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -116,6 +116,92 @@ config COMMON_CLK_MT2712_VENCSYS ---help--- This driver supports MediaTek MT2712 vencsys clocks. +config COMMON_CLK_MT6765 + bool "Clock driver for MediaTek MT6765" + depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST + select COMMON_CLK_MEDIATEK + default ARCH_MEDIATEK && ARM64 + help + This driver supports MediaTek MT6765 basic clocks. + +config COMMON_CLK_MT6765_AUDIOSYS + bool "Clock driver for MediaTek MT6765 audiosys" + depends on COMMON_CLK_MT6765 + help + This driver supports MediaTek MT6765 audiosys clocks. + +config COMMON_CLK_MT6765_CAMSYS + bool "Clock driver for MediaTek MT6765 camsys" + depends on COMMON_CLK_MT6765 + help + This driver supports MediaTek MT6765 camsys clocks. + +config COMMON_CLK_MT6765_GCESYS + bool "Clock driver for MediaTek MT6765 gcesys" + depends on COMMON_CLK_MT6765 + help + This driver supports MediaTek MT6765 gcesys clocks. + +config COMMON_CLK_MT6765_MMSYS + bool "Clock driver for MediaTek MT6765 mmsys" + depends on COMMON_CLK_MT6765 + help + This driver supports MediaTek MT6765 mmsys clocks. + +config COMMON_CLK_MT6765_IMGSYS + bool "Clock driver for MediaTek MT6765 imgsys" + depends on COMMON_CLK_MT6765 + help + This driver supports MediaTek MT6765 imgsys clocks. + +config COMMON_CLK_MT6765_VCODECSYS + bool "Clock driver for MediaTek MT6765 vcodecsys" + depends on COMMON_CLK_MT6765 + help + This driver supports MediaTek MT6765 vcodecsys clocks. + +config COMMON_CLK_MT6765_MFGSYS + bool "Clock driver for MediaTek MT6765 mfgsys" + depends on COMMON_CLK_MT6765 + help + This driver supports MediaTek MT6765 mfgsys clocks. + +config COMMON_CLK_MT6765_MIPI0ASYS + bool "Clock driver for MediaTek MT6765 mipi0asys" + depends on COMMON_CLK_MT6765 + help + This driver supports MediaTek MT6765 mipi0asys clocks. + +config COMMON_CLK_MT6765_MIPI0BSYS + bool "Clock driver for MediaTek MT6765 mipi0bsys" + depends on COMMON_CLK_MT6765 + help + This driver supports MediaTek MT6765 mipi0bsys clocks. + +config COMMON_CLK_MT6765_MIPI1ASYS + bool "Clock driver for MediaTek MT6765 mipi1asys" + depends on COMMON_CLK_MT6765 + help + This driver supports MediaTek MT6765 mipi1asys clocks. + +config COMMON_CLK_MT6765_MIPI1BSYS + bool "Clock driver for MediaTek MT6765 mipi1bsys" + depends on COMMON_CLK_MT6765 + help + This driver supports MediaTek MT6765 mipi1bsys clocks. + +config COMMON_CLK_MT6765_MIPI2ASYS + bool "Clock driver for MediaTek MT6765 mipi2asys" + depends on COMMON_CLK_MT6765 + help + This driver supports MediaTek MT6765 mipi2asys clocks. + +config COMMON_CLK_MT6765_MIPI2BSYS + bool "Clock driver for MediaTek MT6765 mipi2bsys" + depends on COMMON_CLK_MT6765 + help + This driver supports MediaTek MT6765 mipi2bsys clocks. + config COMMON_CLK_MT6797 bool "Clock driver for MediaTek MT6797" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index f74937b35f68..c368442914a8 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -1,6 +1,13 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o +obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o +obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o +obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o +obj-$(CONFIG_COMMON_CLK_MT6765_IMGSYS) += clk-mt6765-img.o +obj-$(CONFIG_COMMON_CLK_MT6765_MIPI0ASYS) += clk-mt6765-mipi0a.o +obj-$(CONFIG_COMMON_CLK_MT6765_MMSYS) += clk-mt6765-mm.o +obj-$(CONFIG_COMMON_CLK_MT6765_VCODECSYS) += clk-mt6765-vcodec.o obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o diff --git a/drivers/clk/mediatek/clk-mt6765-audio.c b/drivers/clk/mediatek/clk-mt6765-audio.c new file mode 100644 index 000000000000..41f19343dfb9 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6765-audio.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Owen Chen <owen.chen@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include <dt-bindings/clock/mt6765-clk.h> + +static const struct mtk_gate_regs audio0_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x0, + .sta_ofs = 0x0, +}; + +static const struct mtk_gate_regs audio1_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x4, + .sta_ofs = 0x4, +}; + +#define GATE_AUDIO0(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &audio0_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr, \ + } + +#define GATE_AUDIO1(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &audio1_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr, \ + } + +static const struct mtk_gate audio_clks[] = { + /* AUDIO0 */ + GATE_AUDIO0(CLK_AUDIO_AFE, "aud_afe", "audio_ck", 2), + GATE_AUDIO0(CLK_AUDIO_22M, "aud_22m", "aud_engen1_ck", 8), + GATE_AUDIO0(CLK_AUDIO_APLL_TUNER, "aud_apll_tuner", + "aud_engen1_ck", 19), + GATE_AUDIO0(CLK_AUDIO_ADC, "aud_adc", "audio_ck", 24), + GATE_AUDIO0(CLK_AUDIO_DAC, "aud_dac", "audio_ck", 25), + GATE_AUDIO0(CLK_AUDIO_DAC_PREDIS, "aud_dac_predis", + "audio_ck", 26), + GATE_AUDIO0(CLK_AUDIO_TML, "aud_tml", "audio_ck", 27), + /* AUDIO1 */ + GATE_AUDIO1(CLK_AUDIO_I2S1_BCLK, "aud_i2s1_bclk", + "audio_ck", 4), + GATE_AUDIO1(CLK_AUDIO_I2S2_BCLK, "aud_i2s2_bclk", + "audio_ck", 5), + GATE_AUDIO1(CLK_AUDIO_I2S3_BCLK, "aud_i2s3_bclk", + "audio_ck", 6), + GATE_AUDIO1(CLK_AUDIO_I2S4_BCLK, "aud_i2s4_bclk", + "audio_ck", 7), +}; + +static int clk_mt6765_audio_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + int r; + struct device_node *node = pdev->dev.of_node; + + clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); + + mtk_clk_register_gates(node, audio_clks, + ARRAY_SIZE(audio_clks), clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + + return r; +} + +static const struct of_device_id of_match_clk_mt6765_audio[] = { + { .compatible = "mediatek,mt6765-audsys", }, + {} +}; + +static struct platform_driver clk_mt6765_audio_drv = { + .probe = clk_mt6765_audio_probe, + .driver = { + .name = "clk-mt6765-audio", + .of_match_table = of_match_clk_mt6765_audio, + }, +}; + +builtin_platform_driver(clk_mt6765_audio_drv); diff --git a/drivers/clk/mediatek/clk-mt6765-cam.c b/drivers/clk/mediatek/clk-mt6765-cam.c new file mode 100644 index 000000000000..d0542f07192c --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6765-cam.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Owen Chen <owen.chen@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include <dt-bindings/clock/mt6765-clk.h> + +static const struct mtk_gate_regs cam_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_CAM(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &cam_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +static const struct mtk_gate cam_clks[] = { + GATE_CAM(CLK_CAM_LARB3, "cam_larb3", "mm_ck", 0), + GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "mm_ck", 1), + GATE_CAM(CLK_CAM, "cam", "mm_ck", 6), + GATE_CAM(CLK_CAMTG, "camtg", "mm_ck", 7), + GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "mm_ck", 8), + GATE_CAM(CLK_CAMSV0, "camsv0", "mm_ck", 9), + GATE_CAM(CLK_CAMSV1, "camsv1", "mm_ck", 10), + GATE_CAM(CLK_CAMSV2, "camsv2", "mm_ck", 11), + GATE_CAM(CLK_CAM_CCU, "cam_ccu", "mm_ck", 12), +}; + +static int clk_mt6765_cam_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + int r; + struct device_node *node = pdev->dev.of_node; + + clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK); + + mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks), clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + + return r; +} + +static const struct of_device_id of_match_clk_mt6765_cam[] = { + { .compatible = "mediatek,mt6765-camsys", }, + {} +}; + +static struct platform_driver clk_mt6765_cam_drv = { + .probe = clk_mt6765_cam_probe, + .driver = { + .name = "clk-mt6765-cam", + .of_match_table = of_match_clk_mt6765_cam, + }, +}; + +builtin_platform_driver(clk_mt6765_cam_drv); diff --git a/drivers/clk/mediatek/clk-mt6765-img.c b/drivers/clk/mediatek/clk-mt6765-img.c new file mode 100644 index 000000000000..eaf8c25ce8b6 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6765-img.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Owen Chen <owen.chen@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include <dt-bindings/clock/mt6765-clk.h> + +static const struct mtk_gate_regs img_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_IMG(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &img_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +static const struct mtk_gate img_clks[] = { + GATE_IMG(CLK_IMG_LARB2, "img_larb2", "mm_ck", 0), + GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_ck", 2), + GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_ck", 3), + GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_ck", 4), + GATE_IMG(CLK_IMG_RSC, "img_rsc", "mm_ck", 5), +}; + +static int clk_mt6765_img_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + int r; + struct device_node *node = pdev->dev.of_node; + + clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK); + + mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + + return r; +} + +static const struct of_device_id of_match_clk_mt6765_img[] = { + { .compatible = "mediatek,mt6765-imgsys", }, + {} +}; + +static struct platform_driver clk_mt6765_img_drv = { + .probe = clk_mt6765_img_probe, + .driver = { + .name = "clk-mt6765-img", + .of_match_table = of_match_clk_mt6765_img, + }, +}; + +builtin_platform_driver(clk_mt6765_img_drv); diff --git a/drivers/clk/mediatek/clk-mt6765-mipi0a.c b/drivers/clk/mediatek/clk-mt6765-mipi0a.c new file mode 100644 index 000000000000..f6c45326dd52 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6765-mipi0a.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Owen Chen <owen.chen@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include <dt-bindings/clock/mt6765-clk.h> + +static const struct mtk_gate_regs mipi0a_cg_regs = { + .set_ofs = 0x80, + .clr_ofs = 0x80, + .sta_ofs = 0x80, +}; + +#define GATE_MIPI0A(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &mipi0a_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate mipi0a_clks[] = { + GATE_MIPI0A(CLK_MIPI0A_CSR_CSI_EN_0A, + "mipi0a_csr_0a", "f_fseninf_ck", 1), +}; + +static int clk_mt6765_mipi0a_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + int r; + struct device_node *node = pdev->dev.of_node; + + clk_data = mtk_alloc_clk_data(CLK_MIPI0A_NR_CLK); + + mtk_clk_register_gates(node, mipi0a_clks, + ARRAY_SIZE(mipi0a_clks), clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + + return r; +} + +static const struct of_device_id of_match_clk_mt6765_mipi0a[] = { + { .compatible = "mediatek,mt6765-mipi0a", }, + {} +}; + +static struct platform_driver clk_mt6765_mipi0a_drv = { + .probe = clk_mt6765_mipi0a_probe, + .driver = { + .name = "clk-mt6765-mipi0a", + .of_match_table = of_match_clk_mt6765_mipi0a, + }, +}; + +builtin_platform_driver(clk_mt6765_mipi0a_drv); diff --git a/drivers/clk/mediatek/clk-mt6765-mm.c b/drivers/clk/mediatek/clk-mt6765-mm.c new file mode 100644 index 000000000000..97b13fe3a4fe --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6765-mm.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Owen Chen <owen.chen@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include <dt-bindings/clock/mt6765-clk.h> + +static const struct mtk_gate_regs mm_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +#define GATE_MM(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &mm_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +static const struct mtk_gate mm_clks[] = { + /* MM */ + GATE_MM(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_ck", 0), + GATE_MM(CLK_MM_MDP_CCORR0, "mm_mdp_ccorr0", "mm_ck", 1), + GATE_MM(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_ck", 2), + GATE_MM(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_ck", 3), + GATE_MM(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_ck", 4), + GATE_MM(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_ck", 5), + GATE_MM(CLK_MM_MDP_WDMA0, "mm_mdp_wdma0", "mm_ck", 6), + GATE_MM(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_ck", 7), + GATE_MM(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_ck", 8), + GATE_MM(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "mm_ck", 9), + GATE_MM(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_ck", 10), + GATE_MM(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_ck", 11), + GATE_MM(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_ck", 12), + GATE_MM(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_ck", 13), + GATE_MM(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_ck", 14), + GATE_MM(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_ck", 15), + GATE_MM(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_ck", 16), + GATE_MM(CLK_MM_DSI0, "mm_dsi0", "mm_ck", 17), + GATE_MM(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_ck", 18), + GATE_MM(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_ck", 19), + GATE_MM(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_ck", 20), + GATE_MM(CLK_MM_SMI_COMM0, "mm_smi_comm0", "mm_ck", 21), + GATE_MM(CLK_MM_SMI_COMM1, "mm_smi_comm1", "mm_ck", 22), + GATE_MM(CLK_MM_CAM_MDP, "mm_cam_mdp_ck", "mm_ck", 23), + GATE_MM(CLK_MM_SMI_IMG, "mm_smi_img_ck", "mm_ck", 24), + GATE_MM(CLK_MM_SMI_CAM, "mm_smi_cam_ck", "mm_ck", 25), + GATE_MM(CLK_MM_IMG_DL_RELAY, "mm_img_dl_relay", "mm_ck", 26), + GATE_MM(CLK_MM_IMG_DL_ASYNC_TOP, "mm_imgdl_async", "mm_ck", 27), + GATE_MM(CLK_MM_DIG_DSI, "mm_dig_dsi_ck", "mm_ck", 28), + GATE_MM(CLK_MM_F26M_HRTWT, "mm_hrtwt", "f_f26m_ck", 29), +}; + +static int clk_mt6765_mm_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + int r; + struct device_node *node = pdev->dev.of_node; + + clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); + + mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + + return r; +} + +static const struct of_device_id of_match_clk_mt6765_mm[] = { + { .compatible = "mediatek,mt6765-mmsys", }, + {} +}; + +static struct platform_driver clk_mt6765_mm_drv = { + .probe = clk_mt6765_mm_probe, + .driver = { + .name = "clk-mt6765-mm", + .of_match_table = of_match_clk_mt6765_mm, + }, +}; + +builtin_platform_driver(clk_mt6765_mm_drv); diff --git a/drivers/clk/mediatek/clk-mt6765-vcodec.c b/drivers/clk/mediatek/clk-mt6765-vcodec.c new file mode 100644 index 000000000000..eb9ae1c2c99c --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6765-vcodec.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Owen Chen <owen.chen@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include <dt-bindings/clock/mt6765-clk.h> + +static const struct mtk_gate_regs venc_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_VENC(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &venc_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr_inv, \ + } + +static const struct mtk_gate venc_clks[] = { + GATE_VENC(CLK_VENC_SET0_LARB, "venc_set0_larb", "mm_ck", 0), + GATE_VENC(CLK_VENC_SET1_VENC, "venc_set1_venc", "mm_ck", 4), + GATE_VENC(CLK_VENC_SET2_JPGENC, "jpgenc", "mm_ck", 8), + GATE_VENC(CLK_VENC_SET3_VDEC, "venc_set3_vdec", "mm_ck", 12), +}; + +static int clk_mt6765_vcodec_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + int r; + struct device_node *node = pdev->dev.of_node; + + clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK); + + mtk_clk_register_gates(node, venc_clks, + ARRAY_SIZE(venc_clks), clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + + return r; +} + +static const struct of_device_id of_match_clk_mt6765_vcodec[] = { + { .compatible = "mediatek,mt6765-vcodecsys", }, + {} +}; + +static struct platform_driver clk_mt6765_vcodec_drv = { + .probe = clk_mt6765_vcodec_probe, + .driver = { + .name = "clk-mt6765-vcodec", + .of_match_table = of_match_clk_mt6765_vcodec, + }, +}; + +builtin_platform_driver(clk_mt6765_vcodec_drv); diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c new file mode 100644 index 000000000000..f716a48a926d --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6765.c @@ -0,0 +1,961 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Owen Chen <owen.chen@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk-provider.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/slab.h> +#include <linux/mfd/syscon.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" + +#include <dt-bindings/clock/mt6765-clk.h> + +/*fmeter div select 4*/ +#define _DIV4_ 1 + +static DEFINE_SPINLOCK(mt6765_clk_lock); + +/* Total 12 subsys */ +static void __iomem *cksys_base; +static void __iomem *apmixed_base; + +/* CKSYS */ +#define CLK_SCP_CFG_0 (cksys_base + 0x200) +#define CLK_SCP_CFG_1 (cksys_base + 0x204) + +/* CG */ +#define AP_PLL_CON3 (apmixed_base + 0x0C) +#define PLLON_CON0 (apmixed_base + 0x44) +#define PLLON_CON1 (apmixed_base + 0x48) + +/* clk cfg update */ +#define CLK_CFG_0 0x40 +#define CLK_CFG_0_SET 0x44 +#define CLK_CFG_0_CLR 0x48 +#define CLK_CFG_1 0x50 +#define CLK_CFG_1_SET 0x54 +#define CLK_CFG_1_CLR 0x58 +#define CLK_CFG_2 0x60 +#define CLK_CFG_2_SET 0x64 +#define CLK_CFG_2_CLR 0x68 +#define CLK_CFG_3 0x70 +#define CLK_CFG_3_SET 0x74 +#define CLK_CFG_3_CLR 0x78 +#define CLK_CFG_4 0x80 +#define CLK_CFG_4_SET 0x84 +#define CLK_CFG_4_CLR 0x88 +#define CLK_CFG_5 0x90 +#define CLK_CFG_5_SET 0x94 +#define CLK_CFG_5_CLR 0x98 +#define CLK_CFG_6 0xa0 +#define CLK_CFG_6_SET 0xa4 +#define CLK_CFG_6_CLR 0xa8 +#define CLK_CFG_7 0xb0 +#define CLK_CFG_7_SET 0xb4 +#define CLK_CFG_7_CLR 0xb8 +#define CLK_CFG_8 0xc0 +#define CLK_CFG_8_SET 0xc4 +#define CLK_CFG_8_CLR 0xc8 +#define CLK_CFG_9 0xd0 +#define CLK_CFG_9_SET 0xd4 +#define CLK_CFG_9_CLR 0xd8 +#define CLK_CFG_10 0xe0 +#define CLK_CFG_10_SET 0xe4 +#define CLK_CFG_10_CLR 0xe8 +#define CLK_CFG_UPDATE 0x004 + +static const struct mtk_fixed_clk fixed_clks[] = { + FIXED_CLK(CLK_TOP_F_FRTC, "f_frtc_ck", "clk32k", 32768), + FIXED_CLK(CLK_TOP_CLK26M, "clk_26m_ck", "clk26m", 26000000), + FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 466000000), +}; + +static const struct mtk_fixed_factor top_divs[] = { + FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1), + FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2), + FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4), + FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8), + FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16), + FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3), + FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2), + FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4), + FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8), + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), + FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2), + FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4), + FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7), + FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2), + FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4), + FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2), + FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "univpll", 2, 13), + FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4), + FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8), + FACTOR(CLK_TOP_USB20_192M_D16, + "usb20_192m_d16", "usb20_192m_ck", 1, 16), + FACTOR(CLK_TOP_USB20_192M_D32, + "usb20_192m_d32", "usb20_192m_ck", 1, 32), + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2), + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4), + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2), + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4), + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8), + FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32), + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), + FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2), + FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4), + FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), + FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, 2), + FACTOR(CLK_TOP_MPLL, "mpll_ck", "mpll", 1, 1), + FACTOR(CLK_TOP_DA_MPLL_104M_DIV, "mpll_104m_div", "mpll_ck", 1, 2), + FACTOR(CLK_TOP_DA_MPLL_52M_DIV, "mpll_52m_div", "mpll_ck", 1, 4), + FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1), + FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2), + FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), + FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2), + FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4), + FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8), + FACTOR(CLK_TOP_ULPOSC1, "ulposc1_ck", "ulposc1", 1, 1), + FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1_ck", 1, 2), + FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1_ck", 1, 4), + FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1_ck", 1, 8), + FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1_ck", 1, 16), + FACTOR(CLK_TOP_ULPOSC1_D32, "ulposc1_d32", "ulposc1_ck", 1, 32), + FACTOR(CLK_TOP_F_F26M, "f_f26m_ck", "clk_26m_ck", 1, 1), + FACTOR(CLK_TOP_AXI, "axi_ck", "axi_sel", 1, 1), + FACTOR(CLK_TOP_MM, "mm_ck", "mm_sel", 1, 1), + FACTOR(CLK_TOP_SCP, "scp_ck", "scp_sel", 1, 1), + FACTOR(CLK_TOP_MFG, "mfg_ck", "mfg_sel", 1, 1), + FACTOR(CLK_TOP_F_FUART, "f_fuart_ck", "uart_sel", 1, 1), + FACTOR(CLK_TOP_SPI, "spi_ck", "spi_sel", 1, 1), + FACTOR(CLK_TOP_MSDC50_0, "msdc50_0_ck", "msdc50_0_sel", 1, 1), + FACTOR(CLK_TOP_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 1, 1), + FACTOR(CLK_TOP_AUDIO, "audio_ck", "audio_sel", 1, 1), + FACTOR(CLK_TOP_AUD_1, "aud_1_ck", "aud_1_sel", 1, 1), + FACTOR(CLK_TOP_AUD_ENGEN1, "aud_engen1_ck", "aud_engen1_sel", 1, 1), + FACTOR(CLK_TOP_F_FDISP_PWM, "f_fdisp_pwm_ck", "disp_pwm_sel", 1, 1), + FACTOR(CLK_TOP_SSPM, "sspm_ck", "sspm_sel", 1, 1), + FACTOR(CLK_TOP_DXCC, "dxcc_ck", "dxcc_sel", 1, 1), + FACTOR(CLK_TOP_I2C, "i2c_ck", "i2c_sel", 1, 1), + FACTOR(CLK_TOP_F_FPWM, "f_fpwm_ck", "pwm_sel", 1, 1), + FACTOR(CLK_TOP_F_FSENINF, "f_fseninf_ck", "seninf_sel", 1, 1), + FACTOR(CLK_TOP_AES_FDE, "aes_fde_ck", "aes_fde_sel", 1, 1), + FACTOR(CLK_TOP_F_BIST2FPC, "f_bist2fpc_ck", "univpll2_d2", 1, 1), + FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL0, "arm_div_pll0", "syspll_d2", 1, 1), + FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL1, "arm_div_pll1", "syspll_ck", 1, 1), + FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL2, "arm_div_pll2", "univpll_d2", 1, 1), + FACTOR(CLK_TOP_DA_USB20_48M_DIV, + "usb20_48m_div", "usb20_192m_d4", 1, 1), + FACTOR(CLK_TOP_DA_UNIV_48M_DIV, "univ_48m_div", "usb20_192m_d4", 1, 1), +}; + +static const char * const axi_parents[] = { + "clk26m", + "syspll_d7", + "syspll1_d4", + "syspll3_d2" +}; + +static const char * const mem_parents[] = { + "clk26m", + "dmpll_ck", + "apll1_ck" +}; + +static const char * const mm_parents[] = { + "clk26m", + "mmpll_ck", + "syspll1_d2", + "syspll_d5", + "syspll1_d4", + "univpll_d5", + "univpll1_d2", + "mmpll_d2" +}; + +static const char * const scp_parents[] = { + "clk26m", + "syspll4_d2", + "univpll2_d2", + "syspll1_d2", + "univpll1_d2", + "syspll_d3", + "univpll_d3" +}; + +static const char * const mfg_parents[] = { + "clk26m", + "mfgpll_ck", + "syspll_d3", + "univpll_d3" +}; + +static const char * const atb_parents[] = { + "clk26m", + "syspll1_d4", + "syspll1_d2" +}; + +static const char * const camtg_parents[] = { + "clk26m", + "usb20_192m_d8", + "univpll2_d8", + "usb20_192m_d4", + "univpll2_d32", + "usb20_192m_d16", + "usb20_192m_d32" +}; + +static const char * const uart_parents[] = { + "clk26m", + "univpll2_d8" +}; + +static const char * const spi_parents[] = { + "clk26m", + "syspll3_d2", + "syspll4_d2", + "syspll2_d4" +}; + +static const char * const msdc5hclk_parents[] = { + "clk26m", + "syspll1_d2", + "univpll1_d4", + "syspll2_d2" +}; + +static const char * const msdc50_0_parents[] = { + "clk26m", + "msdcpll_ck", + "syspll2_d2", + "syspll4_d2", + "univpll1_d2", + "syspll1_d2", + "univpll_d5", + "univpll1_d4" +}; + +static const char * const msdc30_1_parents[] = { + "clk26m", + "msdcpll_d2", + "univpll2_d2", + "syspll2_d2", + "syspll1_d4", + "univpll1_d4", + "usb20_192m_d4", + "syspll2_d4" +}; + +static const char * const audio_parents[] = { + "clk26m", + "syspll3_d4", + "syspll4_d4", + "syspll1_d16" +}; + +static const char * const aud_intbus_parents[] = { + "clk26m", + "syspll1_d4", + "syspll4_d2" +}; + +static const char * const aud_1_parents[] = { + "clk26m", + "apll1_ck" +}; + +static const char * const aud_engen1_parents[] = { + "clk26m", + "apll1_d2", + "apll1_d4", + "apll1_d8" +}; + +static const char * const disp_pwm_parents[] = { + "clk26m", + "univpll2_d4", + "ulposc1_d2", + "ulposc1_d8" +}; + +static const char * const sspm_parents[] = { + "clk26m", + "syspll1_d2", + "syspll_d3" +}; + +static const char * const dxcc_parents[] = { + "clk26m", + "syspll1_d2", + "syspll1_d4", + "syspll1_d8" +}; + +static const char * const usb_top_parents[] = { + "clk26m", + "univpll3_d4" +}; + +static const char * const spm_parents[] = { + "clk26m", + "syspll1_d8" +}; + +static const char * const i2c_parents[] = { + "clk26m", + "univpll3_d4", + "univpll3_d2", + "syspll1_d8", + "syspll2_d8" +}; + +static const char * const pwm_parents[] = { + "clk26m", + "univpll3_d4", + "syspll1_d8" +}; + +static const char * const seninf_parents[] = { + "clk26m", + "univpll1_d4", + "univpll1_d2", + "univpll2_d2" +}; + +static const char * const aes_fde_parents[] = { + "clk26m", + "msdcpll_ck", + "univpll_d3", + "univpll2_d2", + "univpll1_d2", + "syspll1_d2" +}; + +static const char * const ulposc_parents[] = { + "clk26m", + "ulposc1_d4", + "ulposc1_d8", + "ulposc1_d16", + "ulposc1_d32" +}; + +static const char * const camtm_parents[] = { + "clk26m", + "univpll1_d4", + "univpll1_d2", + "univpll2_d2" +}; + +#define INVALID_UPDATE_REG 0xFFFFFFFF +#define INVALID_UPDATE_SHIFT -1 +#define INVALID_MUX_GATE -1 + +static const struct mtk_mux top_muxes[] = { + /* CLK_CFG_0 */ + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, + CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, + 0, 2, 7, CLK_CFG_UPDATE, 0, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, + CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, + 8, 2, 15, CLK_CFG_UPDATE, 1, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0, + CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23, + CLK_CFG_UPDATE, 2), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0, + CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31, + CLK_CFG_UPDATE, 3), + /* CLK_CFG_1 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, CLK_CFG_1, + CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7, + CLK_CFG_UPDATE, 4), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, CLK_CFG_1, + CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 2, 15, + CLK_CFG_UPDATE, 5), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", + camtg_parents, CLK_CFG_1, CLK_CFG_1_SET, + CLK_CFG_1_CLR, 16, 3, 23, CLK_CFG_UPDATE, 6), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents, + CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR, + 24, 3, 31, CLK_CFG_UPDATE, 7), + /* CLK_CFG_2 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel", + camtg_parents, CLK_CFG_2, CLK_CFG_2_SET, + CLK_CFG_2_CLR, 0, 3, 7, CLK_CFG_UPDATE, 8), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", camtg_parents, + CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, + 8, 3, 15, CLK_CFG_UPDATE, 9), + MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, + CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 16, 1, 23, + CLK_CFG_UPDATE, 10), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, CLK_CFG_2, + CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 2, 31, + CLK_CFG_UPDATE, 11), + /* CLK_CFG_3 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk", + msdc5hclk_parents, CLK_CFG_3, CLK_CFG_3_SET, + CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", + msdc50_0_parents, CLK_CFG_3, CLK_CFG_3_SET, + CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", + msdc30_1_parents, CLK_CFG_3, CLK_CFG_3_SET, + CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, + CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR, + 24, 2, 31, CLK_CFG_UPDATE, 15), + /* CLK_CFG_4 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", + aud_intbus_parents, CLK_CFG_4, CLK_CFG_4_SET, + CLK_CFG_4_CLR, 0, 2, 7, CLK_CFG_UPDATE, 16), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, + CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR, + 8, 1, 15, CLK_CFG_UPDATE, 17), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", + aud_engen1_parents, CLK_CFG_4, CLK_CFG_4_SET, + CLK_CFG_4_CLR, 16, 2, 23, CLK_CFG_UPDATE, 18), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel", + disp_pwm_parents, CLK_CFG_4, CLK_CFG_4_SET, + CLK_CFG_4_CLR, 24, 2, 31, CLK_CFG_UPDATE, 19), + /* CLK_CFG_5 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM_SEL, "sspm_sel", sspm_parents, + CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 0, 2, 7, + CLK_CFG_UPDATE, 20), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents, + CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 8, 2, 15, + CLK_CFG_UPDATE, 21), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel", + usb_top_parents, CLK_CFG_5, CLK_CFG_5_SET, + CLK_CFG_5_CLR, 16, 1, 23, CLK_CFG_UPDATE, 22), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPM_SEL, "spm_sel", spm_parents, CLK_CFG_5, + CLK_CFG_5_SET, CLK_CFG_5_CLR, 24, 1, 31, + CLK_CFG_UPDATE, 23), + /* CLK_CFG_6 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, CLK_CFG_6, + CLK_CFG_6_SET, CLK_CFG_6_CLR, 0, 3, 7, CLK_CFG_UPDATE, + 24), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, CLK_CFG_6, + CLK_CFG_6_SET, CLK_CFG_6_CLR, 8, 2, 15, CLK_CFG_UPDATE, + 25), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", seninf_parents, + CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 16, 2, 23, + CLK_CFG_UPDATE, 26), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel", + aes_fde_parents, CLK_CFG_6, CLK_CFG_6_SET, + CLK_CFG_6_CLR, 24, 3, 31, CLK_CFG_UPDATE, 27), + /* CLK_CFG_7 */ + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRAP_ULPOSC_SEL, "ulposc_sel", + ulposc_parents, CLK_CFG_7, CLK_CFG_7_SET, + CLK_CFG_7_CLR, 0, 3, 7, CLK_CFG_UPDATE, 28, + CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", camtm_parents, + CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 8, 2, 15, + CLK_CFG_UPDATE, 29), +}; + +static const struct mtk_gate_regs top0_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x0, + .sta_ofs = 0x0, +}; + +static const struct mtk_gate_regs top1_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x104, + .sta_ofs = 0x104, +}; + +static const struct mtk_gate_regs top2_cg_regs = { + .set_ofs = 0x320, + .clr_ofs = 0x320, + .sta_ofs = 0x320, +}; + +#define GATE_TOP0(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &top0_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr, \ + } + +#define GATE_TOP1(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &top1_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +#define GATE_TOP2(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &top2_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr, \ + } + +static const struct mtk_gate top_clks[] = { + /* TOP0 */ + GATE_TOP0(CLK_TOP_MD_32K, "md_32k", "f_frtc_ck", 8), + GATE_TOP0(CLK_TOP_MD_26M, "md_26m", "f_f26m_ck", 9), + GATE_TOP0(CLK_TOP_MD2_32K, "md2_32k", "f_frtc_ck", 10), + GATE_TOP0(CLK_TOP_MD2_26M, "md2_26m", "f_f26m_ck", 11), + /* TOP1 */ + GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL0_EN, + "arm_div_pll0_en", "arm_div_pll0", 3), + GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL1_EN, + "arm_div_pll1_en", "arm_div_pll1", 4), + GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL2_EN, + "arm_div_pll2_en", "arm_div_pll2", 5), + GATE_TOP1(CLK_TOP_FMEM_OCC_DRC_EN, "drc_en", "univpll2_d2", 6), + GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_48m_div", 8), + GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "univ_48m_div", 9), + GATE_TOP1(CLK_TOP_F_UFS_MP_SAP_CFG_EN, "ufs_sap", "f_f26m_ck", 12), + GATE_TOP1(CLK_TOP_F_BIST2FPC_EN, "bist2fpc", "f_bist2fpc_ck", 16), + /* TOP2 */ + GATE_TOP2(CLK_TOP_APLL12_DIV0, "apll12_div0", "aud_1_ck", 2), + GATE_TOP2(CLK_TOP_APLL12_DIV1, "apll12_div1", "aud_1_ck", 3), + GATE_TOP2(CLK_TOP_APLL12_DIV2, "apll12_div2", "aud_1_ck", 4), + GATE_TOP2(CLK_TOP_APLL12_DIV3, "apll12_div3", "aud_1_ck", 5), +}; + +static const struct mtk_gate_regs ifr0_cg_regs = { + .set_ofs = 0x200, + .clr_ofs = 0x200, + .sta_ofs = 0x200, +}; + +static const struct mtk_gate_regs ifr1_cg_regs = { + .set_ofs = 0x74, + .clr_ofs = 0x74, + .sta_ofs = 0x74, +}; + +static const struct mtk_gate_regs ifr2_cg_regs = { + .set_ofs = 0x80, + .clr_ofs = 0x84, + .sta_ofs = 0x90, +}; + +static const struct mtk_gate_regs ifr3_cg_regs = { + .set_ofs = 0x88, + .clr_ofs = 0x8c, + .sta_ofs = 0x94, +}; + +static const struct mtk_gate_regs ifr4_cg_regs = { + .set_ofs = 0xa4, + .clr_ofs = 0xa8, + .sta_ofs = 0xac, +}; + +static const struct mtk_gate_regs ifr5_cg_regs = { + .set_ofs = 0xc0, + .clr_ofs = 0xc4, + .sta_ofs = 0xc8, +}; + +#define GATE_IFR0(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &ifr0_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +#define GATE_IFR1(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &ifr1_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr, \ + } + +#define GATE_IFR2(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &ifr2_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +#define GATE_IFR3(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &ifr3_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +#define GATE_IFR4(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &ifr4_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +#define GATE_IFR5(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &ifr5_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, \ + } + +static const struct mtk_gate ifr_clks[] = { + /* INFRA_TOPAXI */ + /* INFRA PERI */ + /* INFRA mode 0 */ + GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_ck", 8), + GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_ck", 9), + GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_ck", 10), + GATE_IFR2(CLK_IFR_I2C_AP, "ifr_i2c_ap", "i2c_ck", 11), + GATE_IFR2(CLK_IFR_I2C_CCU, "ifr_i2c_ccu", "i2c_ck", 12), + GATE_IFR2(CLK_IFR_I2C_SSPM, "ifr_i2c_sspm", "i2c_ck", 13), + GATE_IFR2(CLK_IFR_I2C_RSV, "ifr_i2c_rsv", "i2c_ck", 14), + GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_ck", 15), + GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "f_fpwm_ck", 16), + GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "f_fpwm_ck", 17), + GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "f_fpwm_ck", 18), + GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "f_fpwm_ck", 19), + GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "f_fpwm_ck", 20), + GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "f_fpwm_ck", 21), + GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "f_fuart_ck", 22), + GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "f_fuart_ck", 23), + GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "f_f26m_ck", 27), + GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_dma", "axi_ck", 28), + GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_ck", 31), + /* INFRA mode 1 */ + GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_ck", 1), + GATE_IFR3(CLK_IFR_MSDC0, "ifr_msdc0", "msdc5hclk", 2), + GATE_IFR3(CLK_IFR_MSDC1, "ifr_msdc1", "axi_ck", 4), + GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_ck", 9), + GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "f_f26m_ck", 10), + GATE_IFR3(CLK_IFR_CCIF1_AP, "ifr_ccif1_ap", "axi_ck", 12), + GATE_IFR3(CLK_IFR_CCIF1_MD, "ifr_ccif1_md", "axi_ck", 13), + GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "f_f26m_ck", 14), + GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_ck", 18), + GATE_IFR3(CLK_IFR_DEVICE_APC, "ifr_dapc", "axi_ck", 20), + GATE_IFR3(CLK_IFR_CCIF_AP, "ifr_ccif_ap", "axi_ck", 23), + GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_ck", 25), + GATE_IFR3(CLK_IFR_CCIF_MD, "ifr_ccif_md", "axi_ck", 26), + /* INFRA mode 2 */ + GATE_IFR4(CLK_IFR_RG_PWM_FBCLK6, "ifr_pwmfb", "f_f26m_ck", 0), + GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "f_fdisp_pwm_ck", 2), + GATE_IFR4(CLK_IFR_CLDMA_BCLK, "ifr_cldmabclk", "axi_ck", 3), + GATE_IFR4(CLK_IFR_AUDIO_26M_BCLK, "ifr_audio26m", "f_f26m_ck", 4), + GATE_IFR4(CLK_IFR_SPI1, "ifr_spi1", "spi_ck", 6), + GATE_IFR4(CLK_IFR_I2C4, "ifr_i2c4", "i2c_ck", 7), + GATE_IFR4(CLK_IFR_SPI2, "ifr_spi2", "spi_ck", 9), + GATE_IFR4(CLK_IFR_SPI3, "ifr_spi3", "spi_ck", 10), + GATE_IFR4(CLK_IFR_I2C5, "ifr_i2c5", "i2c_ck", 18), + GATE_IFR4(CLK_IFR_I2C5_ARBITER, "ifr_i2c5a", "i2c_ck", 19), + GATE_IFR4(CLK_IFR_I2C5_IMM, "ifr_i2c5_imm", "i2c_ck", 20), + GATE_IFR4(CLK_IFR_I2C1_ARBITER, "ifr_i2c1a", "i2c_ck", 21), + GATE_IFR4(CLK_IFR_I2C1_IMM, "ifr_i2c1_imm", "i2c_ck", 22), + GATE_IFR4(CLK_IFR_I2C2_ARBITER, "ifr_i2c2a", "i2c_ck", 23), + GATE_IFR4(CLK_IFR_I2C2_IMM, "ifr_i2c2_imm", "i2c_ck", 24), + GATE_IFR4(CLK_IFR_SPI4, "ifr_spi4", "spi_ck", 25), + GATE_IFR4(CLK_IFR_SPI5, "ifr_spi5", "spi_ck", 26), + GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_ck", 27), + GATE_IFR4(CLK_IFR_FAES_FDE, "ifr_faes_fde_ck", "aes_fde_ck", 29), + /* INFRA mode 3 */ + GATE_IFR5(CLK_IFR_MSDC0_SELF, "ifr_msdc0sf", "msdc50_0_ck", 0), + GATE_IFR5(CLK_IFR_MSDC1_SELF, "ifr_msdc1sf", "msdc50_0_ck", 1), + GATE_IFR5(CLK_IFR_I2C6, "ifr_i2c6", "i2c_ck", 6), + GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_ck", 7), + GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_ck", 8), + GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_clk", "msdc50_0_ck", 9), + GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_clk", "msdc30_1_ck", 10), + GATE_IFR5(CLK_IFR_MCU_PM_BCLK, "ifr_mcu_pm_bclk", "axi_ck", 17), + GATE_IFR5(CLK_IFR_CCIF2_AP, "ifr_ccif2_ap", "axi_ck", 18), + GATE_IFR5(CLK_IFR_CCIF2_MD, "ifr_ccif2_md", "axi_ck", 19), + GATE_IFR5(CLK_IFR_CCIF3_AP, "ifr_ccif3_ap", "axi_ck", 20), + GATE_IFR5(CLK_IFR_CCIF3_MD, "ifr_ccif3_md", "axi_ck", 21), +}; + +/* additional CCF control for mipi26M race condition(disp/camera) */ +static const struct mtk_gate_regs apmixed_cg_regs = { + .set_ofs = 0x14, + .clr_ofs = 0x14, + .sta_ofs = 0x14, +}; + +#define GATE_APMIXED(_id, _name, _parent, _shift) { \ + .id = _id, \ + .name = _name, \ + .parent_name = _parent, \ + .regs = &apmixed_cg_regs, \ + .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate apmixed_clks[] = { + /* AUDIO0 */ + GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m", "f_f26m_ck", + 4), + GATE_APMIXED(CLK_APMIXED_APPLL26M, "apmixed_appll26m", "f_f26m_ck", + 5), + GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", "f_f26m_ck", + 6), + GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m", "f_f26m_ck", + 7), + GATE_APMIXED(CLK_APMIXED_MMSYS_F26M, "apmixed_mmsys26m", "f_f26m_ck", + 8), + GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m", "f_f26m_ck", + 9), + GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", "f_f26m_ck", + 11), + GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m", "f_f26m_ck", + 13), + GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m", + "f_f26m_ck", 14), + GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", "f_f26m_ck", + 16), +}; + +#define MT6765_PLL_FMAX (3800UL * MHZ) +#define MT6765_PLL_FMIN (1500UL * MHZ) + +#define CON0_MT6765_RST_BAR BIT(23) + +#define PLL_INFO_NULL (0xFF) + +#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pcwibits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,\ + _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table) {\ + .id = _id, \ + .name = _name, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .flags = _flags, \ + .rst_bar_mask = CON0_MT6765_RST_BAR, \ + .fmax = MT6765_PLL_FMAX, \ + .fmin = MT6765_PLL_FMIN, \ + .pcwbits = _pcwbits, \ + .pcwibits = _pcwibits, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .tuner_reg = _tuner_reg, \ + .tuner_en_reg = _tuner_en_reg, \ + .tuner_en_bit = _tuner_en_bit, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + .div_table = _div_table, \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pcwibits, _pd_reg, _pd_shift, _tuner_reg, \ + _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ + _pcw_shift) \ + PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ + _pcwbits, _pcwibits, _pd_reg, _pd_shift, \ + _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ + _pcw_reg, _pcw_shift, NULL) \ + +static const struct mtk_pll_data plls[] = { + PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, BIT(0), + PLL_AO, 22, 8, 0x0220, 24, 0, 0, 0, 0x0220, 0), + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, BIT(0), + PLL_AO, 22, 8, 0x0210, 24, 0, 0, 0, 0x0210, 0), + PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, BIT(0), + PLL_AO, 22, 8, 0x0230, 24, 0, 0, 0, 0x0230, 0), + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, BIT(0), + (HAVE_RST_BAR | PLL_AO), 22, 8, 0x0240, 24, 0, 0, 0, 0x0240, + 0), + PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, BIT(0), + 0, 22, 8, 0x0250, 24, 0, 0, 0, 0x0250, 0), + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, BIT(0), + 0, 22, 8, 0x0260, 24, 0, 0, 0, 0x0260, 0), + PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, BIT(0), + HAVE_RST_BAR, 22, 8, 0x0270, 24, 0, 0, 0, 0x0270, 0), + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, BIT(0), + 0, 22, 8, 0x0280, 24, 0, 0, 0, 0x0280, 0), + PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, BIT(0), + 0, 32, 8, 0x0290, 24, 0x0040, 0x000C, 0, 0x0294, 0), + PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, BIT(0), + PLL_AO, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0), +}; + +static int clk_mt6765_apmixed_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + int r; + struct device_node *node = pdev->dev.of_node; + void __iomem *base; + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) { + pr_err("%s(): ioremap failed\n", __func__); + return PTR_ERR(base); + } + + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); + + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + + mtk_clk_register_gates(node, apmixed_clks, + ARRAY_SIZE(apmixed_clks), clk_data); + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + + apmixed_base = base; + /* MPLL, CCIPLL, MAINPLL set HW mode, TDCLKSQ, CLKSQ1 */ + writel(readl(AP_PLL_CON3) & 0xFFFFFFE1, AP_PLL_CON3); + writel(readl(PLLON_CON0) & 0x01041041, PLLON_CON0); + writel(readl(PLLON_CON1) & 0x01041041, PLLON_CON1); + + return r; +} + +static int clk_mt6765_top_probe(struct platform_device *pdev) +{ + int r; + struct device_node *node = pdev->dev.of_node; + void __iomem *base; + struct clk_onecell_data *clk_data; + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) { + pr_err("%s(): ioremap failed\n", __func__); + return PTR_ERR(base); + } + + clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); + + mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), + clk_data); + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), + clk_data); + mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, + &mt6765_clk_lock, clk_data); + mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + + cksys_base = base; + /* [4]:no need */ + writel(readl(CLK_SCP_CFG_0) | 0x3EF, CLK_SCP_CFG_0); + /*[1,2,3,8]: no need*/ + writel(readl(CLK_SCP_CFG_1) | 0x1, CLK_SCP_CFG_1); + + return r; +} + +static int clk_mt6765_ifr_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + int r; + struct device_node *node = pdev->dev.of_node; + void __iomem *base; + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) { + pr_err("%s(): ioremap failed\n", __func__); + return PTR_ERR(base); + } + + clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK); + + mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks), + clk_data); + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + + return r; +} + +static const struct of_device_id of_match_clk_mt6765[] = { + { + .compatible = "mediatek,mt6765-apmixedsys", + .data = clk_mt6765_apmixed_probe, + }, { + .compatible = "mediatek,mt6765-topckgen", + .data = clk_mt6765_top_probe, + }, { + .compatible = "mediatek,mt6765-infracfg", + .data = clk_mt6765_ifr_probe, + }, { + /* sentinel */ + } +}; + +static int clk_mt6765_probe(struct platform_device *pdev) +{ + int (*clk_probe)(struct platform_device *d); + int r; + + clk_probe = of_device_get_match_data(&pdev->dev); + if (!clk_probe) + return -EINVAL; + + r = clk_probe(pdev); + if (r) + dev_err(&pdev->dev, + "could not register clock provider: %s: %d\n", + pdev->name, r); + + return r; +} + +static struct platform_driver clk_mt6765_drv = { + .probe = clk_mt6765_probe, + .driver = { + .name = "clk-mt6765", + .owner = THIS_MODULE, + .of_match_table = of_match_clk_mt6765, + }, +}; + +static int __init clk_mt6765_init(void) +{ + return platform_driver_register(&clk_mt6765_drv); +} + +arch_initcall(clk_mt6765_init); -- 2.18.0 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v6 5/8] clk: mediatek: Add MT6765 clock support 2019-07-12 9:43 ` [PATCH v6 5/8] clk: mediatek: Add MT6765 clock support Macpaul Lin @ 2019-08-15 0:27 ` Stephen Boyd 2019-08-15 13:44 ` Greg KH 2019-12-02 8:55 ` Owen Chen 0 siblings, 2 replies; 18+ messages in thread From: Stephen Boyd @ 2019-08-15 0:27 UTC (permalink / raw) To: Marc Zyngier, Mars Cheng, Matthias Brugger, Owen Chen, Rob Herring, Ryder Lee, Sean Wang, linux-arm-kernel, linux-kernel, linux-mediatek Cc: wsd_upstream, CC Hwang, Loda Chou, devicetree, linux-serial, linux-clk, Macpaul Lin Quoting Macpaul Lin (2019-07-12 02:43:41) > diff --git a/drivers/clk/mediatek/clk-mt6765-audio.c b/drivers/clk/mediatek/clk-mt6765-audio.c > new file mode 100644 > index 000000000000..41f19343dfb9 > --- /dev/null > +++ b/drivers/clk/mediatek/clk-mt6765-audio.c > @@ -0,0 +1,109 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Owen Chen <owen.chen@mediatek.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. Please use SPDX tags. > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/platform_device.h> > + > +#include "clk-mtk.h" > +#include "clk-gate.h" > + > diff --git a/drivers/clk/mediatek/clk-mt6765-vcodec.c b/drivers/clk/mediatek/clk-mt6765-vcodec.c > new file mode 100644 > index 000000000000..eb9ae1c2c99c > --- /dev/null > +++ b/drivers/clk/mediatek/clk-mt6765-vcodec.c > @@ -0,0 +1,79 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Owen Chen <owen.chen@mediatek.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ SPDX tags. > diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c > new file mode 100644 > index 000000000000..f716a48a926d > --- /dev/null > +++ b/drivers/clk/mediatek/clk-mt6765.c > @@ -0,0 +1,961 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Owen Chen <owen.chen@mediatek.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. SPDX tags. > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/slab.h> > +#include <linux/mfd/syscon.h> Is this used? Maybe I deleted it. > +#include <linux/of_device.h> > +#include <linux/platform_device.h> [...] > + > +static const char * const axi_parents[] = { > + "clk26m", > + "syspll_d7", > + "syspll1_d4", > + "syspll3_d2" > +}; > + > +static const char * const mem_parents[] = { > + "clk26m", > + "dmpll_ck", > + "apll1_ck" > +}; > + > +static const char * const mm_parents[] = { > + "clk26m", > + "mmpll_ck", > + "syspll1_d2", > + "syspll_d5", > + "syspll1_d4", > + "univpll_d5", > + "univpll1_d2", > + "mmpll_d2" > +}; > + > +static const char * const scp_parents[] = { > + "clk26m", > + "syspll4_d2", > + "univpll2_d2", > + "syspll1_d2", > + "univpll1_d2", > + "syspll_d3", > + "univpll_d3" > +}; > + > +static const char * const mfg_parents[] = { > + "clk26m", > + "mfgpll_ck", > + "syspll_d3", > + "univpll_d3" > +}; > + > +static const char * const atb_parents[] = { > + "clk26m", > + "syspll1_d4", > + "syspll1_d2" > +}; > + > +static const char * const camtg_parents[] = { > + "clk26m", > + "usb20_192m_d8", > + "univpll2_d8", > + "usb20_192m_d4", > + "univpll2_d32", > + "usb20_192m_d16", > + "usb20_192m_d32" > +}; > + > +static const char * const uart_parents[] = { > + "clk26m", > + "univpll2_d8" > +}; > + > +static const char * const spi_parents[] = { > + "clk26m", > + "syspll3_d2", > + "syspll4_d2", > + "syspll2_d4" > +}; > + > +static const char * const msdc5hclk_parents[] = { > + "clk26m", > + "syspll1_d2", > + "univpll1_d4", > + "syspll2_d2" > +}; > + > +static const char * const msdc50_0_parents[] = { > + "clk26m", > + "msdcpll_ck", > + "syspll2_d2", > + "syspll4_d2", > + "univpll1_d2", > + "syspll1_d2", > + "univpll_d5", > + "univpll1_d4" > +}; > + > +static const char * const msdc30_1_parents[] = { > + "clk26m", > + "msdcpll_d2", > + "univpll2_d2", > + "syspll2_d2", > + "syspll1_d4", > + "univpll1_d4", > + "usb20_192m_d4", > + "syspll2_d4" > +}; > + > +static const char * const audio_parents[] = { > + "clk26m", > + "syspll3_d4", > + "syspll4_d4", > + "syspll1_d16" > +}; > + > +static const char * const aud_intbus_parents[] = { > + "clk26m", > + "syspll1_d4", > + "syspll4_d2" > +}; > + > +static const char * const aud_1_parents[] = { > + "clk26m", > + "apll1_ck" > +}; > + > +static const char * const aud_engen1_parents[] = { > + "clk26m", > + "apll1_d2", > + "apll1_d4", > + "apll1_d8" > +}; > + > +static const char * const disp_pwm_parents[] = { > + "clk26m", > + "univpll2_d4", > + "ulposc1_d2", > + "ulposc1_d8" > +}; > + > +static const char * const sspm_parents[] = { > + "clk26m", > + "syspll1_d2", > + "syspll_d3" > +}; > + > +static const char * const dxcc_parents[] = { > + "clk26m", > + "syspll1_d2", > + "syspll1_d4", > + "syspll1_d8" > +}; > + > +static const char * const usb_top_parents[] = { > + "clk26m", > + "univpll3_d4" > +}; > + > +static const char * const spm_parents[] = { > + "clk26m", > + "syspll1_d8" > +}; > + > +static const char * const i2c_parents[] = { > + "clk26m", > + "univpll3_d4", > + "univpll3_d2", > + "syspll1_d8", > + "syspll2_d8" > +}; > + > +static const char * const pwm_parents[] = { > + "clk26m", > + "univpll3_d4", > + "syspll1_d8" > +}; > + > +static const char * const seninf_parents[] = { > + "clk26m", > + "univpll1_d4", > + "univpll1_d2", > + "univpll2_d2" > +}; > + > +static const char * const aes_fde_parents[] = { > + "clk26m", > + "msdcpll_ck", > + "univpll_d3", > + "univpll2_d2", > + "univpll1_d2", > + "syspll1_d2" > +}; > + > +static const char * const ulposc_parents[] = { > + "clk26m", > + "ulposc1_d4", > + "ulposc1_d8", > + "ulposc1_d16", > + "ulposc1_d32" > +}; > + > +static const char * const camtm_parents[] = { > + "clk26m", > + "univpll1_d4", > + "univpll1_d2", > + "univpll2_d2" > +}; > + Can you migrate this driver to the new way of specifying clk parents? That way we don't just have lists of strings. > +#define INVALID_UPDATE_REG 0xFFFFFFFF > +#define INVALID_UPDATE_SHIFT -1 > +#define INVALID_MUX_GATE -1 > + > +static const struct mtk_mux top_muxes[] = { > + /* CLK_CFG_0 */ > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, > + CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, > + 0, 2, 7, CLK_CFG_UPDATE, 0, CLK_IS_CRITICAL), Please add a comment why CLK_IS_CRITICAL flag is used in each place. > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, > + CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, > + 8, 2, 15, CLK_CFG_UPDATE, 1, CLK_IS_CRITICAL), > + MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0, > + CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23, > + CLK_CFG_UPDATE, 2), > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0, > + CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31, > + CLK_CFG_UPDATE, 3), [...] > + }, { > + .compatible = "mediatek,mt6765-topckgen", > + .data = clk_mt6765_top_probe, > + }, { > + .compatible = "mediatek,mt6765-infracfg", > + .data = clk_mt6765_ifr_probe, > + }, { > + /* sentinel */ > + } > +}; > + > +static int clk_mt6765_probe(struct platform_device *pdev) > +{ > + int (*clk_probe)(struct platform_device *d); > + int r; > + > + clk_probe = of_device_get_match_data(&pdev->dev); > + if (!clk_probe) > + return -EINVAL; > + > + r = clk_probe(pdev); > + if (r) > + dev_err(&pdev->dev, > + "could not register clock provider: %s: %d\n", > + pdev->name, r); > + > + return r; > +} > + > +static struct platform_driver clk_mt6765_drv = { > + .probe = clk_mt6765_probe, > + .driver = { > + .name = "clk-mt6765", > + .owner = THIS_MODULE, Remove this line, platform_driver_register() should take care of it. > + .of_match_table = of_match_clk_mt6765, > + }, > +}; > + ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v6 5/8] clk: mediatek: Add MT6765 clock support 2019-08-15 0:27 ` Stephen Boyd @ 2019-08-15 13:44 ` Greg KH 2019-12-02 8:55 ` Owen Chen 1 sibling, 0 replies; 18+ messages in thread From: Greg KH @ 2019-08-15 13:44 UTC (permalink / raw) To: Stephen Boyd Cc: Macpaul Lin, Marc Zyngier, Mars Cheng, Matthias Brugger, Owen Chen, Rob Herring, Ryder Lee, Sean Wang, linux-arm-kernel, linux-kernel, linux-mediatek, wsd_upstream, CC Hwang, Loda Chou, devicetree, linux-serial, linux-clk On Wed, Aug 14, 2019 at 05:27:20PM -0700, Stephen Boyd wrote: > Quoting Macpaul Lin (2019-07-12 02:43:41) > > diff --git a/drivers/clk/mediatek/clk-mt6765-audio.c b/drivers/clk/mediatek/clk-mt6765-audio.c > > new file mode 100644 > > index 000000000000..41f19343dfb9 > > --- /dev/null > > +++ b/drivers/clk/mediatek/clk-mt6765-audio.c > > @@ -0,0 +1,109 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (c) 2018 MediaTek Inc. > > + * Author: Owen Chen <owen.chen@mediatek.com> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > Please use SPDX tags. To be specific, _only_ the SPDX tag. There is an SPDX tag on this file, and the others, it's just that the license text is no longer needed with that. thanks, greg k-h ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v6 5/8] clk: mediatek: Add MT6765 clock support 2019-08-15 0:27 ` Stephen Boyd 2019-08-15 13:44 ` Greg KH @ 2019-12-02 8:55 ` Owen Chen 1 sibling, 0 replies; 18+ messages in thread From: Owen Chen @ 2019-12-02 8:55 UTC (permalink / raw) To: Stephen Boyd Cc: devicetree, Ryder Lee (李庚諺), wsd_upstream, Marc Zyngier, Sean Wang, Loda Chou (周宏霖), linux-kernel, Rob Herring, Mars Cheng (鄭森友), Macpaul Lin (林智斌), linux-serial, Matthias Brugger, linux-mediatek, CC Hwang (黃致銓), linux-clk, linux-arm-kernel On Thu, 2019-08-15 at 08:27 +0800, Stephen Boyd wrote: > Quoting Macpaul Lin (2019-07-12 02:43:41) > > diff --git a/drivers/clk/mediatek/clk-mt6765-audio.c b/drivers/clk/mediatek/clk-mt6765-audio.c > > new file mode 100644 > > index 000000000000..41f19343dfb9 > > --- /dev/null > > +++ b/drivers/clk/mediatek/clk-mt6765-audio.c > > @@ -0,0 +1,109 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (c) 2018 MediaTek Inc. > > + * Author: Owen Chen <owen.chen@mediatek.com> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > Please use SPDX tags. > > > + */ > > + > > +#include <linux/clk-provider.h> > > +#include <linux/platform_device.h> > > + > > +#include "clk-mtk.h" > > +#include "clk-gate.h" > > + > > diff --git a/drivers/clk/mediatek/clk-mt6765-vcodec.c b/drivers/clk/mediatek/clk-mt6765-vcodec.c > > new file mode 100644 > > index 000000000000..eb9ae1c2c99c > > --- /dev/null > > +++ b/drivers/clk/mediatek/clk-mt6765-vcodec.c > > @@ -0,0 +1,79 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (c) 2018 MediaTek Inc. > > + * Author: Owen Chen <owen.chen@mediatek.com> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > SPDX tags. > > > diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c > > new file mode 100644 > > index 000000000000..f716a48a926d > > --- /dev/null > > +++ b/drivers/clk/mediatek/clk-mt6765.c > > @@ -0,0 +1,961 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (c) 2018 MediaTek Inc. > > + * Author: Owen Chen <owen.chen@mediatek.com> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > SPDX tags. > > > + */ > > + > > +#include <linux/clk-provider.h> > > +#include <linux/of.h> > > +#include <linux/of_address.h> > > +#include <linux/slab.h> > > +#include <linux/mfd/syscon.h> > > Is this used? Maybe I deleted it. > > > +#include <linux/of_device.h> > > +#include <linux/platform_device.h> > [...] > > + > > +static const char * const axi_parents[] = { > > + "clk26m", > > + "syspll_d7", > > + "syspll1_d4", > > + "syspll3_d2" > > +}; > > + > > +static const char * const mem_parents[] = { > > + "clk26m", > > + "dmpll_ck", > > + "apll1_ck" > > +}; > > + > > +static const char * const mm_parents[] = { > > + "clk26m", > > + "mmpll_ck", > > + "syspll1_d2", > > + "syspll_d5", > > + "syspll1_d4", > > + "univpll_d5", > > + "univpll1_d2", > > + "mmpll_d2" > > +}; > > + > > +static const char * const scp_parents[] = { > > + "clk26m", > > + "syspll4_d2", > > + "univpll2_d2", > > + "syspll1_d2", > > + "univpll1_d2", > > + "syspll_d3", > > + "univpll_d3" > > +}; > > + > > +static const char * const mfg_parents[] = { > > + "clk26m", > > + "mfgpll_ck", > > + "syspll_d3", > > + "univpll_d3" > > +}; > > + > > +static const char * const atb_parents[] = { > > + "clk26m", > > + "syspll1_d4", > > + "syspll1_d2" > > +}; > > + > > +static const char * const camtg_parents[] = { > > + "clk26m", > > + "usb20_192m_d8", > > + "univpll2_d8", > > + "usb20_192m_d4", > > + "univpll2_d32", > > + "usb20_192m_d16", > > + "usb20_192m_d32" > > +}; > > + > > +static const char * const uart_parents[] = { > > + "clk26m", > > + "univpll2_d8" > > +}; > > + > > +static const char * const spi_parents[] = { > > + "clk26m", > > + "syspll3_d2", > > + "syspll4_d2", > > + "syspll2_d4" > > +}; > > + > > +static const char * const msdc5hclk_parents[] = { > > + "clk26m", > > + "syspll1_d2", > > + "univpll1_d4", > > + "syspll2_d2" > > +}; > > + > > +static const char * const msdc50_0_parents[] = { > > + "clk26m", > > + "msdcpll_ck", > > + "syspll2_d2", > > + "syspll4_d2", > > + "univpll1_d2", > > + "syspll1_d2", > > + "univpll_d5", > > + "univpll1_d4" > > +}; > > + > > +static const char * const msdc30_1_parents[] = { > > + "clk26m", > > + "msdcpll_d2", > > + "univpll2_d2", > > + "syspll2_d2", > > + "syspll1_d4", > > + "univpll1_d4", > > + "usb20_192m_d4", > > + "syspll2_d4" > > +}; > > + > > +static const char * const audio_parents[] = { > > + "clk26m", > > + "syspll3_d4", > > + "syspll4_d4", > > + "syspll1_d16" > > +}; > > + > > +static const char * const aud_intbus_parents[] = { > > + "clk26m", > > + "syspll1_d4", > > + "syspll4_d2" > > +}; > > + > > +static const char * const aud_1_parents[] = { > > + "clk26m", > > + "apll1_ck" > > +}; > > + > > +static const char * const aud_engen1_parents[] = { > > + "clk26m", > > + "apll1_d2", > > + "apll1_d4", > > + "apll1_d8" > > +}; > > + > > +static const char * const disp_pwm_parents[] = { > > + "clk26m", > > + "univpll2_d4", > > + "ulposc1_d2", > > + "ulposc1_d8" > > +}; > > + > > +static const char * const sspm_parents[] = { > > + "clk26m", > > + "syspll1_d2", > > + "syspll_d3" > > +}; > > + > > +static const char * const dxcc_parents[] = { > > + "clk26m", > > + "syspll1_d2", > > + "syspll1_d4", > > + "syspll1_d8" > > +}; > > + > > +static const char * const usb_top_parents[] = { > > + "clk26m", > > + "univpll3_d4" > > +}; > > + > > +static const char * const spm_parents[] = { > > + "clk26m", > > + "syspll1_d8" > > +}; > > + > > +static const char * const i2c_parents[] = { > > + "clk26m", > > + "univpll3_d4", > > + "univpll3_d2", > > + "syspll1_d8", > > + "syspll2_d8" > > +}; > > + > > +static const char * const pwm_parents[] = { > > + "clk26m", > > + "univpll3_d4", > > + "syspll1_d8" > > +}; > > + > > +static const char * const seninf_parents[] = { > > + "clk26m", > > + "univpll1_d4", > > + "univpll1_d2", > > + "univpll2_d2" > > +}; > > + > > +static const char * const aes_fde_parents[] = { > > + "clk26m", > > + "msdcpll_ck", > > + "univpll_d3", > > + "univpll2_d2", > > + "univpll1_d2", > > + "syspll1_d2" > > +}; > > + > > +static const char * const ulposc_parents[] = { > > + "clk26m", > > + "ulposc1_d4", > > + "ulposc1_d8", > > + "ulposc1_d16", > > + "ulposc1_d32" > > +}; > > + > > +static const char * const camtm_parents[] = { > > + "clk26m", > > + "univpll1_d4", > > + "univpll1_d2", > > + "univpll2_d2" > > +}; > > + > > Can you migrate this driver to the new way of specifying clk parents? > That way we don't just have lists of strings. > Do you mean hide the string list information inside DTS file or clk header file? > > +#define INVALID_UPDATE_REG 0xFFFFFFFF > > +#define INVALID_UPDATE_SHIFT -1 > > +#define INVALID_MUX_GATE -1 > > + > > +static const struct mtk_mux top_muxes[] = { > > + /* CLK_CFG_0 */ > > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, > > + CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, > > + 0, 2, 7, CLK_CFG_UPDATE, 0, CLK_IS_CRITICAL), > > Please add a comment why CLK_IS_CRITICAL flag is used in each place. > > > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, > > + CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, > > + 8, 2, 15, CLK_CFG_UPDATE, 1, CLK_IS_CRITICAL), > > + MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0, > > + CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23, > > + CLK_CFG_UPDATE, 2), > > + MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0, > > + CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31, > > + CLK_CFG_UPDATE, 3), > [...] > > + }, { > > + .compatible = "mediatek,mt6765-topckgen", > > + .data = clk_mt6765_top_probe, > > + }, { > > + .compatible = "mediatek,mt6765-infracfg", > > + .data = clk_mt6765_ifr_probe, > > + }, { > > + /* sentinel */ > > + } > > +}; > > + > > +static int clk_mt6765_probe(struct platform_device *pdev) > > +{ > > + int (*clk_probe)(struct platform_device *d); > > + int r; > > + > > + clk_probe = of_device_get_match_data(&pdev->dev); > > + if (!clk_probe) > > + return -EINVAL; > > + > > + r = clk_probe(pdev); > > + if (r) > > + dev_err(&pdev->dev, > > + "could not register clock provider: %s: %d\n", > > + pdev->name, r); > > + > > + return r; > > +} > > + > > +static struct platform_driver clk_mt6765_drv = { > > + .probe = clk_mt6765_probe, > > + .driver = { > > + .name = "clk-mt6765", > > + .owner = THIS_MODULE, > > Remove this line, platform_driver_register() should take care of it. > > > + .of_match_table = of_match_clk_mt6765, > > + }, > > +}; > > + _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v6 6/8] soc: mediatek: add MT6765 scpsys and subdomain support 2019-07-12 9:43 [PATCH v6 0/8] Add basic SoC support for mt6765 Macpaul Lin ` (4 preceding siblings ...) 2019-07-12 9:43 ` [PATCH v6 5/8] clk: mediatek: Add MT6765 clock support Macpaul Lin @ 2019-07-12 9:43 ` Macpaul Lin 2019-12-14 23:40 ` Matthias Brugger 2019-07-12 9:43 ` [PATCH v6 7/8] arm64: dts: mediatek: add mt6765 support Macpaul Lin 2019-07-12 9:43 ` [PATCH v6 8/8] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks Macpaul Lin 7 siblings, 1 reply; 18+ messages in thread From: Macpaul Lin @ 2019-07-12 9:43 UTC (permalink / raw) To: Rob Herring, Marc Zyngier, Ryder Lee, Stephen Boyd, Sean Wang, Mars Cheng, Owen Chen, Matthias Brugger, linux-arm-kernel, linux-mediatek, linux-kernel Cc: wsd_upstream, CC Hwang, Loda Chou, devicetree, linux-serial, linux-clk, Macpaul Lin From: Mars Cheng <mars.cheng@mediatek.com> This adds scpsys support for MT6765 Add subdomain support for MT6765: isp, mm, connsys, mfg, and cam. Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Owen Chen <owen.chen@mediatek.com> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> --- drivers/soc/mediatek/mtk-scpsys.c | 130 ++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index ea5a221a16e9..ff124c514e9c 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -16,6 +16,7 @@ #include <dt-bindings/power/mt2701-power.h> #include <dt-bindings/power/mt2712-power.h> +#include <dt-bindings/power/mt6765-power.h> #include <dt-bindings/power/mt6797-power.h> #include <dt-bindings/power/mt7622-power.h> #include <dt-bindings/power/mt7623a-power.h> @@ -869,6 +870,120 @@ static const struct scp_subdomain scp_subdomain_mt2712[] = { {MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3}, }; +/* + * MT6765 power domain support + */ +#define SPM_PWR_STATUS_MT6765 0x0180 +#define SPM_PWR_STATUS_2ND_MT6765 0x0184 + +static const struct scp_domain_data scp_domain_data_mt6765[] = { + [MT6765_POWER_DOMAIN_VCODEC] = { + .name = "vcodec", + .sta_mask = BIT(26), + .ctl_offs = 0x300, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT6765_POWER_DOMAIN_ISP] = { + .name = "isp", + .sta_mask = BIT(5), + .ctl_offs = 0x308, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .subsys_clk_prefix = "isp", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, + BIT(20), BIT(20)), + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0, + BIT(2), BIT(2)), + }, + }, + [MT6765_POWER_DOMAIN_MM] = { + .name = "mm", + .sta_mask = BIT(3), + .ctl_offs = 0x30C, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_id = {"mm"}, + .subsys_clk_prefix = "mm", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, + BIT(16) | BIT(17), BIT(16) | BIT(17)), + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, + BIT(10) | BIT(11), BIT(10) | BIT(11)), + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, + BIT(1) | BIT(2), BIT(1) | BIT(2)), + }, + }, + [MT6765_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = BIT(1), + .ctl_offs = 0x32C, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, + BIT(13), BIT(13)), + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, + BIT(18), BIT(18)), + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, + BIT(14) | BIT(16), BIT(14) | BIT(16)), + }, + }, + [MT6765_POWER_DOMAIN_MFG_ASYNC] = { + .name = "mfg_async", + .sta_mask = BIT(23), + .ctl_offs = 0x334, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .basic_clk_id = {"mfg"}, + }, + [MT6765_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = BIT(4), + .ctl_offs = 0x338, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, + BIT(25), BIT(25)), + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, + BIT(21) | BIT(22), BIT(21) | BIT(22)), + } + }, + [MT6765_POWER_DOMAIN_CAM] = { + .name = "cam", + .sta_mask = BIT(25), + .ctl_offs = 0x344, + .sram_pdn_bits = GENMASK(8, 9), + .sram_pdn_ack_bits = GENMASK(12, 13), + .subsys_clk_prefix = "cam", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, + BIT(19) | BIT(21), BIT(19) | BIT(21)), + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, + BIT(20), BIT(20)), + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0, + BIT(3), BIT(3)), + } + }, + [MT6765_POWER_DOMAIN_MFG_CORE0] = { + .name = "mfg_core0", + .sta_mask = BIT(7), + .ctl_offs = 0x34C, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, +}; + +static const struct scp_subdomain scp_subdomain_mt6765[] = { + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_CAM}, + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_ISP}, + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_VCODEC}, + {MT6765_POWER_DOMAIN_MFG_ASYNC, MT6765_POWER_DOMAIN_MFG}, + {MT6765_POWER_DOMAIN_MFG, MT6765_POWER_DOMAIN_MFG_CORE0}, +}; + /* * MT6797 power domain support */ @@ -1363,6 +1478,18 @@ static const struct scp_soc_data mt2712_data = { .bus_prot_reg_update = false, }; +static const struct scp_soc_data mt6765_data = { + .domains = scp_domain_data_mt6765, + .num_domains = ARRAY_SIZE(scp_domain_data_mt6765), + .subdomains = scp_subdomain_mt6765, + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6765), + .regs = { + .pwr_sta_offs = SPM_PWR_STATUS_MT6765, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6765, + }, + .bus_prot_reg_update = true, +}; + static const struct scp_soc_data mt6797_data = { .domains = scp_domain_data_mt6797, .num_domains = ARRAY_SIZE(scp_domain_data_mt6797), @@ -1429,6 +1556,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = { }, { .compatible = "mediatek,mt2712-scpsys", .data = &mt2712_data, + }, { + .compatible = "mediatek,mt6765-scpsys", + .data = &mt6765_data, }, { .compatible = "mediatek,mt6797-scpsys", .data = &mt6797_data, -- 2.18.0 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v6 6/8] soc: mediatek: add MT6765 scpsys and subdomain support 2019-07-12 9:43 ` [PATCH v6 6/8] soc: mediatek: add MT6765 scpsys and subdomain support Macpaul Lin @ 2019-12-14 23:40 ` Matthias Brugger 2019-12-16 8:45 ` Matthias Brugger 0 siblings, 1 reply; 18+ messages in thread From: Matthias Brugger @ 2019-12-14 23:40 UTC (permalink / raw) To: Macpaul Lin, Rob Herring, Marc Zyngier, Ryder Lee, Stephen Boyd, Sean Wang, Mars Cheng, Owen Chen, linux-arm-kernel, linux-mediatek, linux-kernel Cc: devicetree, CC Hwang, wsd_upstream, Loda Chou, linux-serial, linux-clk On 12/07/2019 11:43, Macpaul Lin wrote: > From: Mars Cheng <mars.cheng@mediatek.com> > > This adds scpsys support for MT6765 > Add subdomain support for MT6765: > isp, mm, connsys, mfg, and cam. > > Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> > Signed-off-by: Owen Chen <owen.chen@mediatek.com> > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Applied to v5.5-next/soc > --- > drivers/soc/mediatek/mtk-scpsys.c | 130 ++++++++++++++++++++++++++++++ > 1 file changed, 130 insertions(+) > > diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c > index ea5a221a16e9..ff124c514e9c 100644 > --- a/drivers/soc/mediatek/mtk-scpsys.c > +++ b/drivers/soc/mediatek/mtk-scpsys.c > @@ -16,6 +16,7 @@ > > #include <dt-bindings/power/mt2701-power.h> > #include <dt-bindings/power/mt2712-power.h> > +#include <dt-bindings/power/mt6765-power.h> > #include <dt-bindings/power/mt6797-power.h> > #include <dt-bindings/power/mt7622-power.h> > #include <dt-bindings/power/mt7623a-power.h> > @@ -869,6 +870,120 @@ static const struct scp_subdomain scp_subdomain_mt2712[] = { > {MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3}, > }; > > +/* > + * MT6765 power domain support > + */ > +#define SPM_PWR_STATUS_MT6765 0x0180 > +#define SPM_PWR_STATUS_2ND_MT6765 0x0184 > + > +static const struct scp_domain_data scp_domain_data_mt6765[] = { > + [MT6765_POWER_DOMAIN_VCODEC] = { > + .name = "vcodec", > + .sta_mask = BIT(26), > + .ctl_offs = 0x300, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + }, > + [MT6765_POWER_DOMAIN_ISP] = { > + .name = "isp", > + .sta_mask = BIT(5), > + .ctl_offs = 0x308, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .subsys_clk_prefix = "isp", > + .bp_table = { > + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, > + BIT(20), BIT(20)), > + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0, > + BIT(2), BIT(2)), > + }, > + }, > + [MT6765_POWER_DOMAIN_MM] = { > + .name = "mm", > + .sta_mask = BIT(3), > + .ctl_offs = 0x30C, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .basic_clk_id = {"mm"}, > + .subsys_clk_prefix = "mm", > + .bp_table = { > + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, > + BIT(16) | BIT(17), BIT(16) | BIT(17)), > + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, > + BIT(10) | BIT(11), BIT(10) | BIT(11)), > + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, > + BIT(1) | BIT(2), BIT(1) | BIT(2)), > + }, > + }, > + [MT6765_POWER_DOMAIN_CONN] = { > + .name = "conn", > + .sta_mask = BIT(1), > + .ctl_offs = 0x32C, > + .sram_pdn_bits = 0, > + .sram_pdn_ack_bits = 0, > + .bp_table = { > + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, > + BIT(13), BIT(13)), > + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, > + BIT(18), BIT(18)), > + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, > + BIT(14) | BIT(16), BIT(14) | BIT(16)), > + }, > + }, > + [MT6765_POWER_DOMAIN_MFG_ASYNC] = { > + .name = "mfg_async", > + .sta_mask = BIT(23), > + .ctl_offs = 0x334, > + .sram_pdn_bits = 0, > + .sram_pdn_ack_bits = 0, > + .basic_clk_id = {"mfg"}, > + }, > + [MT6765_POWER_DOMAIN_MFG] = { > + .name = "mfg", > + .sta_mask = BIT(4), > + .ctl_offs = 0x338, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_table = { > + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, > + BIT(25), BIT(25)), > + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, > + BIT(21) | BIT(22), BIT(21) | BIT(22)), > + } > + }, > + [MT6765_POWER_DOMAIN_CAM] = { > + .name = "cam", > + .sta_mask = BIT(25), > + .ctl_offs = 0x344, > + .sram_pdn_bits = GENMASK(8, 9), > + .sram_pdn_ack_bits = GENMASK(12, 13), > + .subsys_clk_prefix = "cam", > + .bp_table = { > + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, > + BIT(19) | BIT(21), BIT(19) | BIT(21)), > + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, > + BIT(20), BIT(20)), > + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0, > + BIT(3), BIT(3)), > + } > + }, > + [MT6765_POWER_DOMAIN_MFG_CORE0] = { > + .name = "mfg_core0", > + .sta_mask = BIT(7), > + .ctl_offs = 0x34C, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + }, > +}; > + > +static const struct scp_subdomain scp_subdomain_mt6765[] = { > + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_CAM}, > + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_ISP}, > + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_VCODEC}, > + {MT6765_POWER_DOMAIN_MFG_ASYNC, MT6765_POWER_DOMAIN_MFG}, > + {MT6765_POWER_DOMAIN_MFG, MT6765_POWER_DOMAIN_MFG_CORE0}, > +}; > + > /* > * MT6797 power domain support > */ > @@ -1363,6 +1478,18 @@ static const struct scp_soc_data mt2712_data = { > .bus_prot_reg_update = false, > }; > > +static const struct scp_soc_data mt6765_data = { > + .domains = scp_domain_data_mt6765, > + .num_domains = ARRAY_SIZE(scp_domain_data_mt6765), > + .subdomains = scp_subdomain_mt6765, > + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6765), > + .regs = { > + .pwr_sta_offs = SPM_PWR_STATUS_MT6765, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6765, > + }, > + .bus_prot_reg_update = true, > +}; > + > static const struct scp_soc_data mt6797_data = { > .domains = scp_domain_data_mt6797, > .num_domains = ARRAY_SIZE(scp_domain_data_mt6797), > @@ -1429,6 +1556,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = { > }, { > .compatible = "mediatek,mt2712-scpsys", > .data = &mt2712_data, > + }, { > + .compatible = "mediatek,mt6765-scpsys", > + .data = &mt6765_data, > }, { > .compatible = "mediatek,mt6797-scpsys", > .data = &mt6797_data, > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v6 6/8] soc: mediatek: add MT6765 scpsys and subdomain support 2019-12-14 23:40 ` Matthias Brugger @ 2019-12-16 8:45 ` Matthias Brugger 0 siblings, 0 replies; 18+ messages in thread From: Matthias Brugger @ 2019-12-16 8:45 UTC (permalink / raw) To: Macpaul Lin, Rob Herring, Marc Zyngier, Ryder Lee, Stephen Boyd, Sean Wang, Mars Cheng, Owen Chen, linux-arm-kernel, linux-mediatek, linux-kernel Cc: devicetree, CC Hwang, wsd_upstream, Loda Chou, linux-serial, linux-clk On 15/12/2019 00:40, Matthias Brugger wrote: > > > On 12/07/2019 11:43, Macpaul Lin wrote: >> From: Mars Cheng <mars.cheng@mediatek.com> >> >> This adds scpsys support for MT6765 >> Add subdomain support for MT6765: >> isp, mm, connsys, mfg, and cam. >> >> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> >> Signed-off-by: Owen Chen <owen.chen@mediatek.com> >> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> > > Applied to v5.5-next/soc > I didn't realize this has dependencies with other series not yet merged. I drop this one for now as it breaks linux-next. Regards, Matthias >> --- >> drivers/soc/mediatek/mtk-scpsys.c | 130 ++++++++++++++++++++++++++++++ >> 1 file changed, 130 insertions(+) >> >> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c >> index ea5a221a16e9..ff124c514e9c 100644 >> --- a/drivers/soc/mediatek/mtk-scpsys.c >> +++ b/drivers/soc/mediatek/mtk-scpsys.c >> @@ -16,6 +16,7 @@ >> >> #include <dt-bindings/power/mt2701-power.h> >> #include <dt-bindings/power/mt2712-power.h> >> +#include <dt-bindings/power/mt6765-power.h> >> #include <dt-bindings/power/mt6797-power.h> >> #include <dt-bindings/power/mt7622-power.h> >> #include <dt-bindings/power/mt7623a-power.h> >> @@ -869,6 +870,120 @@ static const struct scp_subdomain scp_subdomain_mt2712[] = { >> {MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3}, >> }; >> >> +/* >> + * MT6765 power domain support >> + */ >> +#define SPM_PWR_STATUS_MT6765 0x0180 >> +#define SPM_PWR_STATUS_2ND_MT6765 0x0184 >> + >> +static const struct scp_domain_data scp_domain_data_mt6765[] = { >> + [MT6765_POWER_DOMAIN_VCODEC] = { >> + .name = "vcodec", >> + .sta_mask = BIT(26), >> + .ctl_offs = 0x300, >> + .sram_pdn_bits = GENMASK(8, 8), >> + .sram_pdn_ack_bits = GENMASK(12, 12), >> + }, >> + [MT6765_POWER_DOMAIN_ISP] = { >> + .name = "isp", >> + .sta_mask = BIT(5), >> + .ctl_offs = 0x308, >> + .sram_pdn_bits = GENMASK(8, 8), >> + .sram_pdn_ack_bits = GENMASK(12, 12), >> + .subsys_clk_prefix = "isp", >> + .bp_table = { >> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, >> + BIT(20), BIT(20)), >> + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0, >> + BIT(2), BIT(2)), >> + }, >> + }, >> + [MT6765_POWER_DOMAIN_MM] = { >> + .name = "mm", >> + .sta_mask = BIT(3), >> + .ctl_offs = 0x30C, >> + .sram_pdn_bits = GENMASK(8, 8), >> + .sram_pdn_ack_bits = GENMASK(12, 12), >> + .basic_clk_id = {"mm"}, >> + .subsys_clk_prefix = "mm", >> + .bp_table = { >> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, >> + BIT(16) | BIT(17), BIT(16) | BIT(17)), >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(10) | BIT(11), BIT(10) | BIT(11)), >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(1) | BIT(2), BIT(1) | BIT(2)), >> + }, >> + }, >> + [MT6765_POWER_DOMAIN_CONN] = { >> + .name = "conn", >> + .sta_mask = BIT(1), >> + .ctl_offs = 0x32C, >> + .sram_pdn_bits = 0, >> + .sram_pdn_ack_bits = 0, >> + .bp_table = { >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(13), BIT(13)), >> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, >> + BIT(18), BIT(18)), >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(14) | BIT(16), BIT(14) | BIT(16)), >> + }, >> + }, >> + [MT6765_POWER_DOMAIN_MFG_ASYNC] = { >> + .name = "mfg_async", >> + .sta_mask = BIT(23), >> + .ctl_offs = 0x334, >> + .sram_pdn_bits = 0, >> + .sram_pdn_ack_bits = 0, >> + .basic_clk_id = {"mfg"}, >> + }, >> + [MT6765_POWER_DOMAIN_MFG] = { >> + .name = "mfg", >> + .sta_mask = BIT(4), >> + .ctl_offs = 0x338, >> + .sram_pdn_bits = GENMASK(8, 8), >> + .sram_pdn_ack_bits = GENMASK(12, 12), >> + .bp_table = { >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(25), BIT(25)), >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(21) | BIT(22), BIT(21) | BIT(22)), >> + } >> + }, >> + [MT6765_POWER_DOMAIN_CAM] = { >> + .name = "cam", >> + .sta_mask = BIT(25), >> + .ctl_offs = 0x344, >> + .sram_pdn_bits = GENMASK(8, 9), >> + .sram_pdn_ack_bits = GENMASK(12, 13), >> + .subsys_clk_prefix = "cam", >> + .bp_table = { >> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258, >> + BIT(19) | BIT(21), BIT(19) | BIT(21)), >> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228, >> + BIT(20), BIT(20)), >> + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0, >> + BIT(3), BIT(3)), >> + } >> + }, >> + [MT6765_POWER_DOMAIN_MFG_CORE0] = { >> + .name = "mfg_core0", >> + .sta_mask = BIT(7), >> + .ctl_offs = 0x34C, >> + .sram_pdn_bits = GENMASK(8, 8), >> + .sram_pdn_ack_bits = GENMASK(12, 12), >> + }, >> +}; >> + >> +static const struct scp_subdomain scp_subdomain_mt6765[] = { >> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_CAM}, >> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_ISP}, >> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_VCODEC}, >> + {MT6765_POWER_DOMAIN_MFG_ASYNC, MT6765_POWER_DOMAIN_MFG}, >> + {MT6765_POWER_DOMAIN_MFG, MT6765_POWER_DOMAIN_MFG_CORE0}, >> +}; >> + >> /* >> * MT6797 power domain support >> */ >> @@ -1363,6 +1478,18 @@ static const struct scp_soc_data mt2712_data = { >> .bus_prot_reg_update = false, >> }; >> >> +static const struct scp_soc_data mt6765_data = { >> + .domains = scp_domain_data_mt6765, >> + .num_domains = ARRAY_SIZE(scp_domain_data_mt6765), >> + .subdomains = scp_subdomain_mt6765, >> + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6765), >> + .regs = { >> + .pwr_sta_offs = SPM_PWR_STATUS_MT6765, >> + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6765, >> + }, >> + .bus_prot_reg_update = true, >> +}; >> + >> static const struct scp_soc_data mt6797_data = { >> .domains = scp_domain_data_mt6797, >> .num_domains = ARRAY_SIZE(scp_domain_data_mt6797), >> @@ -1429,6 +1556,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = { >> }, { >> .compatible = "mediatek,mt2712-scpsys", >> .data = &mt2712_data, >> + }, { >> + .compatible = "mediatek,mt6765-scpsys", >> + .data = &mt6765_data, >> }, { >> .compatible = "mediatek,mt6797-scpsys", >> .data = &mt6797_data, >> _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v6 7/8] arm64: dts: mediatek: add mt6765 support 2019-07-12 9:43 [PATCH v6 0/8] Add basic SoC support for mt6765 Macpaul Lin ` (5 preceding siblings ...) 2019-07-12 9:43 ` [PATCH v6 6/8] soc: mediatek: add MT6765 scpsys and subdomain support Macpaul Lin @ 2019-07-12 9:43 ` Macpaul Lin 2019-07-15 8:29 ` CK Hu 2019-07-12 9:43 ` [PATCH v6 8/8] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks Macpaul Lin 7 siblings, 1 reply; 18+ messages in thread From: Macpaul Lin @ 2019-07-12 9:43 UTC (permalink / raw) To: Rob Herring, Marc Zyngier, Ryder Lee, Stephen Boyd, Sean Wang, Mars Cheng, Owen Chen, Matthias Brugger, linux-arm-kernel, linux-mediatek, linux-kernel Cc: wsd_upstream, CC Hwang, Loda Chou, devicetree, linux-serial, linux-clk, Macpaul Lin From: Mars Cheng <mars.cheng@mediatek.com> Add basic chip support for Mediatek 6765, include uart node with correct uart clocks, pwrap device Add clock controller nodes, include topckgen, infracfg, apmixedsys and subsystem. Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Owen Chen <owen.chen@mediatek.com> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 +++ arch/arm64/boot/dts/mediatek/mt6765.dtsi | 253 ++++++++++++++++++++ 3 files changed, 287 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 458bbc422a94..22bdf1a99a62 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6765-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt6765-evb.dts b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts new file mode 100644 index 000000000000..36dddff2b7f8 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Mediatek MT6765 + * + * (C) Copyright 2018. Mediatek, Inc. + * + * Mars Cheng <mars.cheng@mediatek.com> + */ + +/dts-v1/; +#include "mt6765.dtsi" + +/ { + model = "MediaTek MT6765 EVB"; + compatible = "mediatek,mt6765-evb", "mediatek,mt6765"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1e800000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6765.dtsi b/arch/arm64/boot/dts/mediatek/mt6765.dtsi new file mode 100644 index 000000000000..2662470fe607 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6765.dtsi @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Mediatek MT6765 + * + * (C) Copyright 2018. Mediatek, Inc. + * + * Mars Cheng <mars.cheng@mediatek.com> + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/mt6765-clk.h> + +/ { + compatible = "mediatek,mt6765"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x001>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x002>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x003>; + }; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x101>; + }; + + cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x102>; + }; + + cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x103>; + }; + }; + + clocks { + clk26m: clk26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk32k: clk32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c100000 0 0x200000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x2000>, /* GICH */ + <0 0x0c420000 0 0x20000>; /* GICV */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt6765-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt6765-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + interrupts = <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>; + #clock-cells = <1>; + }; + + pericfg: pericfg@10003000 { + compatible = "mediatek,mt6765-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + }; + + scpsys: scpsys@10006000 { + compatible = "mediatek,mt6765-scpsys"; + reg = <0 0x10006000 0 0x1000>; /* spm */ + #power-domain-cells = <1>; + clocks = <&topckgen CLK_TOP_MFG_SEL>, + <&topckgen CLK_TOP_MM_SEL>, + <&mmsys_config CLK_MM_SMI_COMMON>, + <&mmsys_config CLK_MM_SMI_COMM0>, + <&mmsys_config CLK_MM_SMI_COMM1>, + <&mmsys_config CLK_MM_SMI_LARB0>, + <&imgsys CLK_IMG_LARB2>, + <&mmsys_config CLK_MM_SMI_IMG>, + <&camsys CLK_CAM_LARB3>, + <&camsys CLK_CAM_DFP_VAD>, + <&camsys CLK_CAM>, + <&camsys CLK_CAM_CCU>, + <&mmsys_config CLK_MM_SMI_CAM>; + clock-names = "mfg", "mm", + "mm-0", "mm-1", "mm-2", "mm-3", + "isp-0", "isp-1", "cam-0", "cam-1", + "cam-2", "cam-3", "cam-4"; + infracfg = <&infracfg>; + smi_comm = <&smi_common>; + }; + + apmixed: syscon@1000c000 { + compatible = "mediatek,mt6765-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + sysirq: interrupt-controller@10200a80 { + compatible = "mediatek,mt6765-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200a80 0 0x50>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6765-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_IFR_UART0>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6765-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_IFR_UART1>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + audio: syscon@11220000 { + compatible = "mediatek,mt6765-audsys", "syscon"; + reg = <0 0x11220000 0 0x1000>; + #clock-cells = <1>; + }; + + mipi_rx_ana_csi0a: syscon@11c10000 { + compatible = "mediatek,mt6765-mipi0a", + "syscon"; + reg = <0 0x11c10000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys_config: syscon@14000000 { + compatible = "mediatek,mt6765-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + }; + + smi_common: smi_common@14002000 { + compatible = "mediatek,mt6765-smi-common", "syscon"; + reg = <0 0x14002000 0 0x1000>; + }; + + imgsys: syscon@15020000 { + compatible = "mediatek,mt6765-imgsys", "syscon"; + reg = <0 0x15020000 0 0x1000>; + #clock-cells = <1>; + }; + + venc_gcon: syscon@17000000 { + compatible = "mediatek,mt6765-vcodecsys", "syscon"; + reg = <0 0x17000000 0 0x10000>; + #clock-cells = <1>; + }; + + camsys: syscon@1a000000 { + compatible = "mediatek,mt6765-camsys", "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + }; /* end of soc */ +}; -- 2.18.0 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v6 7/8] arm64: dts: mediatek: add mt6765 support 2019-07-12 9:43 ` [PATCH v6 7/8] arm64: dts: mediatek: add mt6765 support Macpaul Lin @ 2019-07-15 8:29 ` CK Hu 0 siblings, 0 replies; 18+ messages in thread From: CK Hu @ 2019-07-15 8:29 UTC (permalink / raw) To: Macpaul Lin Cc: Rob Herring, Marc Zyngier, Ryder Lee, Stephen Boyd, Sean Wang, Mars Cheng, Owen Chen, Matthias Brugger, linux-arm-kernel, linux-mediatek, linux-kernel, devicetree, CC Hwang, wsd_upstream, Loda Chou, linux-serial, linux-clk Hi, Macpaul: On Fri, 2019-07-12 at 17:43 +0800, Macpaul Lin wrote: > From: Mars Cheng <mars.cheng@mediatek.com> > > Add basic chip support for Mediatek 6765, include > uart node with correct uart clocks, pwrap device > > Add clock controller nodes, include topckgen, infracfg, > apmixedsys and subsystem. > > Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> > Signed-off-by: Owen Chen <owen.chen@mediatek.com> > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> > Acked-by: Marc Zyngier <marc.zyngier@arm.com> > --- > arch/arm64/boot/dts/mediatek/Makefile | 1 + > arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 +++ > arch/arm64/boot/dts/mediatek/mt6765.dtsi | 253 ++++++++++++++++++++ > 3 files changed, 287 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > index 458bbc422a94..22bdf1a99a62 100644 > --- a/arch/arm64/boot/dts/mediatek/Makefile > +++ b/arch/arm64/boot/dts/mediatek/Makefile > @@ -1,6 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0 > dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6765-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb > diff --git a/arch/arm64/boot/dts/mediatek/mt6765-evb.dts b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts > new file mode 100644 > index 000000000000..36dddff2b7f8 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt6765-evb.dts > @@ -0,0 +1,33 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * dts file for Mediatek MT6765 > + * > + * (C) Copyright 2018. Mediatek, Inc. > + * > + * Mars Cheng <mars.cheng@mediatek.com> > + */ > + > +/dts-v1/; > +#include "mt6765.dtsi" > + > +/ { > + model = "MediaTek MT6765 EVB"; > + compatible = "mediatek,mt6765-evb", "mediatek,mt6765"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + memory@40000000 { > + device_type = "memory"; > + reg = <0 0x40000000 0 0x1e800000>; > + }; > + > + chosen { > + stdout-path = "serial0:921600n8"; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/mediatek/mt6765.dtsi b/arch/arm64/boot/dts/mediatek/mt6765.dtsi > new file mode 100644 > index 000000000000..2662470fe607 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt6765.dtsi > @@ -0,0 +1,253 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * dts file for Mediatek MT6765 > + * > + * (C) Copyright 2018. Mediatek, Inc. > + * > + * Mars Cheng <mars.cheng@mediatek.com> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/mt6765-clk.h> > + > +/ { > + compatible = "mediatek,mt6765"; > + interrupt-parent = <&sysirq>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + psci { > + compatible = "arm,psci-0.2"; > + method = "smc"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x000>; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x001>; > + }; > + > + cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x002>; > + }; > + > + cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x003>; > + }; > + > + cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x100>; > + }; > + > + cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x101>; > + }; > + > + cpu@102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x102>; > + }; > + > + cpu@103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + enable-method = "psci"; > + reg = <0x103>; > + }; > + }; > + > + clocks { > + clk26m: clk26m { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <26000000>; > + }; > + > + clk32k: clk32k { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32000>; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + > + gic: interrupt-controller@c000000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + reg = <0 0x0c000000 0 0x40000>, /* GICD */ > + <0 0x0c100000 0 0x200000>, /* GICR */ > + <0 0x0c400000 0 0x2000>, /* GICC */ > + <0 0x0c410000 0 0x2000>, /* GICH */ > + <0 0x0c420000 0 0x20000>; /* GICV */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + topckgen: syscon@10000000 { > + compatible = "mediatek,mt6765-topckgen", "syscon"; > + reg = <0 0x10000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + infracfg: syscon@10001000 { > + compatible = "mediatek,mt6765-infracfg", "syscon"; > + reg = <0 0x10001000 0 0x1000>; > + interrupts = <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>; > + #clock-cells = <1>; > + }; > + > + pericfg: pericfg@10003000 { > + compatible = "mediatek,mt6765-pericfg", "syscon"; > + reg = <0 0x10003000 0 0x1000>; > + }; > + > + scpsys: scpsys@10006000 { > + compatible = "mediatek,mt6765-scpsys"; > + reg = <0 0x10006000 0 0x1000>; /* spm */ > + #power-domain-cells = <1>; > + clocks = <&topckgen CLK_TOP_MFG_SEL>, > + <&topckgen CLK_TOP_MM_SEL>, > + <&mmsys_config CLK_MM_SMI_COMMON>, > + <&mmsys_config CLK_MM_SMI_COMM0>, > + <&mmsys_config CLK_MM_SMI_COMM1>, > + <&mmsys_config CLK_MM_SMI_LARB0>, I think you should remove subsys clock in scpsys device node. I've discussed in [1]. [1] https://patchwork.kernel.org/patch/11005731/ Regards, CK > + <&imgsys CLK_IMG_LARB2>, > + <&mmsys_config CLK_MM_SMI_IMG>, > + <&camsys CLK_CAM_LARB3>, > + <&camsys CLK_CAM_DFP_VAD>, > + <&camsys CLK_CAM>, > + <&camsys CLK_CAM_CCU>, > + <&mmsys_config CLK_MM_SMI_CAM>; > + clock-names = "mfg", "mm", > + "mm-0", "mm-1", "mm-2", "mm-3", > + "isp-0", "isp-1", "cam-0", "cam-1", > + "cam-2", "cam-3", "cam-4"; > + infracfg = <&infracfg>; > + smi_comm = <&smi_common>; > + }; > + > + apmixed: syscon@1000c000 { > + compatible = "mediatek,mt6765-apmixedsys", "syscon"; > + reg = <0 0x1000c000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + sysirq: interrupt-controller@10200a80 { > + compatible = "mediatek,mt6765-sysirq", > + "mediatek,mt6577-sysirq"; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupt-parent = <&gic>; > + reg = <0 0x10200a80 0 0x50>; > + }; > + > + uart0: serial@11002000 { > + compatible = "mediatek,mt6765-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11002000 0 0x400>; > + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_IFR_UART0>, > + <&infracfg CLK_IFR_AP_DMA>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart1: serial@11003000 { > + compatible = "mediatek,mt6765-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11003000 0 0x400>; > + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&infracfg CLK_IFR_UART1>, > + <&infracfg CLK_IFR_AP_DMA>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + audio: syscon@11220000 { > + compatible = "mediatek,mt6765-audsys", "syscon"; > + reg = <0 0x11220000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mipi_rx_ana_csi0a: syscon@11c10000 { > + compatible = "mediatek,mt6765-mipi0a", > + "syscon"; > + reg = <0 0x11c10000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mmsys_config: syscon@14000000 { > + compatible = "mediatek,mt6765-mmsys", "syscon"; > + reg = <0 0x14000000 0 0x1000>; > + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; > + #clock-cells = <1>; > + }; > + > + smi_common: smi_common@14002000 { > + compatible = "mediatek,mt6765-smi-common", "syscon"; > + reg = <0 0x14002000 0 0x1000>; > + }; > + > + imgsys: syscon@15020000 { > + compatible = "mediatek,mt6765-imgsys", "syscon"; > + reg = <0 0x15020000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + venc_gcon: syscon@17000000 { > + compatible = "mediatek,mt6765-vcodecsys", "syscon"; > + reg = <0 0x17000000 0 0x10000>; > + #clock-cells = <1>; > + }; > + > + camsys: syscon@1a000000 { > + compatible = "mediatek,mt6765-camsys", "syscon"; > + reg = <0 0x1a000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + }; /* end of soc */ > +}; ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v6 8/8] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks 2019-07-12 9:43 [PATCH v6 0/8] Add basic SoC support for mt6765 Macpaul Lin ` (6 preceding siblings ...) 2019-07-12 9:43 ` [PATCH v6 7/8] arm64: dts: mediatek: add mt6765 support Macpaul Lin @ 2019-07-12 9:43 ` Macpaul Lin 7 siblings, 0 replies; 18+ messages in thread From: Macpaul Lin @ 2019-07-12 9:43 UTC (permalink / raw) To: Rob Herring, Marc Zyngier, Ryder Lee, Stephen Boyd, Sean Wang, Mars Cheng, Owen Chen, Matthias Brugger, linux-arm-kernel, linux-mediatek, linux-kernel Cc: wsd_upstream, CC Hwang, Loda Chou, devicetree, linux-serial, linux-clk, Macpaul Lin From: Owen Chen <owen.chen@mediatek.com> Enable MT6765 clock configs, include topckgen, apmixedsys, infracfg, and subsystem clocks. Signed-off-by: Owen Chen <owen.chen@mediatek.com> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> --- arch/arm64/configs/defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4d583514258c..7ab4d09120bb 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -455,6 +455,12 @@ CONFIG_REGULATOR_QCOM_SMD_RPM=y CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_REGULATOR_RK808=y CONFIG_REGULATOR_S2MPS11=y +CONFIG_COMMON_CLK_MT6765_AUDIOSYS=y +CONFIG_COMMON_CLK_MT6765_CAMSYS=y +CONFIG_COMMON_CLK_MT6765_MMSYS=y +CONFIG_COMMON_CLK_MT6765_IMGSYS=y +CONFIG_COMMON_CLK_MT6765_VCODECSYS=y +CONFIG_COMMON_CLK_MT6765_MIPI0ASYS=y CONFIG_REGULATOR_VCTRL=m CONFIG_RC_CORE=m CONFIG_RC_DECODERS=y -- 2.18.0 ^ permalink raw reply related [flat|nested] 18+ messages in thread
end of thread, other threads:[~2019-12-16 8:45 UTC | newest] Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-07-12 9:43 [PATCH v6 0/8] Add basic SoC support for mt6765 Macpaul Lin 2019-07-12 9:43 ` [PATCH v6 1/8] dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC Macpaul Lin 2019-07-24 20:45 ` Rob Herring 2019-07-12 9:43 ` [PATCH v6 2/8] dt-bindings: mediatek: Add smi dts binding " Macpaul Lin 2019-07-12 9:43 ` [PATCH v6 3/8] dt-bindings: mediatek: add MT6765 power dt-bindings Macpaul Lin 2019-12-14 23:40 ` Matthias Brugger 2019-07-12 9:43 ` [PATCH v6 4/8] clk: mediatek: add mt6765 clock IDs Macpaul Lin 2019-07-24 20:46 ` Rob Herring 2019-07-12 9:43 ` [PATCH v6 5/8] clk: mediatek: Add MT6765 clock support Macpaul Lin 2019-08-15 0:27 ` Stephen Boyd 2019-08-15 13:44 ` Greg KH 2019-12-02 8:55 ` Owen Chen 2019-07-12 9:43 ` [PATCH v6 6/8] soc: mediatek: add MT6765 scpsys and subdomain support Macpaul Lin 2019-12-14 23:40 ` Matthias Brugger 2019-12-16 8:45 ` Matthias Brugger 2019-07-12 9:43 ` [PATCH v6 7/8] arm64: dts: mediatek: add mt6765 support Macpaul Lin 2019-07-15 8:29 ` CK Hu 2019-07-12 9:43 ` [PATCH v6 8/8] arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks Macpaul Lin
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).