* [RESEND v2 0/4] Add Support for MediaTek PMIC MT6359 Regulator
@ 2020-02-21 2:39 Wen Su
2020-02-21 2:39 ` [RESEND v2 1/4] dt-bindings: regulator: Add document for MT6359 regulator Wen Su
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Wen Su @ 2020-02-21 2:39 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger
Cc: Mark Rutland, devicetree, wen.su, wsd_upstream, linux-kernel,
Liam Girdwood, linux-mediatek, linux-arm-kernel
This patchset add support to MT6359 PMIC regulator. MT6359 is primary
PMIC for MT6779 platform.
Changes since v2:
- remove open coding in the mt6359 regulator for volt_table type regulators
- refine coding style in the mt6359 regulator to avoid using ternery operator
- remove unnecessary reject operation in mt6359 regulator set mode function
wen.su (4):
dt-bindings: regulator: Add document for MT6359 regulator
mfd: Add for PMIC MT6359 registers definition
regulator: mt6359: Add support for MT6359 regulator
arm64: dts: mt6359: add PMIC MT6359 related nodes
.../bindings/regulator/mt6359-regulator.txt | 59 ++
arch/arm64/boot/dts/mediatek/mt6359.dtsi | 312 ++++++++
drivers/regulator/Kconfig | 9 +
drivers/regulator/Makefile | 1 +
drivers/regulator/mt6359-regulator.c | 859 +++++++++++++++++++++
include/linux/mfd/mt6359/registers.h | 531 +++++++++++++
include/linux/regulator/mt6359-regulator.h | 58 ++
7 files changed, 1829 insertions(+)
create mode 100644 Documentation/devicetree/bindings/regulator/mt6359-regulator.txt
create mode 100644 arch/arm64/boot/dts/mediatek/mt6359.dtsi
create mode 100644 drivers/regulator/mt6359-regulator.c
create mode 100644 include/linux/mfd/mt6359/registers.h
create mode 100644 include/linux/regulator/mt6359-regulator.h
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [RESEND v2 1/4] dt-bindings: regulator: Add document for MT6359 regulator
2020-02-21 2:39 [RESEND v2 0/4] Add Support for MediaTek PMIC MT6359 Regulator Wen Su
@ 2020-02-21 2:39 ` Wen Su
2020-02-21 2:39 ` [RESEND v2 2/4] mfd: Add for PMIC MT6359 registers definition Wen Su
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Wen Su @ 2020-02-21 2:39 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger
Cc: Mark Rutland, devicetree, wen.su, wsd_upstream, linux-kernel,
Liam Girdwood, linux-mediatek, linux-arm-kernel
From: "Wen Su" <wen.su@mediatek.com>
add dt-binding document for MediaTek MT6359 PMIC
Signed-off-by: Wen Su <wen.su@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/regulator/mt6359-regulator.txt | 58 ++++++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/regulator/mt6359-regulator.txt
diff --git a/Documentation/devicetree/bindings/regulator/mt6359-regulator.txt b/Documentation/devicetree/bindings/regulator/mt6359-regulator.txt
new file mode 100644
index 0000000..c86aaa9
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/mt6359-regulator.txt
@@ -0,0 +1,58 @@
+Mediatek MT6359 Regulator
+
+Required properties:
+- compatible: "mediatek,mt6359-regulator"
+- mt6359regulator: List of regulators provided by this controller. It is named
+ according to its regulator type, buck_<name> and ldo_<name>.
+ The definition for each of these nodes is defined using the standard binding
+ for regulators at Documentation/devicetree/bindings/regulator/regulator.txt.
+
+The valid names for regulators are:
+BUCK:
+ buck_vs1, buck_vgpu11, buck_vmodem, buck_vpu, buck_vcore, buck_vs2,
+ buck_vpa, buck_vproc2, buck_vproc1, buck_vcore_sshub
+LDO:
+ ldo_vaud18, ldo_vsim1, ldo_vibr, ldo_vrf12, ldo_vusb, ldo_vsram_proc2,
+ ldo_vio18, ldo_vcamio, ldo_vcn18, ldo_vfe28, ldo_vcn13, ldo_vcn33_1_bt,
+ ldo_vcn13_1_wifi, ldo_vaux18, ldo_vsram_others, ldo_vefuse, ldo_vxo22,
+ ldo_vrfck, ldo_vbif28, ldo_vio28, ldo_vemc, ldo_vcn33_2_bt, ldo_vcn33_2_wifi,
+ ldo_va12, ldo_va09, ldo_vrf18, ldo_vsram_md, ldo_vufs, ldo_vm18, ldo_vbbck,
+ ldo_vsram_proc1, ldo_vsim2, ldo_vsram_others_sshub
+
+Example:
+ pmic {
+ compatible = "mediatek,mt6359";
+
+ mt6359regulator: mt6359regulator {
+ compatible = "mediatek,mt6359-regulator";
+
+ mt6359_vs1_buck_reg: buck_vs1 {
+ regulator-name = "vs1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-always-on;
+ };
+ mt6359_vgpu11_buck_reg: buck_vgpu11 {
+ regulator-name = "vgpu11";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-always-on;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ mt6359_vaud18_ldo_reg: ldo_vaud18 {
+ regulator-name = "vaud18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vsim1_ldo_reg: ldo_vsim1 {
+ regulator-name = "vsim1";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-enable-ramp-delay = <480>;
+ };
+ };
+ };
+
--
1.9.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* [RESEND v2 2/4] mfd: Add for PMIC MT6359 registers definition
2020-02-21 2:39 [RESEND v2 0/4] Add Support for MediaTek PMIC MT6359 Regulator Wen Su
2020-02-21 2:39 ` [RESEND v2 1/4] dt-bindings: regulator: Add document for MT6359 regulator Wen Su
@ 2020-02-21 2:39 ` Wen Su
2020-06-16 9:58 ` Wen Su
2020-02-21 2:39 ` [RESEND v2 3/4] regulator: mt6359: Add support for MT6359 regulator Wen Su
2020-02-21 2:39 ` [RESEND v2 4/4] arm64: dts: mt6359: add PMIC MT6359 related nodes Wen Su
3 siblings, 1 reply; 7+ messages in thread
From: Wen Su @ 2020-02-21 2:39 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger
Cc: Mark Rutland, devicetree, wen.su, wsd_upstream, linux-kernel,
Liam Girdwood, linux-mediatek, linux-arm-kernel
From: "Wen Su" <wen.su@mediatek.com>
This adds MediaTek PMIC MT6359 registers definition for the
following sub modules:
- Regulator
- RTC
- Interrupt
Signed-off-by: Wen Su <wen.su@mediatek.com>
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
---
include/linux/mfd/mt6359/registers.h | 531 +++++++++++++++++++++++++++++++++++
1 file changed, 531 insertions(+)
create mode 100644 include/linux/mfd/mt6359/registers.h
diff --git a/include/linux/mfd/mt6359/registers.h b/include/linux/mfd/mt6359/registers.h
new file mode 100644
index 0000000..32f627e
--- /dev/null
+++ b/include/linux/mfd/mt6359/registers.h
@@ -0,0 +1,531 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MFD_MT6359_REGISTERS_H__
+#define __MFD_MT6359_REGISTERS_H__
+
+/* PMIC Registers */
+#define MT6359_SWCID 0xa
+#define MT6359_MISC_TOP_INT_CON0 0x188
+#define MT6359_MISC_TOP_INT_STATUS0 0x194
+#define MT6359_TOP_INT_STATUS0 0x19e
+#define MT6359_SCK_TOP_INT_CON0 0x528
+#define MT6359_SCK_TOP_INT_STATUS0 0x534
+#define MT6359_EOSC_CALI_CON0 0x53a
+#define MT6359_EOSC_CALI_CON1 0x53c
+#define MT6359_RTC_MIX_CON0 0x53e
+#define MT6359_RTC_MIX_CON1 0x540
+#define MT6359_RTC_MIX_CON2 0x542
+#define MT6359_RTC_DSN_ID 0x580
+#define MT6359_RTC_DSN_REV0 0x582
+#define MT6359_RTC_DBI 0x584
+#define MT6359_RTC_DXI 0x586
+#define MT6359_RTC_BBPU 0x588
+#define MT6359_RTC_IRQ_STA 0x58a
+#define MT6359_RTC_IRQ_EN 0x58c
+#define MT6359_RTC_CII_EN 0x58e
+#define MT6359_RTC_AL_MASK 0x590
+#define MT6359_RTC_TC_SEC 0x592
+#define MT6359_RTC_TC_MIN 0x594
+#define MT6359_RTC_TC_HOU 0x596
+#define MT6359_RTC_TC_DOM 0x598
+#define MT6359_RTC_TC_DOW 0x59a
+#define MT6359_RTC_TC_MTH 0x59c
+#define MT6359_RTC_TC_YEA 0x59e
+#define MT6359_RTC_AL_SEC 0x5a0
+#define MT6359_RTC_AL_MIN 0x5a2
+#define MT6359_RTC_AL_HOU 0x5a4
+#define MT6359_RTC_AL_DOM 0x5a6
+#define MT6359_RTC_AL_DOW 0x5a8
+#define MT6359_RTC_AL_MTH 0x5aa
+#define MT6359_RTC_AL_YEA 0x5ac
+#define MT6359_RTC_OSC32CON 0x5ae
+#define MT6359_RTC_POWERKEY1 0x5b0
+#define MT6359_RTC_POWERKEY2 0x5b2
+#define MT6359_RTC_PDN1 0x5b4
+#define MT6359_RTC_PDN2 0x5b6
+#define MT6359_RTC_SPAR0 0x5b8
+#define MT6359_RTC_SPAR1 0x5ba
+#define MT6359_RTC_PROT 0x5bc
+#define MT6359_RTC_DIFF 0x5be
+#define MT6359_RTC_CALI 0x5c0
+#define MT6359_RTC_WRTGR 0x5c2
+#define MT6359_RTC_CON 0x5c4
+#define MT6359_RTC_SEC_CTRL 0x5c6
+#define MT6359_RTC_INT_CNT 0x5c8
+#define MT6359_RTC_SEC_DAT0 0x5ca
+#define MT6359_RTC_SEC_DAT1 0x5cc
+#define MT6359_RTC_SEC_DAT2 0x5ce
+#define MT6359_RTC_SEC_DSN_ID 0x600
+#define MT6359_RTC_SEC_DSN_REV0 0x602
+#define MT6359_RTC_SEC_DBI 0x604
+#define MT6359_RTC_SEC_DXI 0x606
+#define MT6359_RTC_TC_SEC_SEC 0x608
+#define MT6359_RTC_TC_MIN_SEC 0x60a
+#define MT6359_RTC_TC_HOU_SEC 0x60c
+#define MT6359_RTC_TC_DOM_SEC 0x60e
+#define MT6359_RTC_TC_DOW_SEC 0x610
+#define MT6359_RTC_TC_MTH_SEC 0x612
+#define MT6359_RTC_TC_YEA_SEC 0x614
+#define MT6359_RTC_SEC_CK_PDN 0x616
+#define MT6359_RTC_SEC_WRTGR 0x618
+#define MT6359_PSC_TOP_INT_CON0 0x910
+#define MT6359_PSC_TOP_INT_STATUS0 0x91c
+#define MT6359_BM_TOP_INT_CON0 0xc32
+#define MT6359_BM_TOP_INT_CON1 0xc38
+#define MT6359_BM_TOP_INT_STATUS0 0xc4a
+#define MT6359_BM_TOP_INT_STATUS1 0xc4c
+#define MT6359_HK_TOP_INT_CON0 0xf92
+#define MT6359_HK_TOP_INT_STATUS0 0xf9e
+#define MT6359_BUCK_TOP_INT_CON0 0x1418
+#define MT6359_BUCK_TOP_INT_STATUS0 0x1424
+#define MT6359_BUCK_VPU_CON0 0x1488
+#define MT6359_BUCK_VPU_DBG0 0x14a6
+#define MT6359_BUCK_VPU_DBG1 0x14a8
+#define MT6359_BUCK_VPU_ELR0 0x14ac
+#define MT6359_BUCK_VCORE_CON0 0x1508
+#define MT6359_BUCK_VCORE_DBG0 0x1526
+#define MT6359_BUCK_VCORE_DBG1 0x1528
+#define MT6359_BUCK_VCORE_SSHUB_CON0 0x152a
+#define MT6359_BUCK_VCORE_ELR0 0x1534
+#define MT6359_BUCK_VGPU11_CON0 0x1588
+#define MT6359_BUCK_VGPU11_DBG0 0x15a6
+#define MT6359_BUCK_VGPU11_DBG1 0x15a8
+#define MT6359_BUCK_VGPU11_ELR0 0x15ac
+#define MT6359_BUCK_VMODEM_CON0 0x1688
+#define MT6359_BUCK_VMODEM_DBG0 0x16a6
+#define MT6359_BUCK_VMODEM_DBG1 0x16a8
+#define MT6359_BUCK_VMODEM_ELR0 0x16ae
+#define MT6359_BUCK_VPROC1_CON0 0x1708
+#define MT6359_BUCK_VPROC1_DBG0 0x1726
+#define MT6359_BUCK_VPROC1_DBG1 0x1728
+#define MT6359_BUCK_VPROC1_ELR0 0x172e
+#define MT6359_BUCK_VPROC2_CON0 0x1788
+#define MT6359_BUCK_VPROC2_DBG0 0x17a6
+#define MT6359_BUCK_VPROC2_DBG1 0x17a8
+#define MT6359_BUCK_VPROC2_ELR0 0x17b2
+#define MT6359_BUCK_VS1_CON0 0x1808
+#define MT6359_BUCK_VS1_DBG0 0x1826
+#define MT6359_BUCK_VS1_DBG1 0x1828
+#define MT6359_BUCK_VS1_ELR0 0x1834
+#define MT6359_BUCK_VS2_CON0 0x1888
+#define MT6359_BUCK_VS2_DBG0 0x18a6
+#define MT6359_BUCK_VS2_DBG1 0x18a8
+#define MT6359_BUCK_VS2_ELR0 0x18b4
+#define MT6359_BUCK_VPA_CON0 0x1908
+#define MT6359_BUCK_VPA_CON1 0x190e
+#define MT6359_BUCK_VPA_CFG0 0x1910
+#define MT6359_BUCK_VPA_CFG1 0x1912
+#define MT6359_BUCK_VPA_DBG0 0x1914
+#define MT6359_BUCK_VPA_DBG1 0x1916
+#define MT6359_VGPUVCORE_ANA_CON2 0x198e
+#define MT6359_VGPUVCORE_ANA_CON13 0x19a4
+#define MT6359_VPROC1_ANA_CON3 0x19b2
+#define MT6359_VPROC2_ANA_CON3 0x1a0e
+#define MT6359_VMODEM_ANA_CON3 0x1a1a
+#define MT6359_VPU_ANA_CON3 0x1a26
+#define MT6359_VS1_ANA_CON0 0x1a2c
+#define MT6359_VS2_ANA_CON0 0x1a34
+#define MT6359_VPA_ANA_CON0 0x1a3c
+#define MT6359_LDO_TOP_INT_CON0 0x1b14
+#define MT6359_LDO_TOP_INT_CON1 0x1b1a
+#define MT6359_LDO_TOP_INT_STATUS0 0x1b28
+#define MT6359_LDO_TOP_INT_STATUS1 0x1b2a
+#define MT6359_LDO_VSRAM_PROC1_ELR 0x1b40
+#define MT6359_LDO_VSRAM_PROC2_ELR 0x1b42
+#define MT6359_LDO_VSRAM_OTHERS_ELR 0x1b44
+#define MT6359_LDO_VSRAM_MD_ELR 0x1b46
+#define MT6359_LDO_VFE28_CON0 0x1b88
+#define MT6359_LDO_VFE28_MON 0x1b8a
+#define MT6359_LDO_VXO22_CON0 0x1b98
+#define MT6359_LDO_VXO22_MON 0x1b9a
+#define MT6359_LDO_VRF18_CON0 0x1ba8
+#define MT6359_LDO_VRF18_MON 0x1baa
+#define MT6359_LDO_VRF12_CON0 0x1bb8
+#define MT6359_LDO_VRF12_MON 0x1bba
+#define MT6359_LDO_VEFUSE_CON0 0x1bc8
+#define MT6359_LDO_VEFUSE_MON 0x1bca
+#define MT6359_LDO_VCN33_1_CON0 0x1bd8
+#define MT6359_LDO_VCN33_1_MON 0x1bda
+#define MT6359_LDO_VCN33_1_MULTI_SW 0x1be8
+#define MT6359_LDO_VCN33_2_CON0 0x1c08
+#define MT6359_LDO_VCN33_2_MON 0x1c0a
+#define MT6359_LDO_VCN33_2_MULTI_SW 0x1c18
+#define MT6359_LDO_VCN13_CON0 0x1c1a
+#define MT6359_LDO_VCN13_MON 0x1c1c
+#define MT6359_LDO_VCN18_CON0 0x1c2a
+#define MT6359_LDO_VCN18_MON 0x1c2c
+#define MT6359_LDO_VA09_CON0 0x1c3a
+#define MT6359_LDO_VA09_MON 0x1c3c
+#define MT6359_LDO_VCAMIO_CON0 0x1c4a
+#define MT6359_LDO_VCAMIO_MON 0x1c4c
+#define MT6359_LDO_VA12_CON0 0x1c5a
+#define MT6359_LDO_VA12_MON 0x1c5c
+#define MT6359_LDO_VAUX18_CON0 0x1c88
+#define MT6359_LDO_VAUX18_MON 0x1c8a
+#define MT6359_LDO_VAUD18_CON0 0x1c98
+#define MT6359_LDO_VAUD18_MON 0x1c9a
+#define MT6359_LDO_VIO18_CON0 0x1ca8
+#define MT6359_LDO_VIO18_MON 0x1caa
+#define MT6359_LDO_VEMC_CON0 0x1cb8
+#define MT6359_LDO_VEMC_MON 0x1cba
+#define MT6359_LDO_VSIM1_CON0 0x1cc8
+#define MT6359_LDO_VSIM1_MON 0x1cca
+#define MT6359_LDO_VSIM2_CON0 0x1cd8
+#define MT6359_LDO_VSIM2_MON 0x1cda
+#define MT6359_LDO_VUSB_CON0 0x1d08
+#define MT6359_LDO_VUSB_MON 0x1d0a
+#define MT6359_LDO_VUSB_MULTI_SW 0x1d18
+#define MT6359_LDO_VRFCK_CON0 0x1d1a
+#define MT6359_LDO_VRFCK_MON 0x1d1c
+#define MT6359_LDO_VBBCK_CON0 0x1d2a
+#define MT6359_LDO_VBBCK_MON 0x1d2c
+#define MT6359_LDO_VBIF28_CON0 0x1d3a
+#define MT6359_LDO_VBIF28_MON 0x1d3c
+#define MT6359_LDO_VIBR_CON0 0x1d4a
+#define MT6359_LDO_VIBR_MON 0x1d4c
+#define MT6359_LDO_VIO28_CON0 0x1d5a
+#define MT6359_LDO_VIO28_MON 0x1d5c
+#define MT6359_LDO_VM18_CON0 0x1d88
+#define MT6359_LDO_VM18_MON 0x1d8a
+#define MT6359_LDO_VUFS_CON0 0x1d98
+#define MT6359_LDO_VUFS_MON 0x1d9a
+#define MT6359_LDO_VSRAM_PROC1_CON0 0x1e88
+#define MT6359_LDO_VSRAM_PROC1_MON 0x1e8a
+#define MT6359_LDO_VSRAM_PROC1_VOSEL1 0x1e8e
+#define MT6359_LDO_VSRAM_PROC2_CON0 0x1ea6
+#define MT6359_LDO_VSRAM_PROC2_MON 0x1ea8
+#define MT6359_LDO_VSRAM_PROC2_VOSEL1 0x1eac
+#define MT6359_LDO_VSRAM_OTHERS_CON0 0x1f08
+#define MT6359_LDO_VSRAM_OTHERS_MON 0x1f0a
+#define MT6359_LDO_VSRAM_OTHERS_VOSEL1 0x1f0e
+#define MT6359_LDO_VSRAM_OTHERS_SSHUB 0x1f26
+#define MT6359_LDO_VSRAM_MD_CON0 0x1f2c
+#define MT6359_LDO_VSRAM_MD_MON 0x1f2e
+#define MT6359_LDO_VSRAM_MD_VOSEL1 0x1f32
+#define MT6359_VFE28_ANA_CON0 0x1f88
+#define MT6359_VAUX18_ANA_CON0 0x1f8c
+#define MT6359_VUSB_ANA_CON0 0x1f90
+#define MT6359_VBIF28_ANA_CON0 0x1f94
+#define MT6359_VCN33_1_ANA_CON0 0x1f98
+#define MT6359_VCN33_2_ANA_CON0 0x1f9c
+#define MT6359_VEMC_ANA_CON0 0x1fa0
+#define MT6359_VSIM1_ANA_CON0 0x1fa4
+#define MT6359_VSIM2_ANA_CON0 0x1fa8
+#define MT6359_VIO28_ANA_CON0 0x1fac
+#define MT6359_VIBR_ANA_CON0 0x1fb0
+#define MT6359_VRF18_ANA_CON0 0x2008
+#define MT6359_VEFUSE_ANA_CON0 0x200c
+#define MT6359_VCN18_ANA_CON0 0x2010
+#define MT6359_VCAMIO_ANA_CON0 0x2014
+#define MT6359_VAUD18_ANA_CON0 0x2018
+#define MT6359_VIO18_ANA_CON0 0x201c
+#define MT6359_VM18_ANA_CON0 0x2020
+#define MT6359_VUFS_ANA_CON0 0x2024
+#define MT6359_VRF12_ANA_CON0 0x202a
+#define MT6359_VCN13_ANA_CON0 0x202e
+#define MT6359_VA09_ANA_CON0 0x2032
+#define MT6359_VA12_ANA_CON0 0x2036
+#define MT6359_VXO22_ANA_CON0 0x2088
+#define MT6359_VRFCK_ANA_CON0 0x208c
+#define MT6359_VBBCK_ANA_CON0 0x2094
+#define MT6359_AUD_TOP_INT_CON0 0x2328
+#define MT6359_AUD_TOP_INT_STATUS0 0x2334
+
+#define MT6359_RG_BUCK_VPU_EN_ADDR MT6359_BUCK_VPU_CON0
+#define MT6359_RG_BUCK_VPU_LP_ADDR MT6359_BUCK_VPU_CON0
+#define MT6359_RG_BUCK_VPU_LP_SHIFT 1
+#define MT6359_DA_VPU_VOSEL_ADDR MT6359_BUCK_VPU_DBG0
+#define MT6359_DA_VPU_VOSEL_MASK 0x7F
+#define MT6359_DA_VPU_VOSEL_SHIFT 0
+#define MT6359_DA_VPU_EN_ADDR MT6359_BUCK_VPU_DBG1
+#define MT6359_RG_BUCK_VPU_VOSEL_ADDR MT6359_BUCK_VPU_ELR0
+#define MT6359_RG_BUCK_VPU_VOSEL_MASK 0x7F
+#define MT6359_RG_BUCK_VPU_VOSEL_SHIFT 0
+#define MT6359_RG_BUCK_VCORE_EN_ADDR MT6359_BUCK_VCORE_CON0
+#define MT6359_RG_BUCK_VCORE_LP_ADDR MT6359_BUCK_VCORE_CON0
+#define MT6359_RG_BUCK_VCORE_LP_SHIFT 1
+#define MT6359_DA_VCORE_VOSEL_ADDR MT6359_BUCK_VCORE_DBG0
+#define MT6359_DA_VCORE_VOSEL_MASK 0x7F
+#define MT6359_DA_VCORE_VOSEL_SHIFT 0
+#define MT6359_DA_VCORE_EN_ADDR MT6359_BUCK_VCORE_DBG1
+#define MT6359_RG_BUCK_VCORE_SSHUB_EN_ADDR MT6359_BUCK_VCORE_SSHUB_CON0
+#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR MT6359_BUCK_VCORE_SSHUB_CON0
+#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK 0x7F
+#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT 4
+#define MT6359_RG_BUCK_VCORE_VOSEL_ADDR MT6359_BUCK_VCORE_ELR0
+#define MT6359_RG_BUCK_VCORE_VOSEL_MASK 0x7F
+#define MT6359_RG_BUCK_VCORE_VOSEL_SHIFT 0
+#define MT6359_RG_BUCK_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_CON0
+#define MT6359_RG_BUCK_VGPU11_LP_ADDR MT6359_BUCK_VGPU11_CON0
+#define MT6359_RG_BUCK_VGPU11_LP_SHIFT 1
+#define MT6359_DA_VGPU11_VOSEL_ADDR MT6359_BUCK_VGPU11_DBG0
+#define MT6359_DA_VGPU11_VOSEL_MASK 0x7F
+#define MT6359_DA_VGPU11_VOSEL_SHIFT 0
+#define MT6359_DA_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_DBG1
+#define MT6359_RG_BUCK_VGPU11_VOSEL_ADDR MT6359_BUCK_VGPU11_ELR0
+#define MT6359_RG_BUCK_VGPU11_VOSEL_MASK 0x7F
+#define MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT 0
+#define MT6359_RG_BUCK_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_CON0
+#define MT6359_RG_BUCK_VMODEM_LP_ADDR MT6359_BUCK_VMODEM_CON0
+#define MT6359_RG_BUCK_VMODEM_LP_SHIFT 1
+#define MT6359_DA_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_DBG0
+#define MT6359_DA_VMODEM_VOSEL_MASK 0x7F
+#define MT6359_DA_VMODEM_VOSEL_SHIFT 0
+#define MT6359_DA_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_DBG1
+#define MT6359_RG_BUCK_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_ELR0
+#define MT6359_RG_BUCK_VMODEM_VOSEL_MASK 0x7F
+#define MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT 0
+#define MT6359_RG_BUCK_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_CON0
+#define MT6359_RG_BUCK_VPROC1_LP_ADDR MT6359_BUCK_VPROC1_CON0
+#define MT6359_RG_BUCK_VPROC1_LP_SHIFT 1
+#define MT6359_DA_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_DBG0
+#define MT6359_DA_VPROC1_VOSEL_MASK 0x7F
+#define MT6359_DA_VPROC1_VOSEL_SHIFT 0
+#define MT6359_DA_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_DBG1
+#define MT6359_RG_BUCK_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_ELR0
+#define MT6359_RG_BUCK_VPROC1_VOSEL_MASK 0x7F
+#define MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT 0
+#define MT6359_RG_BUCK_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_CON0
+#define MT6359_RG_BUCK_VPROC2_LP_ADDR MT6359_BUCK_VPROC2_CON0
+#define MT6359_RG_BUCK_VPROC2_LP_SHIFT 1
+#define MT6359_DA_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_DBG0
+#define MT6359_DA_VPROC2_VOSEL_MASK 0x7F
+#define MT6359_DA_VPROC2_VOSEL_SHIFT 0
+#define MT6359_DA_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_DBG1
+#define MT6359_RG_BUCK_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_ELR0
+#define MT6359_RG_BUCK_VPROC2_VOSEL_MASK 0x7F
+#define MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT 0
+#define MT6359_RG_BUCK_VS1_EN_ADDR MT6359_BUCK_VS1_CON0
+#define MT6359_RG_BUCK_VS1_LP_ADDR MT6359_BUCK_VS1_CON0
+#define MT6359_RG_BUCK_VS1_LP_SHIFT 1
+#define MT6359_DA_VS1_VOSEL_ADDR MT6359_BUCK_VS1_DBG0
+#define MT6359_DA_VS1_VOSEL_MASK 0x7F
+#define MT6359_DA_VS1_VOSEL_SHIFT 0
+#define MT6359_DA_VS1_EN_ADDR MT6359_BUCK_VS1_DBG1
+#define MT6359_RG_BUCK_VS1_VOSEL_ADDR MT6359_BUCK_VS1_ELR0
+#define MT6359_RG_BUCK_VS1_VOSEL_MASK 0x7F
+#define MT6359_RG_BUCK_VS1_VOSEL_SHIFT 0
+#define MT6359_RG_BUCK_VS2_EN_ADDR MT6359_BUCK_VS2_CON0
+#define MT6359_RG_BUCK_VS2_LP_ADDR MT6359_BUCK_VS2_CON0
+#define MT6359_RG_BUCK_VS2_LP_SHIFT 1
+#define MT6359_DA_VS2_VOSEL_ADDR MT6359_BUCK_VS2_DBG0
+#define MT6359_DA_VS2_VOSEL_MASK 0x7F
+#define MT6359_DA_VS2_VOSEL_SHIFT 0
+#define MT6359_DA_VS2_EN_ADDR MT6359_BUCK_VS2_DBG1
+#define MT6359_RG_BUCK_VS2_VOSEL_ADDR MT6359_BUCK_VS2_ELR0
+#define MT6359_RG_BUCK_VS2_VOSEL_MASK 0x7F
+#define MT6359_RG_BUCK_VS2_VOSEL_SHIFT 0
+#define MT6359_RG_BUCK_VPA_EN_ADDR MT6359_BUCK_VPA_CON0
+#define MT6359_RG_BUCK_VPA_LP_ADDR MT6359_BUCK_VPA_CON0
+#define MT6359_RG_BUCK_VPA_LP_SHIFT 1
+#define MT6359_RG_BUCK_VPA_VOSEL_ADDR MT6359_BUCK_VPA_CON1
+#define MT6359_RG_BUCK_VPA_VOSEL_MASK 0x3F
+#define MT6359_RG_BUCK_VPA_VOSEL_SHIFT 0
+#define MT6359_DA_VPA_VOSEL_ADDR MT6359_BUCK_VPA_DBG0
+#define MT6359_DA_VPA_VOSEL_MASK 0x3F
+#define MT6359_DA_VPA_VOSEL_SHIFT 0
+#define MT6359_DA_VPA_EN_ADDR MT6359_BUCK_VPA_DBG1
+#define MT6359_RG_VGPU11_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON2
+#define MT6359_RG_VGPU11_FCCM_SHIFT 9
+#define MT6359_RG_VCORE_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON13
+#define MT6359_RG_VCORE_FCCM_SHIFT 5
+#define MT6359_RG_VPROC1_FCCM_ADDR MT6359_VPROC1_ANA_CON3
+#define MT6359_RG_VPROC1_FCCM_SHIFT 1
+#define MT6359_RG_VPROC2_FCCM_ADDR MT6359_VPROC2_ANA_CON3
+#define MT6359_RG_VPROC2_FCCM_SHIFT 1
+#define MT6359_RG_VMODEM_FCCM_ADDR MT6359_VMODEM_ANA_CON3
+#define MT6359_RG_VMODEM_FCCM_SHIFT 1
+#define MT6359_RG_VPU_FCCM_ADDR MT6359_VPU_ANA_CON3
+#define MT6359_RG_VPU_FCCM_SHIFT 1
+#define MT6359_RG_VS1_FPWM_ADDR MT6359_VS1_ANA_CON0
+#define MT6359_RG_VS1_FPWM_SHIFT 3
+#define MT6359_RG_VS2_FPWM_ADDR MT6359_VS2_ANA_CON0
+#define MT6359_RG_VS2_FPWM_SHIFT 3
+#define MT6359_RG_VPA_MODESET_ADDR MT6359_VPA_ANA_CON0
+#define MT6359_RG_VPA_MODESET_SHIFT 1
+#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_ADDR MT6359_LDO_VSRAM_PROC1_ELR
+#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK 0x7F
+#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT 0
+#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_ADDR MT6359_LDO_VSRAM_PROC2_ELR
+#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK 0x7F
+#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT 0
+#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_ELR
+#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F
+#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT 0
+#define MT6359_RG_LDO_VSRAM_MD_VOSEL_ADDR MT6359_LDO_VSRAM_MD_ELR
+#define MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK 0x7F
+#define MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT 0
+#define MT6359_RG_LDO_VFE28_EN_ADDR MT6359_LDO_VFE28_CON0
+#define MT6359_DA_VFE28_B_EN_ADDR MT6359_LDO_VFE28_MON
+#define MT6359_RG_LDO_VXO22_EN_ADDR MT6359_LDO_VXO22_CON0
+#define MT6359_RG_LDO_VXO22_EN_SHIFT 0
+#define MT6359_DA_VXO22_B_EN_ADDR MT6359_LDO_VXO22_MON
+#define MT6359_RG_LDO_VRF18_EN_ADDR MT6359_LDO_VRF18_CON0
+#define MT6359_RG_LDO_VRF18_EN_SHIFT 0
+#define MT6359_DA_VRF18_B_EN_ADDR MT6359_LDO_VRF18_MON
+#define MT6359_RG_LDO_VRF12_EN_ADDR MT6359_LDO_VRF12_CON0
+#define MT6359_RG_LDO_VRF12_EN_SHIFT 0
+#define MT6359_DA_VRF12_B_EN_ADDR MT6359_LDO_VRF12_MON
+#define MT6359_RG_LDO_VEFUSE_EN_ADDR MT6359_LDO_VEFUSE_CON0
+#define MT6359_RG_LDO_VEFUSE_EN_SHIFT 0
+#define MT6359_DA_VEFUSE_B_EN_ADDR MT6359_LDO_VEFUSE_MON
+#define MT6359_RG_LDO_VCN33_1_EN_0_ADDR MT6359_LDO_VCN33_1_CON0
+#define MT6359_RG_LDO_VCN33_1_EN_0_MASK 0x1
+#define MT6359_RG_LDO_VCN33_1_EN_0_SHIFT 0
+#define MT6359_DA_VCN33_1_B_EN_ADDR MT6359_LDO_VCN33_1_MON
+#define MT6359_RG_LDO_VCN33_1_EN_1_ADDR MT6359_LDO_VCN33_1_MULTI_SW
+#define MT6359_RG_LDO_VCN33_1_EN_1_SHIFT 15
+#define MT6359_RG_LDO_VCN33_2_EN_0_ADDR MT6359_LDO_VCN33_2_CON0
+#define MT6359_RG_LDO_VCN33_2_EN_0_SHIFT 0
+#define MT6359_DA_VCN33_2_B_EN_ADDR MT6359_LDO_VCN33_2_MON
+#define MT6359_RG_LDO_VCN33_2_EN_1_ADDR MT6359_LDO_VCN33_2_MULTI_SW
+#define MT6359_RG_LDO_VCN33_2_EN_1_MASK 0x1
+#define MT6359_RG_LDO_VCN33_2_EN_1_SHIFT 15
+#define MT6359_RG_LDO_VCN13_EN_ADDR MT6359_LDO_VCN13_CON0
+#define MT6359_RG_LDO_VCN13_EN_SHIFT 0
+#define MT6359_DA_VCN13_B_EN_ADDR MT6359_LDO_VCN13_MON
+#define MT6359_RG_LDO_VCN18_EN_ADDR MT6359_LDO_VCN18_CON0
+#define MT6359_DA_VCN18_B_EN_ADDR MT6359_LDO_VCN18_MON
+#define MT6359_RG_LDO_VA09_EN_ADDR MT6359_LDO_VA09_CON0
+#define MT6359_RG_LDO_VA09_EN_SHIFT 0
+#define MT6359_DA_VA09_B_EN_ADDR MT6359_LDO_VA09_MON
+#define MT6359_RG_LDO_VCAMIO_EN_ADDR MT6359_LDO_VCAMIO_CON0
+#define MT6359_RG_LDO_VCAMIO_EN_SHIFT 0
+#define MT6359_DA_VCAMIO_B_EN_ADDR MT6359_LDO_VCAMIO_MON
+#define MT6359_RG_LDO_VA12_EN_ADDR MT6359_LDO_VA12_CON0
+#define MT6359_RG_LDO_VA12_EN_SHIFT 0
+#define MT6359_DA_VA12_B_EN_ADDR MT6359_LDO_VA12_MON
+#define MT6359_RG_LDO_VAUX18_EN_ADDR MT6359_LDO_VAUX18_CON0
+#define MT6359_DA_VAUX18_B_EN_ADDR MT6359_LDO_VAUX18_MON
+#define MT6359_RG_LDO_VAUD18_EN_ADDR MT6359_LDO_VAUD18_CON0
+#define MT6359_DA_VAUD18_B_EN_ADDR MT6359_LDO_VAUD18_MON
+#define MT6359_RG_LDO_VIO18_EN_ADDR MT6359_LDO_VIO18_CON0
+#define MT6359_RG_LDO_VIO18_EN_SHIFT 0
+#define MT6359_DA_VIO18_B_EN_ADDR MT6359_LDO_VIO18_MON
+#define MT6359_RG_LDO_VEMC_EN_ADDR MT6359_LDO_VEMC_CON0
+#define MT6359_RG_LDO_VEMC_EN_SHIFT 0
+#define MT6359_DA_VEMC_B_EN_ADDR MT6359_LDO_VEMC_MON
+#define MT6359_RG_LDO_VSIM1_EN_ADDR MT6359_LDO_VSIM1_CON0
+#define MT6359_RG_LDO_VSIM1_EN_SHIFT 0
+#define MT6359_DA_VSIM1_B_EN_ADDR MT6359_LDO_VSIM1_MON
+#define MT6359_RG_LDO_VSIM2_EN_ADDR MT6359_LDO_VSIM2_CON0
+#define MT6359_RG_LDO_VSIM2_EN_SHIFT 0
+#define MT6359_DA_VSIM2_B_EN_ADDR MT6359_LDO_VSIM2_MON
+#define MT6359_RG_LDO_VUSB_EN_0_ADDR MT6359_LDO_VUSB_CON0
+#define MT6359_RG_LDO_VUSB_EN_0_MASK 0x1
+#define MT6359_RG_LDO_VUSB_EN_0_SHIFT 0
+#define MT6359_DA_VUSB_B_EN_ADDR MT6359_LDO_VUSB_MON
+#define MT6359_RG_LDO_VUSB_EN_1_ADDR MT6359_LDO_VUSB_MULTI_SW
+#define MT6359_RG_LDO_VUSB_EN_1_MASK 0x1
+#define MT6359_RG_LDO_VUSB_EN_1_SHIFT 15
+#define MT6359_RG_LDO_VRFCK_EN_ADDR MT6359_LDO_VRFCK_CON0
+#define MT6359_RG_LDO_VRFCK_EN_SHIFT 0
+#define MT6359_DA_VRFCK_B_EN_ADDR MT6359_LDO_VRFCK_MON
+#define MT6359_RG_LDO_VBBCK_EN_ADDR MT6359_LDO_VBBCK_CON0
+#define MT6359_RG_LDO_VBBCK_EN_SHIFT 0
+#define MT6359_DA_VBBCK_B_EN_ADDR MT6359_LDO_VBBCK_MON
+#define MT6359_RG_LDO_VBIF28_EN_ADDR MT6359_LDO_VBIF28_CON0
+#define MT6359_DA_VBIF28_B_EN_ADDR MT6359_LDO_VBIF28_MON
+#define MT6359_RG_LDO_VIBR_EN_ADDR MT6359_LDO_VIBR_CON0
+#define MT6359_RG_LDO_VIBR_EN_SHIFT 0
+#define MT6359_DA_VIBR_B_EN_ADDR MT6359_LDO_VIBR_MON
+#define MT6359_RG_LDO_VIO28_EN_ADDR MT6359_LDO_VIO28_CON0
+#define MT6359_RG_LDO_VIO28_EN_SHIFT 0
+#define MT6359_DA_VIO28_B_EN_ADDR MT6359_LDO_VIO28_MON
+#define MT6359_RG_LDO_VM18_EN_ADDR MT6359_LDO_VM18_CON0
+#define MT6359_RG_LDO_VM18_EN_SHIFT 0
+#define MT6359_DA_VM18_B_EN_ADDR MT6359_LDO_VM18_MON
+#define MT6359_RG_LDO_VUFS_EN_ADDR MT6359_LDO_VUFS_CON0
+#define MT6359_RG_LDO_VUFS_EN_SHIFT 0
+#define MT6359_DA_VUFS_B_EN_ADDR MT6359_LDO_VUFS_MON
+#define MT6359_RG_LDO_VSRAM_PROC1_EN_ADDR MT6359_LDO_VSRAM_PROC1_CON0
+#define MT6359_DA_VSRAM_PROC1_B_EN_ADDR MT6359_LDO_VSRAM_PROC1_MON
+#define MT6359_DA_VSRAM_PROC1_VOSEL_ADDR MT6359_LDO_VSRAM_PROC1_VOSEL1
+#define MT6359_DA_VSRAM_PROC1_VOSEL_MASK 0x7F
+#define MT6359_DA_VSRAM_PROC1_VOSEL_SHIFT 8
+#define MT6359_RG_LDO_VSRAM_PROC2_EN_ADDR MT6359_LDO_VSRAM_PROC2_CON0
+#define MT6359_DA_VSRAM_PROC2_B_EN_ADDR MT6359_LDO_VSRAM_PROC2_MON
+#define MT6359_DA_VSRAM_PROC2_VOSEL_ADDR MT6359_LDO_VSRAM_PROC2_VOSEL1
+#define MT6359_DA_VSRAM_PROC2_VOSEL_MASK 0x7F
+#define MT6359_DA_VSRAM_PROC2_VOSEL_SHIFT 8
+#define MT6359_RG_LDO_VSRAM_OTHERS_EN_ADDR MT6359_LDO_VSRAM_OTHERS_CON0
+#define MT6359_DA_VSRAM_OTHERS_B_EN_ADDR MT6359_LDO_VSRAM_OTHERS_MON
+#define MT6359_DA_VSRAM_OTHERS_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_VOSEL1
+#define MT6359_DA_VSRAM_OTHERS_VOSEL_MASK 0x7F
+#define MT6359_DA_VSRAM_OTHERS_VOSEL_SHIFT 8
+#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR \
+ MT6359_LDO_VSRAM_OTHERS_SSHUB
+#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR \
+ MT6359_LDO_VSRAM_OTHERS_SSHUB
+#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F
+#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT 1
+#define MT6359_RG_LDO_VSRAM_MD_EN_ADDR MT6359_LDO_VSRAM_MD_CON0
+#define MT6359_DA_VSRAM_MD_B_EN_ADDR MT6359_LDO_VSRAM_MD_MON
+#define MT6359_DA_VSRAM_MD_VOSEL_ADDR MT6359_LDO_VSRAM_MD_VOSEL1
+#define MT6359_DA_VSRAM_MD_VOSEL_MASK 0x7F
+#define MT6359_DA_VSRAM_MD_VOSEL_SHIFT 8
+#define MT6359_RG_VCN33_1_VOSEL_ADDR MT6359_VCN33_1_ANA_CON0
+#define MT6359_RG_VCN33_1_VOSEL_MASK 0xF
+#define MT6359_RG_VCN33_1_VOSEL_SHIFT 8
+#define MT6359_RG_VCN33_2_VOSEL_ADDR MT6359_VCN33_2_ANA_CON0
+#define MT6359_RG_VCN33_2_VOSEL_MASK 0xF
+#define MT6359_RG_VCN33_2_VOSEL_SHIFT 8
+#define MT6359_RG_VEMC_VOSEL_ADDR MT6359_VEMC_ANA_CON0
+#define MT6359_RG_VEMC_VOSEL_MASK 0xF
+#define MT6359_RG_VEMC_VOSEL_SHIFT 8
+#define MT6359_RG_VSIM1_VOSEL_ADDR MT6359_VSIM1_ANA_CON0
+#define MT6359_RG_VSIM1_VOSEL_MASK 0xF
+#define MT6359_RG_VSIM1_VOSEL_SHIFT 8
+#define MT6359_RG_VSIM2_VOSEL_ADDR MT6359_VSIM2_ANA_CON0
+#define MT6359_RG_VSIM2_VOSEL_MASK 0xF
+#define MT6359_RG_VSIM2_VOSEL_SHIFT 8
+#define MT6359_RG_VIO28_VOSEL_ADDR MT6359_VIO28_ANA_CON0
+#define MT6359_RG_VIO28_VOSEL_MASK 0xF
+#define MT6359_RG_VIO28_VOSEL_SHIFT 8
+#define MT6359_RG_VIBR_VOSEL_ADDR MT6359_VIBR_ANA_CON0
+#define MT6359_RG_VIBR_VOSEL_MASK 0xF
+#define MT6359_RG_VIBR_VOSEL_SHIFT 8
+#define MT6359_RG_VRF18_VOSEL_ADDR MT6359_VRF18_ANA_CON0
+#define MT6359_RG_VRF18_VOSEL_MASK 0xF
+#define MT6359_RG_VRF18_VOSEL_SHIFT 8
+#define MT6359_RG_VEFUSE_VOSEL_ADDR MT6359_VEFUSE_ANA_CON0
+#define MT6359_RG_VEFUSE_VOSEL_MASK 0xF
+#define MT6359_RG_VEFUSE_VOSEL_SHIFT 8
+#define MT6359_RG_VCAMIO_VOSEL_ADDR MT6359_VCAMIO_ANA_CON0
+#define MT6359_RG_VCAMIO_VOSEL_MASK 0xF
+#define MT6359_RG_VCAMIO_VOSEL_SHIFT 8
+#define MT6359_RG_VIO18_VOSEL_ADDR MT6359_VIO18_ANA_CON0
+#define MT6359_RG_VIO18_VOSEL_MASK 0xF
+#define MT6359_RG_VIO18_VOSEL_SHIFT 8
+#define MT6359_RG_VM18_VOSEL_ADDR MT6359_VM18_ANA_CON0
+#define MT6359_RG_VM18_VOSEL_MASK 0xF
+#define MT6359_RG_VM18_VOSEL_SHIFT 8
+#define MT6359_RG_VUFS_VOSEL_ADDR MT6359_VUFS_ANA_CON0
+#define MT6359_RG_VUFS_VOSEL_MASK 0xF
+#define MT6359_RG_VUFS_VOSEL_SHIFT 8
+#define MT6359_RG_VRF12_VOSEL_ADDR MT6359_VRF12_ANA_CON0
+#define MT6359_RG_VRF12_VOSEL_MASK 0xF
+#define MT6359_RG_VRF12_VOSEL_SHIFT 8
+#define MT6359_RG_VCN13_VOSEL_ADDR MT6359_VCN13_ANA_CON0
+#define MT6359_RG_VCN13_VOSEL_MASK 0xF
+#define MT6359_RG_VCN13_VOSEL_SHIFT 8
+#define MT6359_RG_VA09_VOSEL_ADDR MT6359_VA09_ANA_CON0
+#define MT6359_RG_VA09_VOSEL_MASK 0xF
+#define MT6359_RG_VA09_VOSEL_SHIFT 8
+#define MT6359_RG_VA12_VOSEL_ADDR MT6359_VA12_ANA_CON0
+#define MT6359_RG_VA12_VOSEL_MASK 0xF
+#define MT6359_RG_VA12_VOSEL_SHIFT 8
+#define MT6359_RG_VXO22_VOSEL_ADDR MT6359_VXO22_ANA_CON0
+#define MT6359_RG_VXO22_VOSEL_MASK 0xF
+#define MT6359_RG_VXO22_VOSEL_SHIFT 8
+#define MT6359_RG_VRFCK_VOSEL_ADDR MT6359_VRFCK_ANA_CON0
+#define MT6359_RG_VRFCK_VOSEL_MASK 0xF
+#define MT6359_RG_VRFCK_VOSEL_SHIFT 8
+#define MT6359_RG_VBBCK_VOSEL_ADDR MT6359_VBBCK_ANA_CON0
+#define MT6359_RG_VBBCK_VOSEL_MASK 0xF
+#define MT6359_RG_VBBCK_VOSEL_SHIFT 8
+
+#endif /* __MFD_MT6359_REGISTERS_H__ */
--
1.9.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* [RESEND v2 3/4] regulator: mt6359: Add support for MT6359 regulator
2020-02-21 2:39 [RESEND v2 0/4] Add Support for MediaTek PMIC MT6359 Regulator Wen Su
2020-02-21 2:39 ` [RESEND v2 1/4] dt-bindings: regulator: Add document for MT6359 regulator Wen Su
2020-02-21 2:39 ` [RESEND v2 2/4] mfd: Add for PMIC MT6359 registers definition Wen Su
@ 2020-02-21 2:39 ` Wen Su
2020-02-21 2:39 ` [RESEND v2 4/4] arm64: dts: mt6359: add PMIC MT6359 related nodes Wen Su
3 siblings, 0 replies; 7+ messages in thread
From: Wen Su @ 2020-02-21 2:39 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger
Cc: Mark Rutland, devicetree, wen.su, wsd_upstream, linux-kernel,
Liam Girdwood, linux-mediatek, linux-arm-kernel
From: "Wen Su" <wen.su@mediatek.com>
The MT6359 is a regulator found on boards based on MediaTek MT6779 and
probably other SoCs. It is a so called pmic and connects as a slave to
SoC using SPI, wrapped inside the pmic-wrapper.
Signed-off-by: Wen Su <wen.su@mediatek.com>
---
drivers/regulator/Kconfig | 9 +
drivers/regulator/Makefile | 1 +
drivers/regulator/mt6359-regulator.c | 738 +++++++++++++++++++++++++++++
include/linux/regulator/mt6359-regulator.h | 58 +++
4 files changed, 806 insertions(+)
create mode 100644 drivers/regulator/mt6359-regulator.c
create mode 100644 include/linux/regulator/mt6359-regulator.h
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 74eb5af..0e74c66 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -628,6 +628,15 @@ config REGULATOR_MT6358
This driver supports the control of different power rails of device
through regulator interface.
+config REGULATOR_MT6359
+ tristate "MediaTek MT6359 PMIC"
+ depends on MFD_MT6397
+ help
+ Say y here to select this option to enable the power regulator of
+ MediaTek MT6359 PMIC.
+ This driver supports the control of different power rails of device
+ through regulator interface.
+
config REGULATOR_MT6380
tristate "MediaTek MT6380 PMIC"
depends on MTK_PMIC_WRAP
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 2210ba5..103d35f 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -80,6 +80,7 @@ obj-$(CONFIG_REGULATOR_MCP16502) += mcp16502.o
obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o
obj-$(CONFIG_REGULATOR_MT6323) += mt6323-regulator.o
obj-$(CONFIG_REGULATOR_MT6358) += mt6358-regulator.o
+obj-$(CONFIG_REGULATOR_MT6359) += mt6359-regulator.o
obj-$(CONFIG_REGULATOR_MT6380) += mt6380-regulator.o
obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o
obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o
diff --git a/drivers/regulator/mt6359-regulator.c b/drivers/regulator/mt6359-regulator.c
new file mode 100644
index 0000000..d64bc7b
--- /dev/null
+++ b/drivers/regulator/mt6359-regulator.c
@@ -0,0 +1,738 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2019 MediaTek Inc.
+
+#include <linux/platform_device.h>
+#include <linux/mfd/mt6359/registers.h>
+#include <linux/mfd/mt6397/core.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/mt6359-regulator.h>
+#include <linux/regulator/of_regulator.h>
+
+#define MT6359_BUCK_MODE_AUTO 0
+#define MT6359_BUCK_MODE_FORCE_PWM 1
+#define MT6359_BUCK_MODE_NORMAL 0
+#define MT6359_BUCK_MODE_LP 2
+
+/*
+ * MT6359 regulators' information
+ *
+ * @desc: standard fields of regulator description.
+ * @status_reg: for query status of regulators.
+ * @qi: Mask for query enable signal status of regulators.
+ * @modeset_reg: for operating AUTO/PWM mode register.
+ * @modeset_mask: MASK for operating modeset register.
+ * @modeset_shift: SHIFT for operating modeset register.
+ */
+struct mt6359_regulator_info {
+ struct regulator_desc desc;
+ u32 status_reg;
+ u32 qi;
+ u32 vsel_shift;
+ u32 da_vsel_reg;
+ u32 da_vsel_mask;
+ u32 da_vsel_shift;
+ u32 modeset_reg;
+ u32 modeset_mask;
+ u32 modeset_shift;
+ u32 lp_mode_reg;
+ u32 lp_mode_mask;
+ u32 lp_mode_shift;
+};
+
+#define MT6359_BUCK(match, _name, min, max, step, min_sel, \
+ volt_ranges, _enable_reg, _status_reg, \
+ _da_vsel_reg, _da_vsel_mask, _da_vsel_shift, \
+ _vsel_reg, _vsel_mask, \
+ _lp_mode_reg, _lp_mode_shift, \
+ _modeset_reg, _modeset_shift) \
+[MT6359_ID_##_name] = { \
+ .desc = { \
+ .name = #_name, \
+ .of_match = of_match_ptr(match), \
+ .ops = &mt6359_volt_range_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6359_ID_##_name, \
+ .owner = THIS_MODULE, \
+ .uV_step = (step), \
+ .linear_min_sel = (min_sel), \
+ .n_voltages = ((max) - (min)) / (step) + 1, \
+ .min_uV = (min), \
+ .linear_ranges = volt_ranges, \
+ .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
+ .vsel_reg = _vsel_reg, \
+ .vsel_mask = _vsel_mask, \
+ .enable_reg = _enable_reg, \
+ .enable_mask = BIT(0), \
+ .of_map_mode = mt6359_map_mode, \
+ }, \
+ .da_vsel_reg = _da_vsel_reg, \
+ .da_vsel_mask = _da_vsel_mask, \
+ .da_vsel_shift = _da_vsel_shift, \
+ .status_reg = _status_reg, \
+ .qi = BIT(0), \
+ .lp_mode_reg = _lp_mode_reg, \
+ .lp_mode_mask = BIT(_lp_mode_shift), \
+ .lp_mode_shift = _lp_mode_shift, \
+ .modeset_reg = _modeset_reg, \
+ .modeset_mask = BIT(_modeset_shift), \
+ .modeset_shift = _modeset_shift \
+}
+
+#define MT6359_LDO_LINEAR(match, _name, min, max, step, min_sel,\
+ volt_ranges, _enable_reg, _status_reg, \
+ _da_vsel_reg, _da_vsel_mask, _da_vsel_shift, \
+ _vsel_reg, _vsel_mask) \
+[MT6359_ID_##_name] = { \
+ .desc = { \
+ .name = #_name, \
+ .of_match = of_match_ptr(match), \
+ .ops = &mt6359_volt_range_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6359_ID_##_name, \
+ .owner = THIS_MODULE, \
+ .uV_step = (step), \
+ .linear_min_sel = (min_sel), \
+ .n_voltages = ((max) - (min)) / (step) + 1, \
+ .min_uV = (min), \
+ .linear_ranges = volt_ranges, \
+ .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
+ .vsel_reg = _vsel_reg, \
+ .vsel_mask = _vsel_mask, \
+ .enable_reg = _enable_reg, \
+ .enable_mask = BIT(0), \
+ }, \
+ .da_vsel_reg = _da_vsel_reg, \
+ .da_vsel_mask = _da_vsel_mask, \
+ .da_vsel_shift = _da_vsel_shift, \
+ .status_reg = _status_reg, \
+ .qi = BIT(0), \
+}
+
+#define MT6359_LDO(match, _name, _volt_table, \
+ _enable_reg, _enable_mask, _status_reg, \
+ _vsel_reg, _vsel_mask, _vsel_shift) \
+[MT6359_ID_##_name] = { \
+ .desc = { \
+ .name = #_name, \
+ .of_match = of_match_ptr(match), \
+ .ops = &mt6359_volt_table_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6359_ID_##_name, \
+ .owner = THIS_MODULE, \
+ .n_voltages = ARRAY_SIZE(_volt_table), \
+ .volt_table = _volt_table, \
+ .vsel_reg = _vsel_reg, \
+ .vsel_mask = _vsel_mask, \
+ .enable_reg = _enable_reg, \
+ .enable_mask = BIT(_enable_mask), \
+ }, \
+ .status_reg = _status_reg, \
+ .qi = BIT(0), \
+ .vsel_shift = _vsel_shift, \
+}
+
+#define MT6359_REG_FIXED(match, _name, _enable_reg, \
+ _status_reg, _fixed_volt) \
+[MT6359_ID_##_name] = { \
+ .desc = { \
+ .name = #_name, \
+ .of_match = of_match_ptr(match), \
+ .ops = &mt6359_volt_fixed_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6359_ID_##_name, \
+ .owner = THIS_MODULE, \
+ .n_voltages = 1, \
+ .enable_reg = _enable_reg, \
+ .enable_mask = BIT(0), \
+ .fixed_uV = (_fixed_volt), \
+ }, \
+ .status_reg = _status_reg, \
+ .qi = BIT(0), \
+}
+
+static const struct regulator_linear_range mt_volt_range1[] = {
+ REGULATOR_LINEAR_RANGE(800000, 0, 0x70, 12500),
+};
+
+static const struct regulator_linear_range mt_volt_range2[] = {
+ REGULATOR_LINEAR_RANGE(400000, 0, 0x7f, 6250),
+};
+
+static const struct regulator_linear_range mt_volt_range3[] = {
+ REGULATOR_LINEAR_RANGE(400000, 0, 0x70, 6250),
+};
+
+static const struct regulator_linear_range mt_volt_range4[] = {
+ REGULATOR_LINEAR_RANGE(800000, 0, 0x40, 12500),
+};
+
+static const struct regulator_linear_range mt_volt_range5[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0, 0x3F, 50000),
+};
+
+static const struct regulator_linear_range mt_volt_range6[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0, 0x6f, 6250),
+};
+
+static const struct regulator_linear_range mt_volt_range7[] = {
+ REGULATOR_LINEAR_RANGE(500000, 0, 0x60, 6250),
+};
+
+static const u32 vsim1_voltages[] = {
+ 0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000,
+};
+
+static const u32 vibr_voltages[] = {
+ 1200000, 1300000, 1500000, 0, 1800000, 2000000, 0, 0, 2700000, 2800000,
+ 0, 3000000, 0, 3300000,
+};
+
+static const u32 vrf12_voltages[] = {
+ 0, 0, 1100000, 1200000, 1300000,
+};
+
+static const u32 volt18_voltages[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000,
+};
+
+static const u32 vcn13_voltages[] = {
+ 900000, 1000000, 0, 1200000, 1300000,
+};
+
+static const u32 vcn33_voltages[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 0, 0, 0, 3300000, 3400000, 3500000,
+};
+
+static const u32 vefuse_voltages[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000, 2000000,
+};
+
+static const u32 vxo22_voltages[] = {
+ 1800000, 0, 0, 0, 2200000,
+};
+
+static const u32 vrfck_voltages[] = {
+ 0, 0, 1500000, 0, 0, 0, 0, 1600000, 0, 0, 0, 0, 1700000,
+};
+
+static const u32 vio28_voltages[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 2900000, 3000000, 3100000, 3300000,
+};
+
+static const u32 vemc_voltages[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2900000, 3000000, 0, 3300000,
+};
+
+static const u32 va12_voltages[] = {
+ 0, 0, 0, 0, 0, 0, 1200000, 1300000,
+};
+
+static const u32 va09_voltages[] = {
+ 0, 0, 800000, 900000, 0, 0, 1200000,
+};
+
+static const u32 vrf18_voltages[] = {
+ 0, 0, 0, 0, 0, 1700000, 1800000, 1810000,
+};
+
+static const u32 vbbck_voltages[] = {
+ 0, 0, 0, 0, 1100000, 0, 0, 0, 1150000, 0, 0, 0, 1200000,
+};
+
+static const u32 vsim2_voltages[] = {
+ 0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000,
+};
+
+static inline unsigned int mt6359_map_mode(unsigned int mode)
+{
+ switch (mode) {
+ case MT6359_BUCK_MODE_NORMAL:
+ return REGULATOR_MODE_NORMAL;
+ case MT6359_BUCK_MODE_FORCE_PWM:
+ return REGULATOR_MODE_FAST;
+ case MT6359_BUCK_MODE_LP:
+ return REGULATOR_MODE_IDLE;
+ default:
+ return REGULATOR_MODE_INVALID;
+ }
+}
+
+static int mt6359_get_linear_voltage_sel(struct regulator_dev *rdev)
+{
+ struct mt6359_regulator_info *info = rdev_get_drvdata(rdev);
+ int ret, regval;
+
+ ret = regmap_read(rdev->regmap, info->da_vsel_reg, ®val);
+ if (ret != 0) {
+ dev_err(&rdev->dev,
+ "Failed to get mt6359 Buck %s vsel reg: %d\n",
+ info->desc.name, ret);
+ return ret;
+ }
+
+ ret = (regval >> info->da_vsel_shift) & info->da_vsel_mask;
+
+ return ret;
+}
+
+static int mt6359_get_status(struct regulator_dev *rdev)
+{
+ int ret;
+ u32 regval;
+ struct mt6359_regulator_info *info = rdev_get_drvdata(rdev);
+
+ ret = regmap_read(rdev->regmap, info->status_reg, ®val);
+ if (ret != 0) {
+ dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret);
+ return ret;
+ }
+
+ if (regval & info->qi)
+ return REGULATOR_STATUS_ON;
+ else
+ return REGULATOR_STATUS_OFF;
+}
+
+static unsigned int mt6359_regulator_get_mode(struct regulator_dev *rdev)
+{
+ struct mt6359_regulator_info *info = rdev_get_drvdata(rdev);
+ int ret, regval;
+
+ ret = regmap_read(rdev->regmap, info->modeset_reg, ®val);
+ if (ret != 0) {
+ dev_err(&rdev->dev,
+ "Failed to get mt6359 buck mode: %d\n", ret);
+ return ret;
+ }
+
+ if ((regval & info->modeset_mask) >> info->modeset_shift ==
+ MT6359_BUCK_MODE_FORCE_PWM)
+ return REGULATOR_MODE_FAST;
+
+ ret = regmap_read(rdev->regmap, info->lp_mode_reg, ®val);
+ if (ret != 0) {
+ dev_err(&rdev->dev,
+ "Failed to get mt6359 buck lp mode: %d\n", ret);
+ return ret;
+ }
+
+ if (regval & info->lp_mode_mask)
+ return REGULATOR_MODE_IDLE;
+ else
+ return REGULATOR_MODE_NORMAL;
+}
+
+static int mt6359_regulator_set_mode(struct regulator_dev *rdev,
+ unsigned int mode)
+{
+ struct mt6359_regulator_info *info = rdev_get_drvdata(rdev);
+ int ret = 0, val;
+ int curr_mode;
+
+ curr_mode = mt6359_regulator_get_mode(rdev);
+ switch (mode) {
+ case REGULATOR_MODE_FAST:
+ val = MT6359_BUCK_MODE_FORCE_PWM;
+ val <<= info->modeset_shift;
+ ret = regmap_update_bits(rdev->regmap,
+ info->modeset_reg,
+ info->modeset_mask,
+ val);
+ break;
+ case REGULATOR_MODE_NORMAL:
+ if (curr_mode == REGULATOR_MODE_FAST) {
+ val = MT6359_BUCK_MODE_AUTO;
+ val <<= info->modeset_shift;
+ ret = regmap_update_bits(rdev->regmap,
+ info->modeset_reg,
+ info->modeset_mask,
+ val);
+ } else if (curr_mode == REGULATOR_MODE_IDLE) {
+ val = MT6359_BUCK_MODE_NORMAL;
+ val <<= info->lp_mode_shift;
+ ret = regmap_update_bits(rdev->regmap,
+ info->lp_mode_reg,
+ info->lp_mode_mask,
+ val);
+ udelay(100);
+ }
+ break;
+ case REGULATOR_MODE_IDLE:
+ val = MT6359_BUCK_MODE_LP >> 1;
+ val <<= info->lp_mode_shift;
+ ret = regmap_update_bits(rdev->regmap,
+ info->lp_mode_reg,
+ info->lp_mode_mask,
+ val);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (ret != 0) {
+ dev_err(&rdev->dev,
+ "Failed to set mt6359 buck mode: %d\n", ret);
+ }
+
+ return ret;
+}
+
+static const struct regulator_ops mt6359_volt_range_ops = {
+ .list_voltage = regulator_list_voltage_linear_range,
+ .map_voltage = regulator_map_voltage_linear_range,
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .get_voltage_sel = mt6359_get_linear_voltage_sel,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .get_status = mt6359_get_status,
+ .set_mode = mt6359_regulator_set_mode,
+ .get_mode = mt6359_regulator_get_mode,
+};
+
+static const struct regulator_ops mt6359_volt_table_ops = {
+ .list_voltage = regulator_list_voltage_table,
+ .map_voltage = regulator_map_voltage_iterate,
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .get_status = mt6359_get_status,
+};
+
+static const struct regulator_ops mt6359_volt_fixed_ops = {
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .get_status = mt6359_get_status,
+};
+
+/* The array is indexed by id(MT6359_ID_XXX) */
+static struct mt6359_regulator_info mt6359_regulators[] = {
+ MT6359_BUCK("buck_vs1", VS1, 800000, 2200000, 12500, 0,
+ mt_volt_range1, MT6359_RG_BUCK_VS1_EN_ADDR,
+ MT6359_DA_VS1_EN_ADDR, MT6359_DA_VS1_VOSEL_ADDR,
+ MT6359_DA_VS1_VOSEL_MASK, MT6359_DA_VS1_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VS1_VOSEL_ADDR,
+ MT6359_RG_BUCK_VS1_VOSEL_MASK <<
+ MT6359_RG_BUCK_VS1_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VS1_LP_ADDR, MT6359_RG_BUCK_VS1_LP_SHIFT,
+ MT6359_RG_VS1_FPWM_ADDR, MT6359_RG_VS1_FPWM_SHIFT),
+ MT6359_BUCK("buck_vgpu11", VGPU11, 400000, 1193750, 6250, 0,
+ mt_volt_range2, MT6359_RG_BUCK_VGPU11_EN_ADDR,
+ MT6359_DA_VGPU11_EN_ADDR, MT6359_DA_VGPU11_VOSEL_ADDR,
+ MT6359_DA_VGPU11_VOSEL_MASK, MT6359_DA_VGPU11_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VGPU11_VOSEL_ADDR,
+ MT6359_RG_BUCK_VGPU11_VOSEL_MASK <<
+ MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VGPU11_LP_ADDR,
+ MT6359_RG_BUCK_VGPU11_LP_SHIFT,
+ MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT),
+ MT6359_BUCK("buck_vmodem", VMODEM, 400000, 1100000, 6250, 0,
+ mt_volt_range3, MT6359_RG_BUCK_VMODEM_EN_ADDR,
+ MT6359_DA_VMODEM_EN_ADDR, MT6359_DA_VMODEM_VOSEL_ADDR,
+ MT6359_DA_VMODEM_VOSEL_MASK, MT6359_DA_VMODEM_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VMODEM_VOSEL_ADDR,
+ MT6359_RG_BUCK_VMODEM_VOSEL_MASK <<
+ MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VMODEM_LP_ADDR,
+ MT6359_RG_BUCK_VMODEM_LP_SHIFT,
+ MT6359_RG_VMODEM_FCCM_ADDR, MT6359_RG_VMODEM_FCCM_SHIFT),
+ MT6359_BUCK("buck_vpu", VPU, 400000, 1193750, 6250, 0,
+ mt_volt_range2, MT6359_RG_BUCK_VPU_EN_ADDR,
+ MT6359_DA_VPU_EN_ADDR, MT6359_DA_VPU_VOSEL_ADDR,
+ MT6359_DA_VPU_VOSEL_MASK, MT6359_DA_VPU_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VPU_VOSEL_ADDR,
+ MT6359_RG_BUCK_VPU_VOSEL_MASK <<
+ MT6359_RG_BUCK_VPU_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VPU_LP_ADDR, MT6359_RG_BUCK_VPU_LP_SHIFT,
+ MT6359_RG_VPU_FCCM_ADDR, MT6359_RG_VPU_FCCM_SHIFT),
+ MT6359_BUCK("buck_vcore", VCORE, 400000, 1193750, 6250, 0,
+ mt_volt_range2, MT6359_RG_BUCK_VCORE_EN_ADDR,
+ MT6359_DA_VCORE_EN_ADDR, MT6359_DA_VCORE_VOSEL_ADDR,
+ MT6359_DA_VCORE_VOSEL_MASK, MT6359_DA_VCORE_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VCORE_VOSEL_ADDR,
+ MT6359_RG_BUCK_VCORE_VOSEL_MASK <<
+ MT6359_RG_BUCK_VCORE_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT,
+ MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT),
+ MT6359_BUCK("buck_vs2", VS2, 800000, 1600000, 12500, 0,
+ mt_volt_range4, MT6359_RG_BUCK_VS2_EN_ADDR,
+ MT6359_DA_VS2_EN_ADDR, MT6359_DA_VS2_VOSEL_ADDR,
+ MT6359_DA_VS2_VOSEL_MASK, MT6359_DA_VS2_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VS2_VOSEL_ADDR,
+ MT6359_RG_BUCK_VS2_VOSEL_MASK <<
+ MT6359_RG_BUCK_VS2_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VS2_LP_ADDR, MT6359_RG_BUCK_VS2_LP_SHIFT,
+ MT6359_RG_VS2_FPWM_ADDR, MT6359_RG_VS2_FPWM_SHIFT),
+ MT6359_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, 0,
+ mt_volt_range5, MT6359_RG_BUCK_VPA_EN_ADDR,
+ MT6359_DA_VPA_EN_ADDR, MT6359_DA_VPA_VOSEL_ADDR,
+ MT6359_DA_VPA_VOSEL_MASK, MT6359_DA_VPA_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VPA_VOSEL_ADDR,
+ MT6359_RG_BUCK_VPA_VOSEL_MASK <<
+ MT6359_RG_BUCK_VPA_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VPA_LP_ADDR, MT6359_RG_BUCK_VPA_LP_SHIFT,
+ MT6359_RG_VPA_MODESET_ADDR, MT6359_RG_VPA_MODESET_SHIFT),
+ MT6359_BUCK("buck_vproc2", VPROC2, 400000, 1193750, 6250, 0,
+ mt_volt_range2, MT6359_RG_BUCK_VPROC2_EN_ADDR,
+ MT6359_DA_VPROC2_EN_ADDR, MT6359_DA_VPROC2_VOSEL_ADDR,
+ MT6359_DA_VPROC2_VOSEL_MASK, MT6359_DA_VPROC2_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VPROC2_VOSEL_ADDR,
+ MT6359_RG_BUCK_VPROC2_VOSEL_MASK <<
+ MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VPROC2_LP_ADDR,
+ MT6359_RG_BUCK_VPROC2_LP_SHIFT,
+ MT6359_RG_VPROC2_FCCM_ADDR, MT6359_RG_VPROC2_FCCM_SHIFT),
+ MT6359_BUCK("buck_vproc1", VPROC1, 400000, 1193750, 6250, 0,
+ mt_volt_range2, MT6359_RG_BUCK_VPROC1_EN_ADDR,
+ MT6359_DA_VPROC1_EN_ADDR, MT6359_DA_VPROC1_VOSEL_ADDR,
+ MT6359_DA_VPROC1_VOSEL_MASK, MT6359_DA_VPROC1_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VPROC1_VOSEL_ADDR,
+ MT6359_RG_BUCK_VPROC1_VOSEL_MASK <<
+ MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VPROC1_LP_ADDR,
+ MT6359_RG_BUCK_VPROC1_LP_SHIFT,
+ MT6359_RG_VPROC1_FCCM_ADDR, MT6359_RG_VPROC1_FCCM_SHIFT),
+ MT6359_BUCK("buck_vcore_sshub", VCORE_SSHUB, 400000, 1193750, 6250, 0,
+ mt_volt_range2, MT6359_RG_BUCK_VCORE_SSHUB_EN_ADDR,
+ MT6359_DA_VCORE_EN_ADDR,
+ MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR,
+ MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK,
+ MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR,
+ MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK <<
+ MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT,
+ MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT,
+ MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT),
+ MT6359_REG_FIXED("ldo_vaud18", VAUD18, MT6359_RG_LDO_VAUD18_EN_ADDR,
+ MT6359_DA_VAUD18_B_EN_ADDR, 1800000),
+ MT6359_LDO("ldo_vsim1", VSIM1, vsim1_voltages,
+ MT6359_RG_LDO_VSIM1_EN_ADDR, MT6359_RG_LDO_VSIM1_EN_SHIFT,
+ MT6359_DA_VSIM1_B_EN_ADDR, MT6359_RG_VSIM1_VOSEL_ADDR,
+ MT6359_RG_VSIM1_VOSEL_MASK << MT6359_RG_VSIM1_VOSEL_SHIFT,
+ MT6359_RG_VSIM1_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vibr", VIBR, vibr_voltages,
+ MT6359_RG_LDO_VIBR_EN_ADDR, MT6359_RG_LDO_VIBR_EN_SHIFT,
+ MT6359_DA_VIBR_B_EN_ADDR, MT6359_RG_VIBR_VOSEL_ADDR,
+ MT6359_RG_VIBR_VOSEL_MASK << MT6359_RG_VIBR_VOSEL_SHIFT,
+ MT6359_RG_VIBR_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vrf12", VRF12, vrf12_voltages,
+ MT6359_RG_LDO_VRF12_EN_ADDR, MT6359_RG_LDO_VRF12_EN_SHIFT,
+ MT6359_DA_VRF12_B_EN_ADDR, MT6359_RG_VRF12_VOSEL_ADDR,
+ MT6359_RG_VRF12_VOSEL_MASK << MT6359_RG_VRF12_VOSEL_SHIFT,
+ MT6359_RG_VRF12_VOSEL_SHIFT),
+ MT6359_REG_FIXED("ldo_vusb", VUSB, MT6359_RG_LDO_VUSB_EN_0_ADDR,
+ MT6359_DA_VUSB_B_EN_ADDR, 3000000),
+ MT6359_LDO_LINEAR("ldo_vsram_proc2", VSRAM_PROC2, 500000, 1193750, 6250,
+ 0, mt_volt_range6, MT6359_RG_LDO_VSRAM_PROC2_EN_ADDR,
+ MT6359_DA_VSRAM_PROC2_B_EN_ADDR,
+ MT6359_DA_VSRAM_PROC2_VOSEL_ADDR,
+ MT6359_DA_VSRAM_PROC2_VOSEL_MASK,
+ MT6359_DA_VSRAM_PROC2_VOSEL_SHIFT,
+ MT6359_RG_LDO_VSRAM_PROC2_VOSEL_ADDR,
+ MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK <<
+ MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vio18", VIO18, volt18_voltages,
+ MT6359_RG_LDO_VIO18_EN_ADDR, MT6359_RG_LDO_VIO18_EN_SHIFT,
+ MT6359_DA_VIO18_B_EN_ADDR, MT6359_RG_VIO18_VOSEL_ADDR,
+ MT6359_RG_VIO18_VOSEL_MASK << MT6359_RG_VIO18_VOSEL_SHIFT,
+ MT6359_RG_VIO18_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vcamio", VCAMIO, volt18_voltages,
+ MT6359_RG_LDO_VCAMIO_EN_ADDR, MT6359_RG_LDO_VCAMIO_EN_SHIFT,
+ MT6359_DA_VCAMIO_B_EN_ADDR, MT6359_RG_VCAMIO_VOSEL_ADDR,
+ MT6359_RG_VCAMIO_VOSEL_MASK << MT6359_RG_VCAMIO_VOSEL_SHIFT,
+ MT6359_RG_VCAMIO_VOSEL_SHIFT),
+ MT6359_REG_FIXED("ldo_vcn18", VCN18, MT6359_RG_LDO_VCN18_EN_ADDR,
+ MT6359_DA_VCN18_B_EN_ADDR, 1800000),
+ MT6359_REG_FIXED("ldo_vfe28", VFE28, MT6359_RG_LDO_VFE28_EN_ADDR,
+ MT6359_DA_VFE28_B_EN_ADDR, 2800000),
+ MT6359_LDO("ldo_vcn13", VCN13, vcn13_voltages,
+ MT6359_RG_LDO_VCN13_EN_ADDR, MT6359_RG_LDO_VCN13_EN_SHIFT,
+ MT6359_DA_VCN13_B_EN_ADDR, MT6359_RG_VCN13_VOSEL_ADDR,
+ MT6359_RG_VCN13_VOSEL_MASK << MT6359_RG_VCN13_VOSEL_SHIFT,
+ MT6359_RG_VCN13_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vcn33_1_bt", VCN33_1_BT, vcn33_voltages,
+ MT6359_RG_LDO_VCN33_1_EN_0_ADDR,
+ MT6359_RG_LDO_VCN33_1_EN_0_SHIFT,
+ MT6359_DA_VCN33_1_B_EN_ADDR, MT6359_RG_VCN33_1_VOSEL_ADDR,
+ MT6359_RG_VCN33_1_VOSEL_MASK <<
+ MT6359_RG_VCN33_1_VOSEL_SHIFT,
+ MT6359_RG_VCN33_1_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vcn33_1_wifi", VCN33_1_WIFI, vcn33_voltages,
+ MT6359_RG_LDO_VCN33_1_EN_1_ADDR,
+ MT6359_RG_LDO_VCN33_1_EN_1_SHIFT,
+ MT6359_DA_VCN33_1_B_EN_ADDR, MT6359_RG_VCN33_1_VOSEL_ADDR,
+ MT6359_RG_VCN33_1_VOSEL_MASK <<
+ MT6359_RG_VCN33_1_VOSEL_SHIFT,
+ MT6359_RG_VCN33_1_VOSEL_SHIFT),
+ MT6359_REG_FIXED("ldo_vaux18", VAUX18, MT6359_RG_LDO_VAUX18_EN_ADDR,
+ MT6359_DA_VAUX18_B_EN_ADDR, 1800000),
+ MT6359_LDO_LINEAR("ldo_vsram_others", VSRAM_OTHERS, 500000, 1193750,
+ 6250, 0, mt_volt_range6,
+ MT6359_RG_LDO_VSRAM_OTHERS_EN_ADDR,
+ MT6359_DA_VSRAM_OTHERS_B_EN_ADDR,
+ MT6359_DA_VSRAM_OTHERS_VOSEL_ADDR,
+ MT6359_DA_VSRAM_OTHERS_VOSEL_MASK,
+ MT6359_DA_VSRAM_OTHERS_VOSEL_SHIFT,
+ MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR,
+ MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK <<
+ MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vefuse", VEFUSE, vefuse_voltages,
+ MT6359_RG_LDO_VEFUSE_EN_ADDR, MT6359_RG_LDO_VEFUSE_EN_SHIFT,
+ MT6359_DA_VEFUSE_B_EN_ADDR, MT6359_RG_VEFUSE_VOSEL_ADDR,
+ MT6359_RG_VEFUSE_VOSEL_MASK << MT6359_RG_VEFUSE_VOSEL_SHIFT,
+ MT6359_RG_VEFUSE_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vxo22", VXO22, vxo22_voltages,
+ MT6359_RG_LDO_VXO22_EN_ADDR, MT6359_RG_LDO_VXO22_EN_SHIFT,
+ MT6359_DA_VXO22_B_EN_ADDR, MT6359_RG_VXO22_VOSEL_ADDR,
+ MT6359_RG_VXO22_VOSEL_MASK << MT6359_RG_VXO22_VOSEL_SHIFT,
+ MT6359_RG_VXO22_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vrfck", VRFCK, vrfck_voltages,
+ MT6359_RG_LDO_VRFCK_EN_ADDR, MT6359_RG_LDO_VRFCK_EN_SHIFT,
+ MT6359_DA_VRFCK_B_EN_ADDR, MT6359_RG_VRFCK_VOSEL_ADDR,
+ MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT,
+ MT6359_RG_VRFCK_VOSEL_SHIFT),
+ MT6359_REG_FIXED("ldo_vbif28", VBIF28, MT6359_RG_LDO_VBIF28_EN_ADDR,
+ MT6359_DA_VBIF28_B_EN_ADDR, 2800000),
+ MT6359_LDO("ldo_vio28", VIO28, vio28_voltages,
+ MT6359_RG_LDO_VIO28_EN_ADDR, MT6359_RG_LDO_VIO28_EN_SHIFT,
+ MT6359_DA_VIO28_B_EN_ADDR, MT6359_RG_VIO28_VOSEL_ADDR,
+ MT6359_RG_VIO28_VOSEL_MASK << MT6359_RG_VIO28_VOSEL_SHIFT,
+ MT6359_RG_VIO28_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vemc", VEMC, vemc_voltages,
+ MT6359_RG_LDO_VEMC_EN_ADDR, MT6359_RG_LDO_VEMC_EN_SHIFT,
+ MT6359_DA_VEMC_B_EN_ADDR, MT6359_RG_VEMC_VOSEL_ADDR,
+ MT6359_RG_VEMC_VOSEL_MASK << MT6359_RG_VEMC_VOSEL_SHIFT,
+ MT6359_RG_VEMC_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vcn33_2_bt", VCN33_2_BT, vcn33_voltages,
+ MT6359_RG_LDO_VCN33_2_EN_0_ADDR,
+ MT6359_RG_LDO_VCN33_2_EN_0_SHIFT,
+ MT6359_DA_VCN33_2_B_EN_ADDR, MT6359_RG_VCN33_2_VOSEL_ADDR,
+ MT6359_RG_VCN33_2_VOSEL_MASK <<
+ MT6359_RG_VCN33_2_VOSEL_SHIFT,
+ MT6359_RG_VCN33_2_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vcn33_2_wifi", VCN33_2_WIFI, vcn33_voltages,
+ MT6359_RG_LDO_VCN33_2_EN_1_ADDR,
+ MT6359_RG_LDO_VCN33_2_EN_1_SHIFT,
+ MT6359_DA_VCN33_2_B_EN_ADDR, MT6359_RG_VCN33_2_VOSEL_ADDR,
+ MT6359_RG_VCN33_2_VOSEL_MASK <<
+ MT6359_RG_VCN33_2_VOSEL_SHIFT,
+ MT6359_RG_VCN33_2_VOSEL_SHIFT),
+ MT6359_LDO("ldo_va12", VA12, va12_voltages,
+ MT6359_RG_LDO_VA12_EN_ADDR, MT6359_RG_LDO_VA12_EN_SHIFT,
+ MT6359_DA_VA12_B_EN_ADDR, MT6359_RG_VA12_VOSEL_ADDR,
+ MT6359_RG_VA12_VOSEL_MASK << MT6359_RG_VA12_VOSEL_SHIFT,
+ MT6359_RG_VA12_VOSEL_SHIFT),
+ MT6359_LDO("ldo_va09", VA09, va09_voltages,
+ MT6359_RG_LDO_VA09_EN_ADDR, MT6359_RG_LDO_VA09_EN_SHIFT,
+ MT6359_DA_VA09_B_EN_ADDR, MT6359_RG_VA09_VOSEL_ADDR,
+ MT6359_RG_VA09_VOSEL_MASK << MT6359_RG_VA09_VOSEL_SHIFT,
+ MT6359_RG_VA09_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vrf18", VRF18, vrf18_voltages,
+ MT6359_RG_LDO_VRF18_EN_ADDR, MT6359_RG_LDO_VRF18_EN_SHIFT,
+ MT6359_DA_VRF18_B_EN_ADDR, MT6359_RG_VRF18_VOSEL_ADDR,
+ MT6359_RG_VRF18_VOSEL_MASK << MT6359_RG_VRF18_VOSEL_SHIFT,
+ MT6359_RG_VRF18_VOSEL_SHIFT),
+ MT6359_LDO_LINEAR("ldo_vsram_md", VSRAM_MD, 500000, 1100000, 6250,
+ 0, mt_volt_range7, MT6359_RG_LDO_VSRAM_MD_EN_ADDR,
+ MT6359_DA_VSRAM_MD_B_EN_ADDR,
+ MT6359_DA_VSRAM_MD_VOSEL_ADDR,
+ MT6359_DA_VSRAM_MD_VOSEL_MASK,
+ MT6359_DA_VSRAM_MD_VOSEL_SHIFT,
+ MT6359_RG_LDO_VSRAM_MD_VOSEL_ADDR,
+ MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK <<
+ MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vufs", VUFS, volt18_voltages,
+ MT6359_RG_LDO_VUFS_EN_ADDR, MT6359_RG_LDO_VUFS_EN_SHIFT,
+ MT6359_DA_VUFS_B_EN_ADDR, MT6359_RG_VUFS_VOSEL_ADDR,
+ MT6359_RG_VUFS_VOSEL_MASK << MT6359_RG_VUFS_VOSEL_SHIFT,
+ MT6359_RG_VUFS_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vm18", VM18, volt18_voltages,
+ MT6359_RG_LDO_VM18_EN_ADDR, MT6359_RG_LDO_VM18_EN_SHIFT,
+ MT6359_DA_VM18_B_EN_ADDR, MT6359_RG_VM18_VOSEL_ADDR,
+ MT6359_RG_VM18_VOSEL_MASK << MT6359_RG_VM18_VOSEL_SHIFT,
+ MT6359_RG_VM18_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vbbck", VBBCK, vbbck_voltages,
+ MT6359_RG_LDO_VBBCK_EN_ADDR, MT6359_RG_LDO_VBBCK_EN_SHIFT,
+ MT6359_DA_VBBCK_B_EN_ADDR, MT6359_RG_VBBCK_VOSEL_ADDR,
+ MT6359_RG_VBBCK_VOSEL_MASK << MT6359_RG_VBBCK_VOSEL_SHIFT,
+ MT6359_RG_VBBCK_VOSEL_SHIFT),
+ MT6359_LDO_LINEAR("ldo_vsram_proc1", VSRAM_PROC1, 500000, 1193750, 6250,
+ 0, mt_volt_range6, MT6359_RG_LDO_VSRAM_PROC1_EN_ADDR,
+ MT6359_DA_VSRAM_PROC1_B_EN_ADDR,
+ MT6359_DA_VSRAM_PROC1_VOSEL_ADDR,
+ MT6359_DA_VSRAM_PROC1_VOSEL_MASK,
+ MT6359_DA_VSRAM_PROC1_VOSEL_SHIFT,
+ MT6359_RG_LDO_VSRAM_PROC1_VOSEL_ADDR,
+ MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK <<
+ MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT),
+ MT6359_LDO("ldo_vsim2", VSIM2, vsim2_voltages,
+ MT6359_RG_LDO_VSIM2_EN_ADDR, MT6359_RG_LDO_VSIM2_EN_SHIFT,
+ MT6359_DA_VSIM2_B_EN_ADDR, MT6359_RG_VSIM2_VOSEL_ADDR,
+ MT6359_RG_VSIM2_VOSEL_MASK << MT6359_RG_VSIM2_VOSEL_SHIFT,
+ MT6359_RG_VSIM2_VOSEL_SHIFT),
+ MT6359_LDO_LINEAR("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB,
+ 500000, 1193750, 6250, 0, mt_volt_range6,
+ MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR,
+ MT6359_DA_VSRAM_OTHERS_B_EN_ADDR,
+ MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR,
+ MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK,
+ MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT,
+ MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR,
+ MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK <<
+ MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT),
+};
+
+static int mt6359_regulator_probe(struct platform_device *pdev)
+{
+ struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
+ struct regulator_config config = {};
+ struct regulator_dev *rdev;
+ int i;
+
+ for (i = 0; i < MT6359_MAX_REGULATOR; i++) {
+ config.dev = &pdev->dev;
+ config.driver_data = &mt6359_regulators[i];
+ config.regmap = mt6397->regmap;
+
+ rdev = devm_regulator_register(&pdev->dev,
+ &mt6359_regulators[i].desc,
+ &config);
+ if (IS_ERR(rdev)) {
+ dev_err(&pdev->dev, "failed to register %s\n",
+ mt6359_regulators[i].desc.name);
+ return PTR_ERR(rdev);
+ }
+ }
+
+ return 0;
+}
+
+static const struct platform_device_id mt6359_platform_ids[] = {
+ {"mt6359-regulator", 0},
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(platform, mt6359_platform_ids);
+
+static struct platform_driver mt6359_regulator_driver = {
+ .driver = {
+ .name = "mt6359-regulator",
+ },
+ .probe = mt6359_regulator_probe,
+ .id_table = mt6359_platform_ids,
+};
+
+module_platform_driver(mt6359_regulator_driver);
+
+MODULE_AUTHOR("Wen Su <wen.su@mediatek.com>");
+MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6359 PMIC");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/regulator/mt6359-regulator.h b/include/linux/regulator/mt6359-regulator.h
new file mode 100644
index 0000000..6b17173
--- /dev/null
+++ b/include/linux/regulator/mt6359-regulator.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __LINUX_REGULATOR_MT6359_H
+#define __LINUX_REGULATOR_MT6359_H
+
+enum {
+ MT6359_ID_VS1 = 0,
+ MT6359_ID_VGPU11,
+ MT6359_ID_VMODEM,
+ MT6359_ID_VPU,
+ MT6359_ID_VCORE,
+ MT6359_ID_VS2,
+ MT6359_ID_VPA,
+ MT6359_ID_VPROC2,
+ MT6359_ID_VPROC1,
+ MT6359_ID_VCORE_SSHUB,
+ MT6359_ID_VAUD18 = 10,
+ MT6359_ID_VSIM1,
+ MT6359_ID_VIBR,
+ MT6359_ID_VRF12,
+ MT6359_ID_VUSB,
+ MT6359_ID_VSRAM_PROC2,
+ MT6359_ID_VIO18,
+ MT6359_ID_VCAMIO,
+ MT6359_ID_VCN18,
+ MT6359_ID_VFE28,
+ MT6359_ID_VCN13,
+ MT6359_ID_VCN33_1_BT,
+ MT6359_ID_VCN33_1_WIFI,
+ MT6359_ID_VAUX18,
+ MT6359_ID_VSRAM_OTHERS,
+ MT6359_ID_VEFUSE,
+ MT6359_ID_VXO22,
+ MT6359_ID_VRFCK,
+ MT6359_ID_VBIF28,
+ MT6359_ID_VIO28,
+ MT6359_ID_VEMC,
+ MT6359_ID_VCN33_2_BT,
+ MT6359_ID_VCN33_2_WIFI,
+ MT6359_ID_VA12,
+ MT6359_ID_VA09,
+ MT6359_ID_VRF18,
+ MT6359_ID_VSRAM_MD,
+ MT6359_ID_VUFS,
+ MT6359_ID_VM18,
+ MT6359_ID_VBBCK,
+ MT6359_ID_VSRAM_PROC1,
+ MT6359_ID_VSIM2,
+ MT6359_ID_VSRAM_OTHERS_SSHUB,
+ MT6359_ID_RG_MAX,
+};
+
+#define MT6359_MAX_REGULATOR MT6359_ID_RG_MAX
+
+#endif /* __LINUX_REGULATOR_MT6359_H */
--
1.9.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* [RESEND v2 4/4] arm64: dts: mt6359: add PMIC MT6359 related nodes
2020-02-21 2:39 [RESEND v2 0/4] Add Support for MediaTek PMIC MT6359 Regulator Wen Su
` (2 preceding siblings ...)
2020-02-21 2:39 ` [RESEND v2 3/4] regulator: mt6359: Add support for MT6359 regulator Wen Su
@ 2020-02-21 2:39 ` Wen Su
3 siblings, 0 replies; 7+ messages in thread
From: Wen Su @ 2020-02-21 2:39 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Mark Brown, Matthias Brugger
Cc: Mark Rutland, devicetree, wen.su, wsd_upstream, linux-kernel,
Liam Girdwood, linux-mediatek, linux-arm-kernel
From: "Wen Su" <wen.su@mediatek.com>
add PMIC MT6359 related nodes which is for MT6779 platform
Signed-off-by: Wen Su <wen.su@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt6359.dtsi | 306 +++++++++++++++++++++++++++++++
1 file changed, 306 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6359.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi
new file mode 100644
index 0000000..4cafe1f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi
@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+&pwrap {
+ pmic: pmic {
+ mt6359regulator: mt6359regulator {
+ compatible = "mediatek,mt6359-regulator";
+ mt6359_vs1_buck_reg: buck_vs1 {
+ regulator-name = "vs1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-always-on;
+ };
+ mt6359_vgpu11_buck_reg: buck_vgpu11 {
+ regulator-name = "vgpu11";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <5000>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-always-on;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ mt6359_vmodem_buck_reg: buck_vmodem {
+ regulator-name = "vmodem";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-ramp-delay = <10760>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-always-on;
+ };
+ mt6359_vpu_buck_reg: buck_vpu {
+ regulator-name = "vpu";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <5000>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ mt6359_vcore_buck_reg: buck_vcore {
+ regulator-name = "vcore";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <5000>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-always-on;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ mt6359_vs2_buck_reg: buck_vs2 {
+ regulator-name = "vs2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1600000>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-always-on;
+ };
+ mt6359_vpa_buck_reg: buck_vpa {
+ regulator-name = "vpa";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3650000>;
+ regulator-enable-ramp-delay = <300>;
+ };
+ mt6359_vproc2_buck_reg: buck_vproc2 {
+ regulator-name = "vproc2";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <7500>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-always-on;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ mt6359_vproc1_buck_reg: buck_vproc1 {
+ regulator-name = "vproc1";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <7500>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-always-on;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ mt6359_vcore_sshub_buck_reg: buck_vcore_sshub {
+ regulator-name = "vcore_sshub";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ };
+ mt6359_vaud18_ldo_reg: ldo_vaud18 {
+ regulator-name = "vaud18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vsim1_ldo_reg: ldo_vsim1 {
+ regulator-name = "vsim1";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-enable-ramp-delay = <480>;
+ };
+ mt6359_vibr_ldo_reg: ldo_vibr {
+ regulator-name = "vibr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vrf12_ldo_reg: ldo_vrf12 {
+ regulator-name = "vrf12";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+ mt6359_vusb_ldo_reg: ldo_vusb {
+ regulator-name = "vusb";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+ mt6359_vsram_proc2_ldo_reg: ldo_vsram_proc2 {
+ regulator-name = "vsram_proc2";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <7500>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+ mt6359_vio18_ldo_reg: ldo_vio18 {
+ regulator-name = "vio18";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-enable-ramp-delay = <960>;
+ regulator-always-on;
+ };
+ mt6359_vcamio_ldo_reg: ldo_vcamio {
+ regulator-name = "vcamio";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-enable-ramp-delay = <1920>;
+ };
+ mt6359_vcn18_ldo_reg: ldo_vcn18 {
+ regulator-name = "vcn18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vfe28_ldo_reg: ldo_vfe28 {
+ regulator-name = "vfe28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <120>;
+ regulator-always-on;
+ };
+ mt6359_vcn13_ldo_reg: ldo_vcn13 {
+ regulator-name = "vcn13";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vcn33_1_bt_ldo_reg: ldo_vcn33_1_bt {
+ regulator-name = "vcn33_1_bt";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3500000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vcn33_1_wifi_ldo_reg: ldo_vcn33_1_wifi {
+ regulator-name = "vcn33_1_wifi";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3500000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vaux18_ldo_reg: ldo_vaux18 {
+ regulator-name = "vaux18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+ mt6359_vsram_others_ldo_reg: ldo_vsram_others {
+ regulator-name = "vsram_others";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <5000>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+ mt6359_vefuse_ldo_reg: ldo_vefuse {
+ regulator-name = "vefuse";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vxo22_ldo_reg: ldo_vxo22 {
+ regulator-name = "vxo22";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-enable-ramp-delay = <120>;
+ regulator-always-on;
+ };
+ mt6359_vrfck_ldo_reg: ldo_vrfck {
+ regulator-name = "vrfck";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1700000>;
+ regulator-enable-ramp-delay = <480>;
+ };
+ mt6359_vbif28_ldo_reg: ldo_vbif28 {
+ regulator-name = "vbif28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+ mt6359_vio28_ldo_reg: ldo_vio28 {
+ regulator-name = "vio28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+ mt6359_vemc_ldo_reg: ldo_vemc {
+ regulator-name = "vemc";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vcn33_2_bt_ldo_reg: ldo_vcn33_2_bt {
+ regulator-name = "vcn33_2_bt";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3500000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vcn33_2_wifi_ldo_reg: ldo_vcn33_2_wifi {
+ regulator-name = "vcn33_2_wifi";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3500000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_va12_ldo_reg: ldo_va12 {
+ regulator-name = "va12";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+ mt6359_va09_ldo_reg: ldo_va09 {
+ regulator-name = "va09";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+ mt6359_vrf18_ldo_reg: ldo_vrf18 {
+ regulator-name = "vrf18";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1810000>;
+ regulator-enable-ramp-delay = <120>;
+ regulator-always-on;
+ };
+ mt6359_vsram_md_ldo_reg: ldo_vsram_md {
+ regulator-name = "vsram_md";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-ramp-delay = <10760>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+ mt6359_vufs_ldo_reg: ldo_vufs {
+ regulator-name = "vufs";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-enable-ramp-delay = <1920>;
+ regulator-always-on;
+ };
+ mt6359_vm18_ldo_reg: ldo_vm18 {
+ regulator-name = "vm18";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-enable-ramp-delay = <1920>;
+ regulator-always-on;
+ };
+ mt6359_vbbck_ldo_reg: ldo_vbbck {
+ regulator-name = "vbbck";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vsram_proc1_ldo_reg: ldo_vsram_proc1 {
+ regulator-name = "vsram_proc1";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <7500>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+ mt6359_vsim2_ldo_reg: ldo_vsim2 {
+ regulator-name = "vsim2";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-enable-ramp-delay = <480>;
+ };
+ mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub {
+ regulator-name = "vsram_others_sshub";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1193750>;
+ };
+ };
+ };
+};
--
1.9.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [RESEND v2 2/4] mfd: Add for PMIC MT6359 registers definition
2020-02-21 2:39 ` [RESEND v2 2/4] mfd: Add for PMIC MT6359 registers definition Wen Su
@ 2020-06-16 9:58 ` Wen Su
2020-06-16 13:18 ` Lee Jones
0 siblings, 1 reply; 7+ messages in thread
From: Wen Su @ 2020-06-16 9:58 UTC (permalink / raw)
To: Lee Jones, Mark Brown
Cc: Mark Rutland, devicetree, wen.su, wsd_upstream, linux-kernel,
Rob Herring, Liam Girdwood, Mark Brown, linux-mediatek,
Matthias Brugger, linux-arm-kernel
Dear Reviewers,
I am sorry to bother you. How should I proceed for this patch set ?
Since the regulator driver were applied and dropped because of the MFD
header file dependency on this patch.
Will this mfd registers definition patch and regulator driver patch be
applied ? Please advice.
Thanks
On Fri, 2020-02-21 at 10:39 +0800, Wen Su wrote:
> From: "Wen Su" <wen.su@mediatek.com>
>
> This adds MediaTek PMIC MT6359 registers definition for the
> following sub modules:
>
> - Regulator
> - RTC
> - Interrupt
>
> Signed-off-by: Wen Su <wen.su@mediatek.com>
> Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
> ---
> include/linux/mfd/mt6359/registers.h | 531 +++++++++++++++++++++++++++++++++++
> 1 file changed, 531 insertions(+)
> create mode 100644 include/linux/mfd/mt6359/registers.h
>
> diff --git a/include/linux/mfd/mt6359/registers.h b/include/linux/mfd/mt6359/registers.h
> new file mode 100644
> index 0000000..32f627e
> --- /dev/null
> +++ b/include/linux/mfd/mt6359/registers.h
> @@ -0,0 +1,531 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + */
> +
> +#ifndef __MFD_MT6359_REGISTERS_H__
> +#define __MFD_MT6359_REGISTERS_H__
> +
> +/* PMIC Registers */
> +#define MT6359_SWCID 0xa
> +#define MT6359_MISC_TOP_INT_CON0 0x188
> +#define MT6359_MISC_TOP_INT_STATUS0 0x194
> +#define MT6359_TOP_INT_STATUS0 0x19e
> +#define MT6359_SCK_TOP_INT_CON0 0x528
> +#define MT6359_SCK_TOP_INT_STATUS0 0x534
> +#define MT6359_EOSC_CALI_CON0 0x53a
> +#define MT6359_EOSC_CALI_CON1 0x53c
> +#define MT6359_RTC_MIX_CON0 0x53e
> +#define MT6359_RTC_MIX_CON1 0x540
> +#define MT6359_RTC_MIX_CON2 0x542
> +#define MT6359_RTC_DSN_ID 0x580
> +#define MT6359_RTC_DSN_REV0 0x582
> +#define MT6359_RTC_DBI 0x584
> +#define MT6359_RTC_DXI 0x586
> +#define MT6359_RTC_BBPU 0x588
> +#define MT6359_RTC_IRQ_STA 0x58a
> +#define MT6359_RTC_IRQ_EN 0x58c
> +#define MT6359_RTC_CII_EN 0x58e
> +#define MT6359_RTC_AL_MASK 0x590
> +#define MT6359_RTC_TC_SEC 0x592
> +#define MT6359_RTC_TC_MIN 0x594
> +#define MT6359_RTC_TC_HOU 0x596
> +#define MT6359_RTC_TC_DOM 0x598
> +#define MT6359_RTC_TC_DOW 0x59a
> +#define MT6359_RTC_TC_MTH 0x59c
> +#define MT6359_RTC_TC_YEA 0x59e
> +#define MT6359_RTC_AL_SEC 0x5a0
> +#define MT6359_RTC_AL_MIN 0x5a2
> +#define MT6359_RTC_AL_HOU 0x5a4
> +#define MT6359_RTC_AL_DOM 0x5a6
> +#define MT6359_RTC_AL_DOW 0x5a8
> +#define MT6359_RTC_AL_MTH 0x5aa
> +#define MT6359_RTC_AL_YEA 0x5ac
> +#define MT6359_RTC_OSC32CON 0x5ae
> +#define MT6359_RTC_POWERKEY1 0x5b0
> +#define MT6359_RTC_POWERKEY2 0x5b2
> +#define MT6359_RTC_PDN1 0x5b4
> +#define MT6359_RTC_PDN2 0x5b6
> +#define MT6359_RTC_SPAR0 0x5b8
> +#define MT6359_RTC_SPAR1 0x5ba
> +#define MT6359_RTC_PROT 0x5bc
> +#define MT6359_RTC_DIFF 0x5be
> +#define MT6359_RTC_CALI 0x5c0
> +#define MT6359_RTC_WRTGR 0x5c2
> +#define MT6359_RTC_CON 0x5c4
> +#define MT6359_RTC_SEC_CTRL 0x5c6
> +#define MT6359_RTC_INT_CNT 0x5c8
> +#define MT6359_RTC_SEC_DAT0 0x5ca
> +#define MT6359_RTC_SEC_DAT1 0x5cc
> +#define MT6359_RTC_SEC_DAT2 0x5ce
> +#define MT6359_RTC_SEC_DSN_ID 0x600
> +#define MT6359_RTC_SEC_DSN_REV0 0x602
> +#define MT6359_RTC_SEC_DBI 0x604
> +#define MT6359_RTC_SEC_DXI 0x606
> +#define MT6359_RTC_TC_SEC_SEC 0x608
> +#define MT6359_RTC_TC_MIN_SEC 0x60a
> +#define MT6359_RTC_TC_HOU_SEC 0x60c
> +#define MT6359_RTC_TC_DOM_SEC 0x60e
> +#define MT6359_RTC_TC_DOW_SEC 0x610
> +#define MT6359_RTC_TC_MTH_SEC 0x612
> +#define MT6359_RTC_TC_YEA_SEC 0x614
> +#define MT6359_RTC_SEC_CK_PDN 0x616
> +#define MT6359_RTC_SEC_WRTGR 0x618
> +#define MT6359_PSC_TOP_INT_CON0 0x910
> +#define MT6359_PSC_TOP_INT_STATUS0 0x91c
> +#define MT6359_BM_TOP_INT_CON0 0xc32
> +#define MT6359_BM_TOP_INT_CON1 0xc38
> +#define MT6359_BM_TOP_INT_STATUS0 0xc4a
> +#define MT6359_BM_TOP_INT_STATUS1 0xc4c
> +#define MT6359_HK_TOP_INT_CON0 0xf92
> +#define MT6359_HK_TOP_INT_STATUS0 0xf9e
> +#define MT6359_BUCK_TOP_INT_CON0 0x1418
> +#define MT6359_BUCK_TOP_INT_STATUS0 0x1424
> +#define MT6359_BUCK_VPU_CON0 0x1488
> +#define MT6359_BUCK_VPU_DBG0 0x14a6
> +#define MT6359_BUCK_VPU_DBG1 0x14a8
> +#define MT6359_BUCK_VPU_ELR0 0x14ac
> +#define MT6359_BUCK_VCORE_CON0 0x1508
> +#define MT6359_BUCK_VCORE_DBG0 0x1526
> +#define MT6359_BUCK_VCORE_DBG1 0x1528
> +#define MT6359_BUCK_VCORE_SSHUB_CON0 0x152a
> +#define MT6359_BUCK_VCORE_ELR0 0x1534
> +#define MT6359_BUCK_VGPU11_CON0 0x1588
> +#define MT6359_BUCK_VGPU11_DBG0 0x15a6
> +#define MT6359_BUCK_VGPU11_DBG1 0x15a8
> +#define MT6359_BUCK_VGPU11_ELR0 0x15ac
> +#define MT6359_BUCK_VMODEM_CON0 0x1688
> +#define MT6359_BUCK_VMODEM_DBG0 0x16a6
> +#define MT6359_BUCK_VMODEM_DBG1 0x16a8
> +#define MT6359_BUCK_VMODEM_ELR0 0x16ae
> +#define MT6359_BUCK_VPROC1_CON0 0x1708
> +#define MT6359_BUCK_VPROC1_DBG0 0x1726
> +#define MT6359_BUCK_VPROC1_DBG1 0x1728
> +#define MT6359_BUCK_VPROC1_ELR0 0x172e
> +#define MT6359_BUCK_VPROC2_CON0 0x1788
> +#define MT6359_BUCK_VPROC2_DBG0 0x17a6
> +#define MT6359_BUCK_VPROC2_DBG1 0x17a8
> +#define MT6359_BUCK_VPROC2_ELR0 0x17b2
> +#define MT6359_BUCK_VS1_CON0 0x1808
> +#define MT6359_BUCK_VS1_DBG0 0x1826
> +#define MT6359_BUCK_VS1_DBG1 0x1828
> +#define MT6359_BUCK_VS1_ELR0 0x1834
> +#define MT6359_BUCK_VS2_CON0 0x1888
> +#define MT6359_BUCK_VS2_DBG0 0x18a6
> +#define MT6359_BUCK_VS2_DBG1 0x18a8
> +#define MT6359_BUCK_VS2_ELR0 0x18b4
> +#define MT6359_BUCK_VPA_CON0 0x1908
> +#define MT6359_BUCK_VPA_CON1 0x190e
> +#define MT6359_BUCK_VPA_CFG0 0x1910
> +#define MT6359_BUCK_VPA_CFG1 0x1912
> +#define MT6359_BUCK_VPA_DBG0 0x1914
> +#define MT6359_BUCK_VPA_DBG1 0x1916
> +#define MT6359_VGPUVCORE_ANA_CON2 0x198e
> +#define MT6359_VGPUVCORE_ANA_CON13 0x19a4
> +#define MT6359_VPROC1_ANA_CON3 0x19b2
> +#define MT6359_VPROC2_ANA_CON3 0x1a0e
> +#define MT6359_VMODEM_ANA_CON3 0x1a1a
> +#define MT6359_VPU_ANA_CON3 0x1a26
> +#define MT6359_VS1_ANA_CON0 0x1a2c
> +#define MT6359_VS2_ANA_CON0 0x1a34
> +#define MT6359_VPA_ANA_CON0 0x1a3c
> +#define MT6359_LDO_TOP_INT_CON0 0x1b14
> +#define MT6359_LDO_TOP_INT_CON1 0x1b1a
> +#define MT6359_LDO_TOP_INT_STATUS0 0x1b28
> +#define MT6359_LDO_TOP_INT_STATUS1 0x1b2a
> +#define MT6359_LDO_VSRAM_PROC1_ELR 0x1b40
> +#define MT6359_LDO_VSRAM_PROC2_ELR 0x1b42
> +#define MT6359_LDO_VSRAM_OTHERS_ELR 0x1b44
> +#define MT6359_LDO_VSRAM_MD_ELR 0x1b46
> +#define MT6359_LDO_VFE28_CON0 0x1b88
> +#define MT6359_LDO_VFE28_MON 0x1b8a
> +#define MT6359_LDO_VXO22_CON0 0x1b98
> +#define MT6359_LDO_VXO22_MON 0x1b9a
> +#define MT6359_LDO_VRF18_CON0 0x1ba8
> +#define MT6359_LDO_VRF18_MON 0x1baa
> +#define MT6359_LDO_VRF12_CON0 0x1bb8
> +#define MT6359_LDO_VRF12_MON 0x1bba
> +#define MT6359_LDO_VEFUSE_CON0 0x1bc8
> +#define MT6359_LDO_VEFUSE_MON 0x1bca
> +#define MT6359_LDO_VCN33_1_CON0 0x1bd8
> +#define MT6359_LDO_VCN33_1_MON 0x1bda
> +#define MT6359_LDO_VCN33_1_MULTI_SW 0x1be8
> +#define MT6359_LDO_VCN33_2_CON0 0x1c08
> +#define MT6359_LDO_VCN33_2_MON 0x1c0a
> +#define MT6359_LDO_VCN33_2_MULTI_SW 0x1c18
> +#define MT6359_LDO_VCN13_CON0 0x1c1a
> +#define MT6359_LDO_VCN13_MON 0x1c1c
> +#define MT6359_LDO_VCN18_CON0 0x1c2a
> +#define MT6359_LDO_VCN18_MON 0x1c2c
> +#define MT6359_LDO_VA09_CON0 0x1c3a
> +#define MT6359_LDO_VA09_MON 0x1c3c
> +#define MT6359_LDO_VCAMIO_CON0 0x1c4a
> +#define MT6359_LDO_VCAMIO_MON 0x1c4c
> +#define MT6359_LDO_VA12_CON0 0x1c5a
> +#define MT6359_LDO_VA12_MON 0x1c5c
> +#define MT6359_LDO_VAUX18_CON0 0x1c88
> +#define MT6359_LDO_VAUX18_MON 0x1c8a
> +#define MT6359_LDO_VAUD18_CON0 0x1c98
> +#define MT6359_LDO_VAUD18_MON 0x1c9a
> +#define MT6359_LDO_VIO18_CON0 0x1ca8
> +#define MT6359_LDO_VIO18_MON 0x1caa
> +#define MT6359_LDO_VEMC_CON0 0x1cb8
> +#define MT6359_LDO_VEMC_MON 0x1cba
> +#define MT6359_LDO_VSIM1_CON0 0x1cc8
> +#define MT6359_LDO_VSIM1_MON 0x1cca
> +#define MT6359_LDO_VSIM2_CON0 0x1cd8
> +#define MT6359_LDO_VSIM2_MON 0x1cda
> +#define MT6359_LDO_VUSB_CON0 0x1d08
> +#define MT6359_LDO_VUSB_MON 0x1d0a
> +#define MT6359_LDO_VUSB_MULTI_SW 0x1d18
> +#define MT6359_LDO_VRFCK_CON0 0x1d1a
> +#define MT6359_LDO_VRFCK_MON 0x1d1c
> +#define MT6359_LDO_VBBCK_CON0 0x1d2a
> +#define MT6359_LDO_VBBCK_MON 0x1d2c
> +#define MT6359_LDO_VBIF28_CON0 0x1d3a
> +#define MT6359_LDO_VBIF28_MON 0x1d3c
> +#define MT6359_LDO_VIBR_CON0 0x1d4a
> +#define MT6359_LDO_VIBR_MON 0x1d4c
> +#define MT6359_LDO_VIO28_CON0 0x1d5a
> +#define MT6359_LDO_VIO28_MON 0x1d5c
> +#define MT6359_LDO_VM18_CON0 0x1d88
> +#define MT6359_LDO_VM18_MON 0x1d8a
> +#define MT6359_LDO_VUFS_CON0 0x1d98
> +#define MT6359_LDO_VUFS_MON 0x1d9a
> +#define MT6359_LDO_VSRAM_PROC1_CON0 0x1e88
> +#define MT6359_LDO_VSRAM_PROC1_MON 0x1e8a
> +#define MT6359_LDO_VSRAM_PROC1_VOSEL1 0x1e8e
> +#define MT6359_LDO_VSRAM_PROC2_CON0 0x1ea6
> +#define MT6359_LDO_VSRAM_PROC2_MON 0x1ea8
> +#define MT6359_LDO_VSRAM_PROC2_VOSEL1 0x1eac
> +#define MT6359_LDO_VSRAM_OTHERS_CON0 0x1f08
> +#define MT6359_LDO_VSRAM_OTHERS_MON 0x1f0a
> +#define MT6359_LDO_VSRAM_OTHERS_VOSEL1 0x1f0e
> +#define MT6359_LDO_VSRAM_OTHERS_SSHUB 0x1f26
> +#define MT6359_LDO_VSRAM_MD_CON0 0x1f2c
> +#define MT6359_LDO_VSRAM_MD_MON 0x1f2e
> +#define MT6359_LDO_VSRAM_MD_VOSEL1 0x1f32
> +#define MT6359_VFE28_ANA_CON0 0x1f88
> +#define MT6359_VAUX18_ANA_CON0 0x1f8c
> +#define MT6359_VUSB_ANA_CON0 0x1f90
> +#define MT6359_VBIF28_ANA_CON0 0x1f94
> +#define MT6359_VCN33_1_ANA_CON0 0x1f98
> +#define MT6359_VCN33_2_ANA_CON0 0x1f9c
> +#define MT6359_VEMC_ANA_CON0 0x1fa0
> +#define MT6359_VSIM1_ANA_CON0 0x1fa4
> +#define MT6359_VSIM2_ANA_CON0 0x1fa8
> +#define MT6359_VIO28_ANA_CON0 0x1fac
> +#define MT6359_VIBR_ANA_CON0 0x1fb0
> +#define MT6359_VRF18_ANA_CON0 0x2008
> +#define MT6359_VEFUSE_ANA_CON0 0x200c
> +#define MT6359_VCN18_ANA_CON0 0x2010
> +#define MT6359_VCAMIO_ANA_CON0 0x2014
> +#define MT6359_VAUD18_ANA_CON0 0x2018
> +#define MT6359_VIO18_ANA_CON0 0x201c
> +#define MT6359_VM18_ANA_CON0 0x2020
> +#define MT6359_VUFS_ANA_CON0 0x2024
> +#define MT6359_VRF12_ANA_CON0 0x202a
> +#define MT6359_VCN13_ANA_CON0 0x202e
> +#define MT6359_VA09_ANA_CON0 0x2032
> +#define MT6359_VA12_ANA_CON0 0x2036
> +#define MT6359_VXO22_ANA_CON0 0x2088
> +#define MT6359_VRFCK_ANA_CON0 0x208c
> +#define MT6359_VBBCK_ANA_CON0 0x2094
> +#define MT6359_AUD_TOP_INT_CON0 0x2328
> +#define MT6359_AUD_TOP_INT_STATUS0 0x2334
> +
> +#define MT6359_RG_BUCK_VPU_EN_ADDR MT6359_BUCK_VPU_CON0
> +#define MT6359_RG_BUCK_VPU_LP_ADDR MT6359_BUCK_VPU_CON0
> +#define MT6359_RG_BUCK_VPU_LP_SHIFT 1
> +#define MT6359_DA_VPU_VOSEL_ADDR MT6359_BUCK_VPU_DBG0
> +#define MT6359_DA_VPU_VOSEL_MASK 0x7F
> +#define MT6359_DA_VPU_VOSEL_SHIFT 0
> +#define MT6359_DA_VPU_EN_ADDR MT6359_BUCK_VPU_DBG1
> +#define MT6359_RG_BUCK_VPU_VOSEL_ADDR MT6359_BUCK_VPU_ELR0
> +#define MT6359_RG_BUCK_VPU_VOSEL_MASK 0x7F
> +#define MT6359_RG_BUCK_VPU_VOSEL_SHIFT 0
> +#define MT6359_RG_BUCK_VCORE_EN_ADDR MT6359_BUCK_VCORE_CON0
> +#define MT6359_RG_BUCK_VCORE_LP_ADDR MT6359_BUCK_VCORE_CON0
> +#define MT6359_RG_BUCK_VCORE_LP_SHIFT 1
> +#define MT6359_DA_VCORE_VOSEL_ADDR MT6359_BUCK_VCORE_DBG0
> +#define MT6359_DA_VCORE_VOSEL_MASK 0x7F
> +#define MT6359_DA_VCORE_VOSEL_SHIFT 0
> +#define MT6359_DA_VCORE_EN_ADDR MT6359_BUCK_VCORE_DBG1
> +#define MT6359_RG_BUCK_VCORE_SSHUB_EN_ADDR MT6359_BUCK_VCORE_SSHUB_CON0
> +#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR MT6359_BUCK_VCORE_SSHUB_CON0
> +#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK 0x7F
> +#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT 4
> +#define MT6359_RG_BUCK_VCORE_VOSEL_ADDR MT6359_BUCK_VCORE_ELR0
> +#define MT6359_RG_BUCK_VCORE_VOSEL_MASK 0x7F
> +#define MT6359_RG_BUCK_VCORE_VOSEL_SHIFT 0
> +#define MT6359_RG_BUCK_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_CON0
> +#define MT6359_RG_BUCK_VGPU11_LP_ADDR MT6359_BUCK_VGPU11_CON0
> +#define MT6359_RG_BUCK_VGPU11_LP_SHIFT 1
> +#define MT6359_DA_VGPU11_VOSEL_ADDR MT6359_BUCK_VGPU11_DBG0
> +#define MT6359_DA_VGPU11_VOSEL_MASK 0x7F
> +#define MT6359_DA_VGPU11_VOSEL_SHIFT 0
> +#define MT6359_DA_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_DBG1
> +#define MT6359_RG_BUCK_VGPU11_VOSEL_ADDR MT6359_BUCK_VGPU11_ELR0
> +#define MT6359_RG_BUCK_VGPU11_VOSEL_MASK 0x7F
> +#define MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT 0
> +#define MT6359_RG_BUCK_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_CON0
> +#define MT6359_RG_BUCK_VMODEM_LP_ADDR MT6359_BUCK_VMODEM_CON0
> +#define MT6359_RG_BUCK_VMODEM_LP_SHIFT 1
> +#define MT6359_DA_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_DBG0
> +#define MT6359_DA_VMODEM_VOSEL_MASK 0x7F
> +#define MT6359_DA_VMODEM_VOSEL_SHIFT 0
> +#define MT6359_DA_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_DBG1
> +#define MT6359_RG_BUCK_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_ELR0
> +#define MT6359_RG_BUCK_VMODEM_VOSEL_MASK 0x7F
> +#define MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT 0
> +#define MT6359_RG_BUCK_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_CON0
> +#define MT6359_RG_BUCK_VPROC1_LP_ADDR MT6359_BUCK_VPROC1_CON0
> +#define MT6359_RG_BUCK_VPROC1_LP_SHIFT 1
> +#define MT6359_DA_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_DBG0
> +#define MT6359_DA_VPROC1_VOSEL_MASK 0x7F
> +#define MT6359_DA_VPROC1_VOSEL_SHIFT 0
> +#define MT6359_DA_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_DBG1
> +#define MT6359_RG_BUCK_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_ELR0
> +#define MT6359_RG_BUCK_VPROC1_VOSEL_MASK 0x7F
> +#define MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT 0
> +#define MT6359_RG_BUCK_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_CON0
> +#define MT6359_RG_BUCK_VPROC2_LP_ADDR MT6359_BUCK_VPROC2_CON0
> +#define MT6359_RG_BUCK_VPROC2_LP_SHIFT 1
> +#define MT6359_DA_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_DBG0
> +#define MT6359_DA_VPROC2_VOSEL_MASK 0x7F
> +#define MT6359_DA_VPROC2_VOSEL_SHIFT 0
> +#define MT6359_DA_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_DBG1
> +#define MT6359_RG_BUCK_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_ELR0
> +#define MT6359_RG_BUCK_VPROC2_VOSEL_MASK 0x7F
> +#define MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT 0
> +#define MT6359_RG_BUCK_VS1_EN_ADDR MT6359_BUCK_VS1_CON0
> +#define MT6359_RG_BUCK_VS1_LP_ADDR MT6359_BUCK_VS1_CON0
> +#define MT6359_RG_BUCK_VS1_LP_SHIFT 1
> +#define MT6359_DA_VS1_VOSEL_ADDR MT6359_BUCK_VS1_DBG0
> +#define MT6359_DA_VS1_VOSEL_MASK 0x7F
> +#define MT6359_DA_VS1_VOSEL_SHIFT 0
> +#define MT6359_DA_VS1_EN_ADDR MT6359_BUCK_VS1_DBG1
> +#define MT6359_RG_BUCK_VS1_VOSEL_ADDR MT6359_BUCK_VS1_ELR0
> +#define MT6359_RG_BUCK_VS1_VOSEL_MASK 0x7F
> +#define MT6359_RG_BUCK_VS1_VOSEL_SHIFT 0
> +#define MT6359_RG_BUCK_VS2_EN_ADDR MT6359_BUCK_VS2_CON0
> +#define MT6359_RG_BUCK_VS2_LP_ADDR MT6359_BUCK_VS2_CON0
> +#define MT6359_RG_BUCK_VS2_LP_SHIFT 1
> +#define MT6359_DA_VS2_VOSEL_ADDR MT6359_BUCK_VS2_DBG0
> +#define MT6359_DA_VS2_VOSEL_MASK 0x7F
> +#define MT6359_DA_VS2_VOSEL_SHIFT 0
> +#define MT6359_DA_VS2_EN_ADDR MT6359_BUCK_VS2_DBG1
> +#define MT6359_RG_BUCK_VS2_VOSEL_ADDR MT6359_BUCK_VS2_ELR0
> +#define MT6359_RG_BUCK_VS2_VOSEL_MASK 0x7F
> +#define MT6359_RG_BUCK_VS2_VOSEL_SHIFT 0
> +#define MT6359_RG_BUCK_VPA_EN_ADDR MT6359_BUCK_VPA_CON0
> +#define MT6359_RG_BUCK_VPA_LP_ADDR MT6359_BUCK_VPA_CON0
> +#define MT6359_RG_BUCK_VPA_LP_SHIFT 1
> +#define MT6359_RG_BUCK_VPA_VOSEL_ADDR MT6359_BUCK_VPA_CON1
> +#define MT6359_RG_BUCK_VPA_VOSEL_MASK 0x3F
> +#define MT6359_RG_BUCK_VPA_VOSEL_SHIFT 0
> +#define MT6359_DA_VPA_VOSEL_ADDR MT6359_BUCK_VPA_DBG0
> +#define MT6359_DA_VPA_VOSEL_MASK 0x3F
> +#define MT6359_DA_VPA_VOSEL_SHIFT 0
> +#define MT6359_DA_VPA_EN_ADDR MT6359_BUCK_VPA_DBG1
> +#define MT6359_RG_VGPU11_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON2
> +#define MT6359_RG_VGPU11_FCCM_SHIFT 9
> +#define MT6359_RG_VCORE_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON13
> +#define MT6359_RG_VCORE_FCCM_SHIFT 5
> +#define MT6359_RG_VPROC1_FCCM_ADDR MT6359_VPROC1_ANA_CON3
> +#define MT6359_RG_VPROC1_FCCM_SHIFT 1
> +#define MT6359_RG_VPROC2_FCCM_ADDR MT6359_VPROC2_ANA_CON3
> +#define MT6359_RG_VPROC2_FCCM_SHIFT 1
> +#define MT6359_RG_VMODEM_FCCM_ADDR MT6359_VMODEM_ANA_CON3
> +#define MT6359_RG_VMODEM_FCCM_SHIFT 1
> +#define MT6359_RG_VPU_FCCM_ADDR MT6359_VPU_ANA_CON3
> +#define MT6359_RG_VPU_FCCM_SHIFT 1
> +#define MT6359_RG_VS1_FPWM_ADDR MT6359_VS1_ANA_CON0
> +#define MT6359_RG_VS1_FPWM_SHIFT 3
> +#define MT6359_RG_VS2_FPWM_ADDR MT6359_VS2_ANA_CON0
> +#define MT6359_RG_VS2_FPWM_SHIFT 3
> +#define MT6359_RG_VPA_MODESET_ADDR MT6359_VPA_ANA_CON0
> +#define MT6359_RG_VPA_MODESET_SHIFT 1
> +#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_ADDR MT6359_LDO_VSRAM_PROC1_ELR
> +#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK 0x7F
> +#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT 0
> +#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_ADDR MT6359_LDO_VSRAM_PROC2_ELR
> +#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK 0x7F
> +#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT 0
> +#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_ELR
> +#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F
> +#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT 0
> +#define MT6359_RG_LDO_VSRAM_MD_VOSEL_ADDR MT6359_LDO_VSRAM_MD_ELR
> +#define MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK 0x7F
> +#define MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT 0
> +#define MT6359_RG_LDO_VFE28_EN_ADDR MT6359_LDO_VFE28_CON0
> +#define MT6359_DA_VFE28_B_EN_ADDR MT6359_LDO_VFE28_MON
> +#define MT6359_RG_LDO_VXO22_EN_ADDR MT6359_LDO_VXO22_CON0
> +#define MT6359_RG_LDO_VXO22_EN_SHIFT 0
> +#define MT6359_DA_VXO22_B_EN_ADDR MT6359_LDO_VXO22_MON
> +#define MT6359_RG_LDO_VRF18_EN_ADDR MT6359_LDO_VRF18_CON0
> +#define MT6359_RG_LDO_VRF18_EN_SHIFT 0
> +#define MT6359_DA_VRF18_B_EN_ADDR MT6359_LDO_VRF18_MON
> +#define MT6359_RG_LDO_VRF12_EN_ADDR MT6359_LDO_VRF12_CON0
> +#define MT6359_RG_LDO_VRF12_EN_SHIFT 0
> +#define MT6359_DA_VRF12_B_EN_ADDR MT6359_LDO_VRF12_MON
> +#define MT6359_RG_LDO_VEFUSE_EN_ADDR MT6359_LDO_VEFUSE_CON0
> +#define MT6359_RG_LDO_VEFUSE_EN_SHIFT 0
> +#define MT6359_DA_VEFUSE_B_EN_ADDR MT6359_LDO_VEFUSE_MON
> +#define MT6359_RG_LDO_VCN33_1_EN_0_ADDR MT6359_LDO_VCN33_1_CON0
> +#define MT6359_RG_LDO_VCN33_1_EN_0_MASK 0x1
> +#define MT6359_RG_LDO_VCN33_1_EN_0_SHIFT 0
> +#define MT6359_DA_VCN33_1_B_EN_ADDR MT6359_LDO_VCN33_1_MON
> +#define MT6359_RG_LDO_VCN33_1_EN_1_ADDR MT6359_LDO_VCN33_1_MULTI_SW
> +#define MT6359_RG_LDO_VCN33_1_EN_1_SHIFT 15
> +#define MT6359_RG_LDO_VCN33_2_EN_0_ADDR MT6359_LDO_VCN33_2_CON0
> +#define MT6359_RG_LDO_VCN33_2_EN_0_SHIFT 0
> +#define MT6359_DA_VCN33_2_B_EN_ADDR MT6359_LDO_VCN33_2_MON
> +#define MT6359_RG_LDO_VCN33_2_EN_1_ADDR MT6359_LDO_VCN33_2_MULTI_SW
> +#define MT6359_RG_LDO_VCN33_2_EN_1_MASK 0x1
> +#define MT6359_RG_LDO_VCN33_2_EN_1_SHIFT 15
> +#define MT6359_RG_LDO_VCN13_EN_ADDR MT6359_LDO_VCN13_CON0
> +#define MT6359_RG_LDO_VCN13_EN_SHIFT 0
> +#define MT6359_DA_VCN13_B_EN_ADDR MT6359_LDO_VCN13_MON
> +#define MT6359_RG_LDO_VCN18_EN_ADDR MT6359_LDO_VCN18_CON0
> +#define MT6359_DA_VCN18_B_EN_ADDR MT6359_LDO_VCN18_MON
> +#define MT6359_RG_LDO_VA09_EN_ADDR MT6359_LDO_VA09_CON0
> +#define MT6359_RG_LDO_VA09_EN_SHIFT 0
> +#define MT6359_DA_VA09_B_EN_ADDR MT6359_LDO_VA09_MON
> +#define MT6359_RG_LDO_VCAMIO_EN_ADDR MT6359_LDO_VCAMIO_CON0
> +#define MT6359_RG_LDO_VCAMIO_EN_SHIFT 0
> +#define MT6359_DA_VCAMIO_B_EN_ADDR MT6359_LDO_VCAMIO_MON
> +#define MT6359_RG_LDO_VA12_EN_ADDR MT6359_LDO_VA12_CON0
> +#define MT6359_RG_LDO_VA12_EN_SHIFT 0
> +#define MT6359_DA_VA12_B_EN_ADDR MT6359_LDO_VA12_MON
> +#define MT6359_RG_LDO_VAUX18_EN_ADDR MT6359_LDO_VAUX18_CON0
> +#define MT6359_DA_VAUX18_B_EN_ADDR MT6359_LDO_VAUX18_MON
> +#define MT6359_RG_LDO_VAUD18_EN_ADDR MT6359_LDO_VAUD18_CON0
> +#define MT6359_DA_VAUD18_B_EN_ADDR MT6359_LDO_VAUD18_MON
> +#define MT6359_RG_LDO_VIO18_EN_ADDR MT6359_LDO_VIO18_CON0
> +#define MT6359_RG_LDO_VIO18_EN_SHIFT 0
> +#define MT6359_DA_VIO18_B_EN_ADDR MT6359_LDO_VIO18_MON
> +#define MT6359_RG_LDO_VEMC_EN_ADDR MT6359_LDO_VEMC_CON0
> +#define MT6359_RG_LDO_VEMC_EN_SHIFT 0
> +#define MT6359_DA_VEMC_B_EN_ADDR MT6359_LDO_VEMC_MON
> +#define MT6359_RG_LDO_VSIM1_EN_ADDR MT6359_LDO_VSIM1_CON0
> +#define MT6359_RG_LDO_VSIM1_EN_SHIFT 0
> +#define MT6359_DA_VSIM1_B_EN_ADDR MT6359_LDO_VSIM1_MON
> +#define MT6359_RG_LDO_VSIM2_EN_ADDR MT6359_LDO_VSIM2_CON0
> +#define MT6359_RG_LDO_VSIM2_EN_SHIFT 0
> +#define MT6359_DA_VSIM2_B_EN_ADDR MT6359_LDO_VSIM2_MON
> +#define MT6359_RG_LDO_VUSB_EN_0_ADDR MT6359_LDO_VUSB_CON0
> +#define MT6359_RG_LDO_VUSB_EN_0_MASK 0x1
> +#define MT6359_RG_LDO_VUSB_EN_0_SHIFT 0
> +#define MT6359_DA_VUSB_B_EN_ADDR MT6359_LDO_VUSB_MON
> +#define MT6359_RG_LDO_VUSB_EN_1_ADDR MT6359_LDO_VUSB_MULTI_SW
> +#define MT6359_RG_LDO_VUSB_EN_1_MASK 0x1
> +#define MT6359_RG_LDO_VUSB_EN_1_SHIFT 15
> +#define MT6359_RG_LDO_VRFCK_EN_ADDR MT6359_LDO_VRFCK_CON0
> +#define MT6359_RG_LDO_VRFCK_EN_SHIFT 0
> +#define MT6359_DA_VRFCK_B_EN_ADDR MT6359_LDO_VRFCK_MON
> +#define MT6359_RG_LDO_VBBCK_EN_ADDR MT6359_LDO_VBBCK_CON0
> +#define MT6359_RG_LDO_VBBCK_EN_SHIFT 0
> +#define MT6359_DA_VBBCK_B_EN_ADDR MT6359_LDO_VBBCK_MON
> +#define MT6359_RG_LDO_VBIF28_EN_ADDR MT6359_LDO_VBIF28_CON0
> +#define MT6359_DA_VBIF28_B_EN_ADDR MT6359_LDO_VBIF28_MON
> +#define MT6359_RG_LDO_VIBR_EN_ADDR MT6359_LDO_VIBR_CON0
> +#define MT6359_RG_LDO_VIBR_EN_SHIFT 0
> +#define MT6359_DA_VIBR_B_EN_ADDR MT6359_LDO_VIBR_MON
> +#define MT6359_RG_LDO_VIO28_EN_ADDR MT6359_LDO_VIO28_CON0
> +#define MT6359_RG_LDO_VIO28_EN_SHIFT 0
> +#define MT6359_DA_VIO28_B_EN_ADDR MT6359_LDO_VIO28_MON
> +#define MT6359_RG_LDO_VM18_EN_ADDR MT6359_LDO_VM18_CON0
> +#define MT6359_RG_LDO_VM18_EN_SHIFT 0
> +#define MT6359_DA_VM18_B_EN_ADDR MT6359_LDO_VM18_MON
> +#define MT6359_RG_LDO_VUFS_EN_ADDR MT6359_LDO_VUFS_CON0
> +#define MT6359_RG_LDO_VUFS_EN_SHIFT 0
> +#define MT6359_DA_VUFS_B_EN_ADDR MT6359_LDO_VUFS_MON
> +#define MT6359_RG_LDO_VSRAM_PROC1_EN_ADDR MT6359_LDO_VSRAM_PROC1_CON0
> +#define MT6359_DA_VSRAM_PROC1_B_EN_ADDR MT6359_LDO_VSRAM_PROC1_MON
> +#define MT6359_DA_VSRAM_PROC1_VOSEL_ADDR MT6359_LDO_VSRAM_PROC1_VOSEL1
> +#define MT6359_DA_VSRAM_PROC1_VOSEL_MASK 0x7F
> +#define MT6359_DA_VSRAM_PROC1_VOSEL_SHIFT 8
> +#define MT6359_RG_LDO_VSRAM_PROC2_EN_ADDR MT6359_LDO_VSRAM_PROC2_CON0
> +#define MT6359_DA_VSRAM_PROC2_B_EN_ADDR MT6359_LDO_VSRAM_PROC2_MON
> +#define MT6359_DA_VSRAM_PROC2_VOSEL_ADDR MT6359_LDO_VSRAM_PROC2_VOSEL1
> +#define MT6359_DA_VSRAM_PROC2_VOSEL_MASK 0x7F
> +#define MT6359_DA_VSRAM_PROC2_VOSEL_SHIFT 8
> +#define MT6359_RG_LDO_VSRAM_OTHERS_EN_ADDR MT6359_LDO_VSRAM_OTHERS_CON0
> +#define MT6359_DA_VSRAM_OTHERS_B_EN_ADDR MT6359_LDO_VSRAM_OTHERS_MON
> +#define MT6359_DA_VSRAM_OTHERS_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_VOSEL1
> +#define MT6359_DA_VSRAM_OTHERS_VOSEL_MASK 0x7F
> +#define MT6359_DA_VSRAM_OTHERS_VOSEL_SHIFT 8
> +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR \
> + MT6359_LDO_VSRAM_OTHERS_SSHUB
> +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR \
> + MT6359_LDO_VSRAM_OTHERS_SSHUB
> +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F
> +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT 1
> +#define MT6359_RG_LDO_VSRAM_MD_EN_ADDR MT6359_LDO_VSRAM_MD_CON0
> +#define MT6359_DA_VSRAM_MD_B_EN_ADDR MT6359_LDO_VSRAM_MD_MON
> +#define MT6359_DA_VSRAM_MD_VOSEL_ADDR MT6359_LDO_VSRAM_MD_VOSEL1
> +#define MT6359_DA_VSRAM_MD_VOSEL_MASK 0x7F
> +#define MT6359_DA_VSRAM_MD_VOSEL_SHIFT 8
> +#define MT6359_RG_VCN33_1_VOSEL_ADDR MT6359_VCN33_1_ANA_CON0
> +#define MT6359_RG_VCN33_1_VOSEL_MASK 0xF
> +#define MT6359_RG_VCN33_1_VOSEL_SHIFT 8
> +#define MT6359_RG_VCN33_2_VOSEL_ADDR MT6359_VCN33_2_ANA_CON0
> +#define MT6359_RG_VCN33_2_VOSEL_MASK 0xF
> +#define MT6359_RG_VCN33_2_VOSEL_SHIFT 8
> +#define MT6359_RG_VEMC_VOSEL_ADDR MT6359_VEMC_ANA_CON0
> +#define MT6359_RG_VEMC_VOSEL_MASK 0xF
> +#define MT6359_RG_VEMC_VOSEL_SHIFT 8
> +#define MT6359_RG_VSIM1_VOSEL_ADDR MT6359_VSIM1_ANA_CON0
> +#define MT6359_RG_VSIM1_VOSEL_MASK 0xF
> +#define MT6359_RG_VSIM1_VOSEL_SHIFT 8
> +#define MT6359_RG_VSIM2_VOSEL_ADDR MT6359_VSIM2_ANA_CON0
> +#define MT6359_RG_VSIM2_VOSEL_MASK 0xF
> +#define MT6359_RG_VSIM2_VOSEL_SHIFT 8
> +#define MT6359_RG_VIO28_VOSEL_ADDR MT6359_VIO28_ANA_CON0
> +#define MT6359_RG_VIO28_VOSEL_MASK 0xF
> +#define MT6359_RG_VIO28_VOSEL_SHIFT 8
> +#define MT6359_RG_VIBR_VOSEL_ADDR MT6359_VIBR_ANA_CON0
> +#define MT6359_RG_VIBR_VOSEL_MASK 0xF
> +#define MT6359_RG_VIBR_VOSEL_SHIFT 8
> +#define MT6359_RG_VRF18_VOSEL_ADDR MT6359_VRF18_ANA_CON0
> +#define MT6359_RG_VRF18_VOSEL_MASK 0xF
> +#define MT6359_RG_VRF18_VOSEL_SHIFT 8
> +#define MT6359_RG_VEFUSE_VOSEL_ADDR MT6359_VEFUSE_ANA_CON0
> +#define MT6359_RG_VEFUSE_VOSEL_MASK 0xF
> +#define MT6359_RG_VEFUSE_VOSEL_SHIFT 8
> +#define MT6359_RG_VCAMIO_VOSEL_ADDR MT6359_VCAMIO_ANA_CON0
> +#define MT6359_RG_VCAMIO_VOSEL_MASK 0xF
> +#define MT6359_RG_VCAMIO_VOSEL_SHIFT 8
> +#define MT6359_RG_VIO18_VOSEL_ADDR MT6359_VIO18_ANA_CON0
> +#define MT6359_RG_VIO18_VOSEL_MASK 0xF
> +#define MT6359_RG_VIO18_VOSEL_SHIFT 8
> +#define MT6359_RG_VM18_VOSEL_ADDR MT6359_VM18_ANA_CON0
> +#define MT6359_RG_VM18_VOSEL_MASK 0xF
> +#define MT6359_RG_VM18_VOSEL_SHIFT 8
> +#define MT6359_RG_VUFS_VOSEL_ADDR MT6359_VUFS_ANA_CON0
> +#define MT6359_RG_VUFS_VOSEL_MASK 0xF
> +#define MT6359_RG_VUFS_VOSEL_SHIFT 8
> +#define MT6359_RG_VRF12_VOSEL_ADDR MT6359_VRF12_ANA_CON0
> +#define MT6359_RG_VRF12_VOSEL_MASK 0xF
> +#define MT6359_RG_VRF12_VOSEL_SHIFT 8
> +#define MT6359_RG_VCN13_VOSEL_ADDR MT6359_VCN13_ANA_CON0
> +#define MT6359_RG_VCN13_VOSEL_MASK 0xF
> +#define MT6359_RG_VCN13_VOSEL_SHIFT 8
> +#define MT6359_RG_VA09_VOSEL_ADDR MT6359_VA09_ANA_CON0
> +#define MT6359_RG_VA09_VOSEL_MASK 0xF
> +#define MT6359_RG_VA09_VOSEL_SHIFT 8
> +#define MT6359_RG_VA12_VOSEL_ADDR MT6359_VA12_ANA_CON0
> +#define MT6359_RG_VA12_VOSEL_MASK 0xF
> +#define MT6359_RG_VA12_VOSEL_SHIFT 8
> +#define MT6359_RG_VXO22_VOSEL_ADDR MT6359_VXO22_ANA_CON0
> +#define MT6359_RG_VXO22_VOSEL_MASK 0xF
> +#define MT6359_RG_VXO22_VOSEL_SHIFT 8
> +#define MT6359_RG_VRFCK_VOSEL_ADDR MT6359_VRFCK_ANA_CON0
> +#define MT6359_RG_VRFCK_VOSEL_MASK 0xF
> +#define MT6359_RG_VRFCK_VOSEL_SHIFT 8
> +#define MT6359_RG_VBBCK_VOSEL_ADDR MT6359_VBBCK_ANA_CON0
> +#define MT6359_RG_VBBCK_VOSEL_MASK 0xF
> +#define MT6359_RG_VBBCK_VOSEL_SHIFT 8
> +
> +#endif /* __MFD_MT6359_REGISTERS_H__ */
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [RESEND v2 2/4] mfd: Add for PMIC MT6359 registers definition
2020-06-16 9:58 ` Wen Su
@ 2020-06-16 13:18 ` Lee Jones
0 siblings, 0 replies; 7+ messages in thread
From: Lee Jones @ 2020-06-16 13:18 UTC (permalink / raw)
To: Wen Su
Cc: Mark Rutland, devicetree, wsd_upstream, linux-kernel,
Rob Herring, Liam Girdwood, Mark Brown, linux-mediatek,
Matthias Brugger, linux-arm-kernel
On Tue, 16 Jun 2020, Wen Su wrote:
> Dear Reviewers,
>
> I am sorry to bother you. How should I proceed for this patch set ?
> Since the regulator driver were applied and dropped because of the MFD
> header file dependency on this patch.
>
> Will this mfd registers definition patch and regulator driver patch be
> applied ? Please advice.
Once you have all of your Acks, it should be applied as a set.
Best thing you can do is submit a [RESEND].
> On Fri, 2020-02-21 at 10:39 +0800, Wen Su wrote:
> > From: "Wen Su" <wen.su@mediatek.com>
> >
> > This adds MediaTek PMIC MT6359 registers definition for the
> > following sub modules:
> >
> > - Regulator
> > - RTC
> > - Interrupt
> >
> > Signed-off-by: Wen Su <wen.su@mediatek.com>
> > Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
> > ---
> > include/linux/mfd/mt6359/registers.h | 531 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 531 insertions(+)
> > create mode 100644 include/linux/mfd/mt6359/registers.h
--
Lee Jones [李琼斯]
Senior Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-06-16 13:18 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-21 2:39 [RESEND v2 0/4] Add Support for MediaTek PMIC MT6359 Regulator Wen Su
2020-02-21 2:39 ` [RESEND v2 1/4] dt-bindings: regulator: Add document for MT6359 regulator Wen Su
2020-02-21 2:39 ` [RESEND v2 2/4] mfd: Add for PMIC MT6359 registers definition Wen Su
2020-06-16 9:58 ` Wen Su
2020-06-16 13:18 ` Lee Jones
2020-02-21 2:39 ` [RESEND v2 3/4] regulator: mt6359: Add support for MT6359 regulator Wen Su
2020-02-21 2:39 ` [RESEND v2 4/4] arm64: dts: mt6359: add PMIC MT6359 related nodes Wen Su
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