[PATCH v2 0/9] Add MediaTek SoC DRM (vdosys0) support for mt8195

[PATCH v2 0/9] Add MediaTek SoC DRM (vdosys0) support for mt8195

[jason-jh.lin]

The hardware path of vdosys0 with eDP panel output need to go through
by several modules, such as, OVL, RDMA, COLOR, CCORR, AAL, GAMMA,
DITHER, DSC and MERGE.

Add DRM and these modules support by the patches below:

jason-jh.lin (9):
  dt-bindings: mediatek: add definition for mt8195 display
  dt-bindings: mediatek: add DSC definition for mt8195
  dt-bindings: arm: mediatek: add definition for mt8195 mmsys
  arm64: dts: mt8195: add display node for vdosys0
  soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  soc: mediatek: add mtk-mutex support for mt8195 vdosys0
  drm/mediatek: add mediatek-drm of vdosys0 support for MT8195
  drm/mediatek: add DSC support for MT8195
  drm/mediatek: add MERGE support for MT8195

 .../bindings/arm/mediatek/mediatek,mmsys.txt  |  15 +
 .../display/mediatek/mediatek,disp.txt        |   9 +-
 .../display/mediatek/mediatek,dsc.yaml        |  57 ++
 arch/arm64/boot/dts/mediatek/mt8195.dtsi      | 111 ++++
 drivers/gpu/drm/mediatek/Makefile             |   2 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |  16 +
 drivers/gpu/drm/mediatek/mtk_disp_dsc.c       | 205 +++++++
 drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 525 ++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
 drivers/gpu/drm/mediatek/mtk_drm_crtc.h       |  14 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  29 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  32 ++
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   2 +
 drivers/soc/mediatek/mt8195-mmsys.h           | 191 +++++++
 drivers/soc/mediatek/mtk-mmsys.c              |  11 +
 drivers/soc/mediatek/mtk-mutex.c              | 107 +++-
 include/linux/soc/mediatek/mtk-mmsys.h        |  10 +
 18 files changed, 1337 insertions(+), 7 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_dsc.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

-- 
2.18.0
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[PATCH v2 1/9] dt-bindings: mediatek: add definition for mt8195 display

[jason-jh.lin]

Add definition for mt8195 display.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 .../bindings/display/mediatek/mediatek,disp.txt          | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index fbb59c9ddda6..de6226d4bca3 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -37,6 +37,7 @@ Required properties (all function blocks):
 	"mediatek,<chip>-disp-aal"   		- adaptive ambient light controller
 	"mediatek,<chip>-disp-gamma" 		- gamma correction
 	"mediatek,<chip>-disp-merge" 		- merge streams from two RDMA sources
+	"mediatek,<chip>-disp-dsc"   		- DSC controller, see mediatek,dsc.yaml
 	"mediatek,<chip>-disp-postmask" 	- control round corner for display frame
 	"mediatek,<chip>-disp-split" 		- split stream to two encoders
 	"mediatek,<chip>-disp-ufoe"  		- data compression engine
@@ -44,7 +45,7 @@ Required properties (all function blocks):
 	"mediatek,<chip>-dpi"        		- DPI controller, see mediatek,dpi.txt
 	"mediatek,<chip>-disp-mutex" 		- display mutex
 	"mediatek,<chip>-disp-od"    		- overdrive
-  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
+  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183, mt8192 and mt8195.
 - reg: Physical base address and length of the function block register space
 - interrupts: The interrupt signal from the function block (required, except for
   merge and split function blocks).
@@ -60,7 +61,7 @@ Required properties (DMA function blocks):
 	"mediatek,<chip>-disp-ovl"
 	"mediatek,<chip>-disp-rdma"
 	"mediatek,<chip>-disp-wdma"
-  the supported chips are mt2701, mt8167 and mt8173.
+  the supported chips are mt2701, mt8167, mt8173 and mt8195.
 - larb: Should contain a phandle pointing to the local arbiter device as defined
   in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
 - iommus: Should point to the respective IOMMU block with master port as
@@ -217,3 +218,7 @@ od@14023000 {
 	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 	clocks = <&mmsys CLK_MM_DISP_OD>;
 };
+
+dsc0: disp_dsc_wrap@1c009000 {
+	/* See mediatek,dsc.yaml for details */
+};
-- 
2.18.0
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Re: [PATCH v2 1/9] dt-bindings: mediatek: add definition for mt8195 display

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
>
> Add definition for mt8195 display.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  .../bindings/display/mediatek/mediatek,disp.txt          | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index fbb59c9ddda6..de6226d4bca3 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -37,6 +37,7 @@ Required properties (all function blocks):
>         "mediatek,<chip>-disp-aal"              - adaptive ambient light controller
>         "mediatek,<chip>-disp-gamma"            - gamma correction
>         "mediatek,<chip>-disp-merge"            - merge streams from two RDMA sources
> +       "mediatek,<chip>-disp-dsc"              - DSC controller, see mediatek,dsc.yaml

You add dsc binding document in yaml format, so I would like you to
change this binding document to yaml format.

Regards,
Chun-Kuang.

>         "mediatek,<chip>-disp-postmask"         - control round corner for display frame
>         "mediatek,<chip>-disp-split"            - split stream to two encoders
>         "mediatek,<chip>-disp-ufoe"             - data compression engine
> @@ -44,7 +45,7 @@ Required properties (all function blocks):
>         "mediatek,<chip>-dpi"                   - DPI controller, see mediatek,dpi.txt
>         "mediatek,<chip>-disp-mutex"            - display mutex
>         "mediatek,<chip>-disp-od"               - overdrive
> -  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
> +  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183, mt8192 and mt8195.
>  - reg: Physical base address and length of the function block register space
>  - interrupts: The interrupt signal from the function block (required, except for
>    merge and split function blocks).
> @@ -60,7 +61,7 @@ Required properties (DMA function blocks):
>         "mediatek,<chip>-disp-ovl"
>         "mediatek,<chip>-disp-rdma"
>         "mediatek,<chip>-disp-wdma"
> -  the supported chips are mt2701, mt8167 and mt8173.
> +  the supported chips are mt2701, mt8167, mt8173 and mt8195.
>  - larb: Should contain a phandle pointing to the local arbiter device as defined
>    in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
>  - iommus: Should point to the respective IOMMU block with master port as
> @@ -217,3 +218,7 @@ od@14023000 {
>         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
>         clocks = <&mmsys CLK_MM_DISP_OD>;
>  };
> +
> +dsc0: disp_dsc_wrap@1c009000 {
> +       /* See mediatek,dsc.yaml for details */
> +};
> --
> 2.18.0
>

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Re: [PATCH v2 1/9] dt-bindings: mediatek: add definition for mt8195 display

[Jason-JH Lin]

On Sun, 2021-07-11 at 09:21 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
> > 
> > Add definition for mt8195 display.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  .../bindings/display/mediatek/mediatek,disp.txt          | 9
> > +++++++--
> >  1 file changed, 7 insertions(+), 2 deletions(-)
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > txt
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > txt
> > index fbb59c9ddda6..de6226d4bca3 100644
> > ---
> > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > txt
> > +++
> > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.
> > txt
> > @@ -37,6 +37,7 @@ Required properties (all function blocks):
> >         "mediatek,<chip>-disp-aal"              - adaptive ambient
> > light controller
> >         "mediatek,<chip>-disp-gamma"            - gamma correction
> >         "mediatek,<chip>-disp-merge"            - merge streams
> > from two RDMA sources
> > +       "mediatek,<chip>-disp-dsc"              - DSC controller,
> > see mediatek,dsc.yaml
> 
> You add dsc binding document in yaml format, so I would like you to
> change this binding document to yaml format.
> 
> Regards,
> Chun-Kuang.
> 
Hi CK,

OK, I will change this binding document to yaml format at the next
version.

Regards,
Jason-JH.Lin
> >         "mediatek,<chip>-disp-postmask"         - control round
> > corner for display frame
> >         "mediatek,<chip>-disp-split"            - split stream to
> > two encoders
> >         "mediatek,<chip>-disp-ufoe"             - data compression
> > engine
> > @@ -44,7 +45,7 @@ Required properties (all function blocks):
> >         "mediatek,<chip>-dpi"                   - DPI controller,
> > see mediatek,dpi.txt
> >         "mediatek,<chip>-disp-mutex"            - display mutex
> >         "mediatek,<chip>-disp-od"               - overdrive
> > -  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173,
> > mt8183 and mt8192.
> > +  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173,
> > mt8183, mt8192 and mt8195.
> >  - reg: Physical base address and length of the function block
> > register space
> >  - interrupts: The interrupt signal from the function block
> > (required, except for
> >    merge and split function blocks).
> > @@ -60,7 +61,7 @@ Required properties (DMA function blocks):
> >         "mediatek,<chip>-disp-ovl"
> >         "mediatek,<chip>-disp-rdma"
> >         "mediatek,<chip>-disp-wdma"
> > -  the supported chips are mt2701, mt8167 and mt8173.
> > +  the supported chips are mt2701, mt8167, mt8173 and mt8195.
> >  - larb: Should contain a phandle pointing to the local arbiter
> > device as defined
> >    in Documentation/devicetree/bindings/memory-
> > controllers/mediatek,smi-larb.yaml
> >  - iommus: Should point to the respective IOMMU block with master
> > port as
> > @@ -217,3 +218,7 @@ od@14023000 {
> >         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> >         clocks = <&mmsys CLK_MM_DISP_OD>;
> >  };
> > +
> > +dsc0: disp_dsc_wrap@1c009000 {
> > +       /* See mediatek,dsc.yaml for details */
> > +};
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>
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[PATCH v2 2/9] dt-bindings: mediatek: add DSC definition for mt8195

[jason-jh.lin]

Add DSC definition file for mt8195 display.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 .../display/mediatek/mediatek,dsc.yaml        | 57 +++++++++++++++++++
 1 file changed, 57 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
new file mode 100644
index 000000000000..85ee0d85e77e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek DSC Controller Device Tree Bindings
+
+maintainers:
+  - CK Hu <ck.hu@mediatek.com>
+  - Jitao shi <jitao.shi@mediatek.com>
+  - Jason-JH Lin <jason-jh.lin@mediatek.com>
+
+description: |
+  The DSC Standard is a specification of the algorithms used for
+  compressing and decompressing image display streams, including
+  the specification of the syntax and semantics of the compressed
+  video bit stream. DSC is designed for real-time systems, with
+  real-time compression, transmission, decompression, and Display.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt8195-disp-dsc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: DSC Wrapper Clock
+
+  clock-names:
+    items:
+      - const: DSC_WRAP0
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    dsc0: disp_dsc_wrap@1c009000 {
+        compatible = "mediatek,mt8195-disp-dsc";
+        reg = <0 0x1c009000 0 0x1000>;
+        interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+        clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+    };
+
+...
-- 
2.18.0
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[PATCH v2 3/9] dt-bindings: arm: mediatek: add definition for mt8195 mmsys

[jason-jh.lin]

There are 2 display hardware path in mt8195, namely vdosys0 and vdosys1,
so add their definition in mtk-mmsys documentation.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,mmsys.txt      | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
index 9712a6831fab..be1761010d3c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
@@ -17,6 +17,8 @@ Required Properties:
 	- "mediatek,mt8173-mmsys", "syscon"
 	- "mediatek,mt8183-mmsys", "syscon"
 	- "mediatek,mt8192-mmsys", "syscon"
+	- "mediatek,mt8195-vdosys0", "syscon"
+	- "mediatek,mt8195-vdosys1", "syscon"
 - #clock-cells: Must be 1
 
 For the clock control, the mmsys controller uses the common clk binding from
@@ -30,3 +32,16 @@ mmsys: syscon@14000000 {
 	reg = <0 0x14000000 0 0x1000>;
 	#clock-cells = <1>;
 };
+
+vdosys0: syscon@1c01a000 {
+	compatible = "mediatek,mt8195-vdosys0", "syscon";
+	reg = <0 0x1c01a000 0 0x1000>;
+	#clock-cells = <1>;
+};
+
+vdosys1: syscon@1c100000 {
+	compatible = "mediatek,mt8195-vdosys1", "syscon";
+	reg = <0 0x1c100000 0 0x1000>;
+	#clock-cells = <1>;
+};
+
-- 
2.18.0
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[PATCH v2 4/9] arm64: dts: mt8195: add display node for vdosys0

[jason-jh.lin]

Add display node for vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 111 +++++++++++++++++++++++
 1 file changed, 111 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index c10b48ef455f..d30b3b9545e2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1155,9 +1155,120 @@
 			#clock-cells = <1>;
 		};
 
+		ovl0: disp_ovl@1c000000 {
+			compatible = "mediatek,mt8195-disp-ovl",
+				     "mediatek,mt8183-disp-ovl";
+			reg = <0 0x1c000000 0 0x1000>;
+			interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x0000 0x1000>;
+		};
+
+		rdma0: disp_rdma@1c002000 {
+			compatible = "mediatek,mt8195-disp-rdma";
+			reg = <0 0x1c002000 0 0x1000>;
+			interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x2000 0x1000>;
+		};
+
+		color0: disp_color@1c003000 {
+			compatible = "mediatek,mt8195-disp-color",
+				     "mediatek,mt8173-disp-color";
+			reg = <0 0x1c003000 0 0x1000>;
+			interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x3000 0x1000>;
+		};
+
+		ccorr0: disp_ccorr@1c004000 {
+			compatible = "mediatek,mt8195-disp-ccorr",
+				     "mediatek,mt8183-disp-ccorr";
+			reg = <0 0x1c004000 0 0x1000>;
+			interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x4000 0x1000>;
+		};
+
+		aal0: disp_aal@1c005000 {
+			compatible = "mediatek,mt8195-disp-aal",
+				     "mediatek,mt8173-disp-aal";
+			reg = <0 0x1c005000 0 0x1000>;
+			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x5000 0x1000>;
+		};
+
+		gamma0: disp_gamma@1c006000 {
+			compatible = "mediatek,mt8195-disp-gamma",
+				     "mediatek,mt8173-disp-gamma";
+			reg = <0 0x1c006000 0 0x1000>;
+			interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x6000 0x1000>;
+		};
+
+		dither0: disp_dither@1c007000 {
+			compatible = "mediatek,mt8195-disp-dither",
+				     "mediatek,mt8183-disp-dither";
+			reg = <0 0x1c007000 0 0x1000>;
+			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x7000 0x1000>;
+		};
+
+		dsc0: disp_dsc_wrap@1c009000 {
+			compatible = "mediatek,mt8195-disp-dsc";
+			reg = <0 0x1c009000 0 0x1000>;
+			interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+		};
+
+		merge0: disp_vpp_merge0@1c014000 {
+			compatible = "mediatek,mt8195-disp-merge";
+			reg = <0 0x1c014000 0 0x1000>;
+			interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
+			mediatek,gce-client-reg =
+				 <&gce1 SUBSYS_1c01XXXX 0x4000 0x1000>;
+		};
+
+		mutex: disp_mutex0@1c016000 {
+			compatible = "mediatek,mt8195-disp-mutex";
+			reg = <0 0x1c016000 0 0x1000>;
+			reg-names = "vdo0_mutex";
+			interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+			clock-names = "vdo0_mutex";
+			mediatek,gce-events =
+				 <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+		};
+
 		vdosys0: syscon@1c01a000 {
 			compatible = "mediatek,mt8195-vdosys0", "syscon";
 			reg = <0 0x1c01a000 0 0x1000>;
+			mboxes = <&gce1 0 0 CMDQ_THR_PRIO_4>;
 			#clock-cells = <1>;
 		};
 
-- 
2.18.0
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[PATCH v2 5/9] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[jason-jh.lin]

Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/soc/mediatek/mt8195-mmsys.h    | 191 +++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c       |  11 ++
 include/linux/soc/mediatek/mtk-mmsys.h |  10 ++
 3 files changed, 212 insertions(+)
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..73e9e8286d50
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN					0xf14
+#define MOUT_DISP_OVL0_TO_DISP_RDMA0				BIT(0)
+#define MOUT_DISP_OVL0_TO_DISP_WDMA0				BIT(1)
+#define MOUT_DISP_OVL0_TO_DISP_OVL1				BIT(2)
+#define MOUT_DISP_OVL1_TO_DISP_RDMA1				BIT(4)
+#define MOUT_DISP_OVL1_TO_DISP_WDMA1				BIT(5)
+#define MOUT_DISP_OVL1_TO_DISP_OVL0				BIT(6)
+
+#define MT8195_VDO0_SEL_IN					0xf34
+#define SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT			(0 << 0)
+#define SEL_IN_VPP_MERGE_FROM_DISP_DITHER1			(1 << 0)
+#define SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0			(2 << 0)
+#define SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0			(0 << 4)
+#define SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE			(1 << 4)
+#define SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1			(0 << 5)
+#define SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE			(1 << 5)
+#define SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE			(0 << 8)
+#define SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT			(1 << 8)
+#define SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT			(0 << 9)
+#define SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT			(0 << 12)
+#define SEL_IN_DP_INTF0_FROM_VPP_MERGE				(1 << 12)
+#define SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0			(2 << 12)
+#define SEL_IN_DSI0_FROM_DSC_WRAP0_OUT				(0 << 16)
+#define SEL_IN_DSI0_FROM_DISP_DITHER0				(1 << 16)
+#define SEL_IN_DSI1_FROM_DSC_WRAP1_OUT				(0 << 17)
+#define SEL_IN_DSI1_FROM_VPP_MERGE				(1 << 17)
+#define SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 << 20)
+#define SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 << 20)
+#define SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN			(0 << 21)
+#define SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1			(1 << 21)
+#define SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 << 22)
+#define SEL_IN_DISP_WDMA0_FROM_VPP_MERGE			(1 << 22)
+
+#define MT8195_VDO0_SEL_OUT					0xf38
+#define SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN			(0 << 0)
+#define SOUT_DISP_DITHER0_TO_DSI0				(1 << 0)
+#define SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN			(0 << 1)
+#define SOUT_DISP_DITHER1_TO_VPP_MERGE				(1 << 1)
+#define SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT			(2 << 1)
+#define SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE				(0 << 4)
+#define SOUT_VDO1_VIRTUAL0_TO_DP_INTF0				(1 << 4)
+#define SOUT_VPP_MERGE_TO_DSI1					(0 << 8)
+#define SOUT_VPP_MERGE_TO_DP_INTF0				(1 << 8)
+#define SOUT_VPP_MERGE_TO_SINA_VIRTUAL0				(2 << 8)
+#define SOUT_VPP_MERGE_TO_DISP_WDMA1				(3 << 8)
+#define SOUT_VPP_MERGE_TO_DSC_WRAP0_IN				(4 << 8)
+#define SOUT_VPP_MERGE_TO_DSC_WRAP1_IN				(0 << 11)
+#define SOUT_VPP_MERGE_TO_DISP_WDMA0				(1 << 11)
+#define SOUT_DSC_WRAP0_OUT_TO_DSI0				(0 << 12)
+#define SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0			(1 << 12)
+#define SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE				(2 << 12)
+#define SOUT_DSC_WRAP1_OUT_TO_DSI1				(0 << 16)
+#define SOUT_DSC_WRAP1_OUT_TO_DP_INTF0				(1 << 16)
+#define SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0			(2 << 16)
+#define SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE				(3 << 16)
+
+#define MT8195_VDO1_VPP3_ASYNC_SOUT				0xf54
+#define SOUT_TO_VPP_MERGE0_P0_SEL				(0 << 0)
+#define SOUT_TO_VPP_MERGE0_P1_SEL				(1 << 0)
+
+#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL			0xf40
+#define SOUT_TO_HDR_VDO_FE0					(0 << 0)
+
+#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL			0xf44
+#define SOUT_TO_HDR_VDO_FE1					(0 << 0)
+
+#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL			0xf48
+#define SOUT_TO_HDR_GFX_FE0					(0 << 0)
+
+#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL			0xf4c
+#define SOUT_TO_HDR_GFX_FE1					(0 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SOUT_SEL				0xf58
+#define MIXER_IN1_SOUT_TO_DISP_MIXER				(0 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SOUT_SEL				0xf5c
+#define MIXER_IN2_SOUT_TO_DISP_MIXER				(0 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SOUT_SEL				0xf60
+#define MIXER_IN3_SOUT_TO_DISP_MIXER				(0 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SOUT_SEL				0xf64
+#define MIXER_IN4_SOUT_TO_DISP_MIXER				(0 << 0)
+
+#define MT8195_VDO1_MIXER_OUT_SOUT_SEL				0xf34
+#define MIXER_SOUT_TO_HDR_VDO_BE0				(0 << 0)
+
+#define MT8195_VDO1_MERGE4_SOUT_SEL				0xf18
+#define MERGE4_SOUT_TO_VDOSYS0					(0 << 0)
+#define MERGE4_SOUT_TO_DPI0_SEL					(1 << 0)
+#define MERGE4_SOUT_TO_DPI1_SEL					(2 << 0)
+#define MERGE4_SOUT_TO_DP_INTF0_SEL				(3 << 0)
+
+#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN			0xf04
+#define VPP_MERGE0_P0_SEL_IN_FROM_SVPP2				(0 << 0)
+#define VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0			(1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN			0xf08
+#define VPP_MERGE0_P1_SEL_IN_FROM_SVPP3				(0 << 0)
+#define VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1			(1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN			0xf3c
+#define VPP_MERGE1_P0_SEL_IN_FROM_VPP3_ASYNC_SOUT		(0 << 0)
+#define VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2			(1 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SEL_IN				0xf24
+#define MIXER_IN1_SEL_IN_FROM_HDR_VDO_FE0			(0 << 0)
+#define MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT			(1 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SEL_IN				0xf28
+#define MIXER_IN2_SEL_IN_FROM_HDR_VDO_FE1			(0 << 0)
+#define MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT			(1 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SEL_IN				0xf2c
+#define MIXER_IN3_SEL_IN_FROM_HDR_GFX_FE0			(0 << 0)
+#define MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT			(1 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SEL_IN				0xf30
+#define MIXER_IN4_SEL_IN_FROM_HDR_GFX_FE1			(0 << 0)
+#define MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT			(1 << 0)
+
+#define MT8195_VDO1_MIXER_SOUT_SEL_IN				0xf68
+#define MIXER_SOUT_SEL_IN_FROM_DISP_MIXER			(0 << 0)
+#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN1_SOUT			(1 << 0)
+#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN2_SOUT			(2 << 0)
+#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN3_SOUTR			(3 << 0)
+#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN4_SOUTR			(4 << 0)
+
+#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN				0xf50
+#define MERGE4_ASYNC_SEL_IN_FROM_HDR_VDO_BE0			(0 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT			(1 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MERGE0_ASYNC_SOUT		(2 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MERGE1_ASYNC_SOUT		(3 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MERGE2_ASYNC_SOUT		(4 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MERGE3_ASYNC_SOUT		(5 << 0)
+
+#define MT8195_VDO1_DISP_DPI0_SEL_IN				0xf0c
+#define DISP_DPI0_SEL_IN_FROM_VPP_MERGE4_MOUT			(0 << 0)
+#define DISP_DPI0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT		(1 << 0)
+#define DISP_DPI0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT		(2 << 0)
+
+#define MT8195_VDO1_DISP_DPI1_SEL_IN				0xf10
+#define DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT			(0 << 0)
+#define DISP_DPI1_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT		(1 << 0)
+#define DISP_DPI1_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT		(2 << 0)
+
+#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN			0xf14
+#define DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT		(0 << 0)
+#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT	(1 << 0)
+#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT	(2 << 0)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+	{
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+		MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL0_TO_DISP_RDMA0
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+		MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL1_TO_DISP_RDMA1
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_IN, SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_OUT, SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, DDP_COMPONENT_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+	}
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 080660ef11bf..1fb241750897 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -13,6 +13,7 @@
 #include "mtk-mmsys.h"
 #include "mt8167-mmsys.h"
 #include "mt8183-mmsys.h"
+#include "mt8195-mmsys.h"
 
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.clk_driver = "clk-mt2701-mm",
@@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.clk_driver = "clk-mt8195-vdo0",
+	.routes = mmsys_mt8195_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
 struct mtk_mmsys {
 	void __iomem *regs;
 	const struct mtk_mmsys_driver_data *data;
@@ -157,6 +164,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
 		.compatible = "mediatek,mt8183-mmsys",
 		.data = &mt8183_mmsys_driver_data,
 	},
+	{
+		.compatible = "mediatek,mt8195-vdosys0",
+		.data = &mt8195_vdosys0_driver_data,
+	},
 	{ }
 };
 
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6133da..34cb605e5df9 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -39,6 +39,16 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_UFOE,
 	DDP_COMPONENT_WDMA0,
 	DDP_COMPONENT_WDMA1,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_MERGE1,
+	DDP_COMPONENT_MERGE2,
+	DDP_COMPONENT_MERGE3,
+	DDP_COMPONENT_MERGE4,
+	DDP_COMPONENT_MERGE5,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_DSC1,
+	DDP_COMPONENT_DSC1_VIRTUAL0,
+	DDP_COMPONENT_DP_INTF0,
 	DDP_COMPONENT_ID_MAX,
 };
 
-- 
2.18.0
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[PATCH v2 6/9] soc: mediatek: add mtk-mutex support for mt8195 vdosys0

[jason-jh.lin]

Add mtk-mutex support for mt8195 vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/soc/mediatek/mtk-mutex.c | 107 +++++++++++++++++++++++++++++--
 1 file changed, 102 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2e4bcc300576..d74eb3f97f1d 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -17,6 +17,9 @@
 #define MT8183_MUTEX0_MOD0			0x30
 #define MT8183_MUTEX0_SOF0			0x2c
 
+#define MT8195_DISP_MUTEX0_MOD0			0x30
+#define MT8195_DISP_MUTEX0_SOF			0x2c
+
 #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
@@ -67,6 +70,36 @@
 #define MT8173_MUTEX_MOD_DISP_PWM1		24
 #define MT8173_MUTEX_MOD_DISP_OD		25
 
+#define MT8195_MUTEX_MOD_DISP_OVL0		0
+#define MT8195_MUTEX_MOD_DISP_WDMA0		1
+#define MT8195_MUTEX_MOD_DISP_RDMA0		2
+#define MT8195_MUTEX_MOD_DISP_COLOR0		3
+#define MT8195_MUTEX_MOD_DISP_CCORR0		4
+#define MT8195_MUTEX_MOD_DISP_AAL0		5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0		6
+#define MT8195_MUTEX_MOD_DISP_DITHER0		7
+#define MT8195_MUTEX_MOD_DISP_DSI0		8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	9
+#define MT8195_MUTEX_MOD_DISP_OVL1		10
+#define MT8195_MUTEX_MOD_DISP_WDMA1		11
+#define MT8195_MUTEX_MOD_DISP_RDMA1		12
+#define MT8195_MUTEX_MOD_DISP_COLOR1		13
+#define MT8195_MUTEX_MOD_DISP_CCORR1		14
+#define MT8195_MUTEX_MOD_DISP_AAL1		15
+#define MT8195_MUTEX_MOD_DISP_GAMMA1		16
+#define MT8195_MUTEX_MOD_DISP_DITHER1		17
+#define MT8195_MUTEX_MOD_DISP_DSI1		18
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1	19
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0	22
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1	23
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2	24
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3	25
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4	26
+#define MT8195_MUTEX_MOD_DISP_PWM0		27
+#define MT8195_MUTEX_MOD_DISP_PWM1		28
+
 #define MT2712_MUTEX_MOD_DISP_PWM2		10
 #define MT2712_MUTEX_MOD_DISP_OVL0		11
 #define MT2712_MUTEX_MOD_DISP_OVL1		12
@@ -101,11 +134,36 @@
 #define MT2712_MUTEX_SOF_DSI3			6
 #define MT8167_MUTEX_SOF_DPI0			2
 #define MT8167_MUTEX_SOF_DPI1			3
+
 #define MT8183_MUTEX_SOF_DSI0			1
 #define MT8183_MUTEX_SOF_DPI0			2
 
-#define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_SOF_DSI0 << 6)
-#define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8183_MUTEX_EOF_CONVERT(sof)	((sof) << 6)
+#define MT8183_MUTEX_EOF_DSI0 \
+	MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DSI0)
+#define MT8183_MUTEX_EOF_DPI0 \
+	MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DPI0)
+
+#define MT8195_MUTEX_SOF_DSI0			1
+#define MT8195_MUTEX_SOF_DSI1			2
+#define MT8195_MUTEX_SOF_DP_INTF0		3
+#define MT8195_MUTEX_SOF_DP_INTF1		4
+#define MT8195_MUTEX_SOF_DPI0			6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1			5 /* for digital video out */
+
+#define MT8195_MUTEX_EOF_CONVERT(sof)	((sof) << 7)
+#define MT8195_MUTEX_EOF_DSI0 \
+	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI0)
+#define MT8195_MUTEX_EOF_DSI1 \
+	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI1)
+#define MT8195_MUTEX_EOF_DP_INTF0 \
+	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF0)
+#define MT8195_MUTEX_EOF_DP_INTF1 \
+	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF1)
+#define MT8195_MUTEX_EOF_DPI0 \
+	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI0)
+#define MT8195_MUTEX_EOF_DPI1 \
+	MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI1)
 
 struct mtk_mutex {
 	int id;
@@ -120,6 +178,9 @@ enum mtk_mutex_sof_id {
 	MUTEX_SOF_DPI1,
 	MUTEX_SOF_DSI2,
 	MUTEX_SOF_DSI3,
+	MUTEX_SOF_DP_INTF0,
+	MUTEX_SOF_DP_INTF1,
+	DDP_MUTEX_SOF_MAX,
 };
 
 struct mtk_mutex_data {
@@ -214,7 +275,22 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
 };
 
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+	[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+	[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+	[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+	[DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+	[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+	[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -224,7 +300,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 	[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
 };
 
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -232,12 +308,24 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 };
 
 /* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
 };
 
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+	[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+	[MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+	[MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+	[MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+	[MUTEX_SOF_DP_INTF0] =
+		MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+	[MUTEX_SOF_DP_INTF1] =
+		MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
 	.mutex_mod = mt2701_mutex_mod,
 	.mutex_sof = mt2712_mutex_sof,
@@ -275,6 +363,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
 	.no_clk = true,
 };
 
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+	.mutex_mod = mt8195_mutex_mod,
+	.mutex_sof = mt8195_mutex_sof,
+	.mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+	.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
 struct mtk_mutex *mtk_mutex_get(struct device *dev)
 {
 	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -507,6 +602,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
 	  .data = &mt8173_mutex_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-mutex",
 	  .data = &mt8183_mutex_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = &mt8195_mutex_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
-- 
2.18.0
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Re: [PATCH v2 6/9] soc: mediatek: add mtk-mutex support for mt8195 vdosys0

[Matthias Brugger]

On 10/07/2021 13:38, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195 vdosys0.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/soc/mediatek/mtk-mutex.c | 107 +++++++++++++++++++++++++++++--
>  1 file changed, 102 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 2e4bcc300576..d74eb3f97f1d 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -17,6 +17,9 @@
>  #define MT8183_MUTEX0_MOD0			0x30
>  #define MT8183_MUTEX0_SOF0			0x2c
>  
> +#define MT8195_DISP_MUTEX0_MOD0			0x30
> +#define MT8195_DISP_MUTEX0_SOF			0x2c
> +
>  #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))
>  #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
>  #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
> @@ -67,6 +70,36 @@
>  #define MT8173_MUTEX_MOD_DISP_PWM1		24
>  #define MT8173_MUTEX_MOD_DISP_OD		25
>  
> +#define MT8195_MUTEX_MOD_DISP_OVL0		0
> +#define MT8195_MUTEX_MOD_DISP_WDMA0		1
> +#define MT8195_MUTEX_MOD_DISP_RDMA0		2
> +#define MT8195_MUTEX_MOD_DISP_COLOR0		3
> +#define MT8195_MUTEX_MOD_DISP_CCORR0		4
> +#define MT8195_MUTEX_MOD_DISP_AAL0		5
> +#define MT8195_MUTEX_MOD_DISP_GAMMA0		6
> +#define MT8195_MUTEX_MOD_DISP_DITHER0		7
> +#define MT8195_MUTEX_MOD_DISP_DSI0		8
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	9
> +#define MT8195_MUTEX_MOD_DISP_OVL1		10
> +#define MT8195_MUTEX_MOD_DISP_WDMA1		11
> +#define MT8195_MUTEX_MOD_DISP_RDMA1		12
> +#define MT8195_MUTEX_MOD_DISP_COLOR1		13
> +#define MT8195_MUTEX_MOD_DISP_CCORR1		14
> +#define MT8195_MUTEX_MOD_DISP_AAL1		15
> +#define MT8195_MUTEX_MOD_DISP_GAMMA1		16
> +#define MT8195_MUTEX_MOD_DISP_DITHER1		17
> +#define MT8195_MUTEX_MOD_DISP_DSI1		18
> +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1	19
> +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20
> +#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
> +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0	22
> +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1	23
> +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2	24
> +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3	25
> +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4	26
> +#define MT8195_MUTEX_MOD_DISP_PWM0		27
> +#define MT8195_MUTEX_MOD_DISP_PWM1		28
> +
>  #define MT2712_MUTEX_MOD_DISP_PWM2		10
>  #define MT2712_MUTEX_MOD_DISP_OVL0		11
>  #define MT2712_MUTEX_MOD_DISP_OVL1		12
> @@ -101,11 +134,36 @@
>  #define MT2712_MUTEX_SOF_DSI3			6
>  #define MT8167_MUTEX_SOF_DPI0			2
>  #define MT8167_MUTEX_SOF_DPI1			3
> +
>  #define MT8183_MUTEX_SOF_DSI0			1
>  #define MT8183_MUTEX_SOF_DPI0			2
>  
> -#define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_SOF_DSI0 << 6)
> -#define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
> +#define MT8183_MUTEX_EOF_CONVERT(sof)	((sof) << 6)
> +#define MT8183_MUTEX_EOF_DSI0 \
> +	MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DSI0)
> +#define MT8183_MUTEX_EOF_DPI0 \
> +	MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DPI0)

Not needed here, please drop.

> +
> +#define MT8195_MUTEX_SOF_DSI0			1
> +#define MT8195_MUTEX_SOF_DSI1			2
> +#define MT8195_MUTEX_SOF_DP_INTF0		3
> +#define MT8195_MUTEX_SOF_DP_INTF1		4
> +#define MT8195_MUTEX_SOF_DPI0			6 /* for HDMI_TX */
> +#define MT8195_MUTEX_SOF_DPI1			5 /* for digital video out */
> +
> +#define MT8195_MUTEX_EOF_CONVERT(sof)	((sof) << 7)

Same here.

Regards,
Matthias

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Re: [PATCH v2 6/9] soc: mediatek: add mtk-mutex support for mt8195 vdosys0

[Jason-JH Lin]

On Wed, 2021-07-14 at 18:04 +0200, Matthias Brugger wrote:
> 
> On 10/07/2021 13:38, jason-jh.lin wrote:
> > Add mtk-mutex support for mt8195 vdosys0.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/soc/mediatek/mtk-mutex.c | 107
> > +++++++++++++++++++++++++++++--
> >  1 file changed, 102 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index 2e4bcc300576..d74eb3f97f1d 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -17,6 +17,9 @@
> >  #define MT8183_MUTEX0_MOD0			0x30
> >  #define MT8183_MUTEX0_SOF0			0x2c
> >  
> > +#define MT8195_DISP_MUTEX0_MOD0			0x30
> > +#define MT8195_DISP_MUTEX0_SOF			0x2c
> > +
> >  #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 *
> > (n))
> >  #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
> >  #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 *
> > (n))
> > @@ -67,6 +70,36 @@
> >  #define MT8173_MUTEX_MOD_DISP_PWM1		24
> >  #define MT8173_MUTEX_MOD_DISP_OD		25
> >  
> > +#define MT8195_MUTEX_MOD_DISP_OVL0		0
> > +#define MT8195_MUTEX_MOD_DISP_WDMA0		1
> > +#define MT8195_MUTEX_MOD_DISP_RDMA0		2
> > +#define MT8195_MUTEX_MOD_DISP_COLOR0		3
> > +#define MT8195_MUTEX_MOD_DISP_CCORR0		4
> > +#define MT8195_MUTEX_MOD_DISP_AAL0		5
> > +#define MT8195_MUTEX_MOD_DISP_GAMMA0		6
> > +#define MT8195_MUTEX_MOD_DISP_DITHER0		7
> > +#define MT8195_MUTEX_MOD_DISP_DSI0		8
> > +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	9
> > +#define MT8195_MUTEX_MOD_DISP_OVL1		10
> > +#define MT8195_MUTEX_MOD_DISP_WDMA1		11
> > +#define MT8195_MUTEX_MOD_DISP_RDMA1		12
> > +#define MT8195_MUTEX_MOD_DISP_COLOR1		13
> > +#define MT8195_MUTEX_MOD_DISP_CCORR1		14
> > +#define MT8195_MUTEX_MOD_DISP_AAL1		15
> > +#define MT8195_MUTEX_MOD_DISP_GAMMA1		16
> > +#define MT8195_MUTEX_MOD_DISP_DITHER1		17
> > +#define MT8195_MUTEX_MOD_DISP_DSI1		18
> > +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1	19
> > +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20
> > +#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
> > +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0	22
> > +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1	23
> > +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2	24
> > +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3	25
> > +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4	26
> > +#define MT8195_MUTEX_MOD_DISP_PWM0		27
> > +#define MT8195_MUTEX_MOD_DISP_PWM1		28
> > +
> >  #define MT2712_MUTEX_MOD_DISP_PWM2		10
> >  #define MT2712_MUTEX_MOD_DISP_OVL0		11
> >  #define MT2712_MUTEX_MOD_DISP_OVL1		12
> > @@ -101,11 +134,36 @@
> >  #define MT2712_MUTEX_SOF_DSI3			6
> >  #define MT8167_MUTEX_SOF_DPI0			2
> >  #define MT8167_MUTEX_SOF_DPI1			3
> > +
> >  #define MT8183_MUTEX_SOF_DSI0			1
> >  #define MT8183_MUTEX_SOF_DPI0			2
> >  
> > -#define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_S
> > OF_DSI0 << 6)
> > -#define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_S
> > OF_DPI0 << 6)
> > +#define MT8183_MUTEX_EOF_CONVERT(sof)	((sof) << 6)
> > +#define MT8183_MUTEX_EOF_DSI0 \
> > +	MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DSI0)
> > +#define MT8183_MUTEX_EOF_DPI0 \
> > +	MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DPI0)
> 
> Not needed here, please drop.
> 
> > +
> > +#define MT8195_MUTEX_SOF_DSI0			1
> > +#define MT8195_MUTEX_SOF_DSI1			2
> > +#define MT8195_MUTEX_SOF_DP_INTF0		3
> > +#define MT8195_MUTEX_SOF_DP_INTF1		4
> > +#define MT8195_MUTEX_SOF_DPI0			6 /* for
> > HDMI_TX */
> > +#define MT8195_MUTEX_SOF_DPI1			5 /* for
> > digital video out */
> > +
> > +#define MT8195_MUTEX_EOF_CONVERT(sof)	((sof) << 7)
> 
> Same here.
> 
> Regards,
> Matthias

Hi Matthias,

Ok, I will drop this at the next version.

Regards,
Jason-JH.Lin
-- 
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Re: [PATCH v2 6/9] soc: mediatek: add mtk-mutex support for mt8195 vdosys0

[Matthias Brugger]

On 10/07/2021 13:38, jason-jh.lin wrote:
> Add mtk-mutex support for mt8195 vdosys0.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/soc/mediatek/mtk-mutex.c | 107 +++++++++++++++++++++++++++++--
>  1 file changed, 102 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 2e4bcc300576..d74eb3f97f1d 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
[...]
>  struct mtk_mutex *mtk_mutex_get(struct device *dev)
>  {
>  	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -507,6 +602,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
>  	  .data = &mt8173_mutex_driver_data},
>  	{ .compatible = "mediatek,mt8183-disp-mutex",
>  	  .data = &mt8183_mutex_driver_data},
> +	{ .compatible = "mediatek,mt8195-disp-mutex",
> +	  .data = &mt8195_mutex_driver_data},

Are we missing a binding description for that?

Regards,
Matthias

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Re: [PATCH v2 6/9] soc: mediatek: add mtk-mutex support for mt8195 vdosys0

[Jason-JH Lin]

On Wed, 2021-07-14 at 18:06 +0200, Matthias Brugger wrote:
> 
> On 10/07/2021 13:38, jason-jh.lin wrote:
> > Add mtk-mutex support for mt8195 vdosys0.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/soc/mediatek/mtk-mutex.c | 107
> > +++++++++++++++++++++++++++++--
> >  1 file changed, 102 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index 2e4bcc300576..d74eb3f97f1d 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> 
> [...]
> >  struct mtk_mutex *mtk_mutex_get(struct device *dev)
> >  {
> >  	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> > @@ -507,6 +602,8 @@ static const struct of_device_id
> > mutex_driver_dt_match[] = {
> >  	  .data = &mt8173_mutex_driver_data},
> >  	{ .compatible = "mediatek,mt8183-disp-mutex",
> >  	  .data = &mt8183_mutex_driver_data},
> > +	{ .compatible = "mediatek,mt8195-disp-mutex",
> > +	  .data = &mt8195_mutex_driver_data},
> 
> Are we missing a binding description for that?
> 
> Regards,
> Matthias

Hi Matthias,

mutex is already defined in
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt

I'll change it to mediatek,disp.yaml at the next version.

Regards,
Jason-JH.Lin
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[PATCH v2 7/9] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

[jason-jh.lin]

Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  6 ++++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 24 ++++++++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 728aaadfea8c..00e9827acefe 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
 	.fifo_size = 5 * SZ_1K,
 };
 
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+	.fifo_size = 1920,
+};
+
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-rdma",
 	  .data = &mt2701_rdma_driver_data},
@@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	  .data = &mt8173_rdma_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-rdma",
 	  .data = &mt8183_rdma_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = &mt8195_rdma_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b46bdb8985da..d6f6d1bdad85 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
 	DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+	DDP_COMPONENT_OVL0,
+	DDP_COMPONENT_RDMA0,
+	DDP_COMPONENT_COLOR0,
+	DDP_COMPONENT_CCORR,
+	DDP_COMPONENT_AAL0,
+	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_DP_INTF0,
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.main_path = mt2701_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.main_path = mt8195_mtk_ddp_main,
+	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
 static int mtk_drm_kms_init(struct drm_device *drm)
 {
 	struct mtk_drm_private *private = drm->dev_private;
@@ -410,6 +428,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8183-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8173-disp-wdma",
 	  .data = (void *)MTK_DISP_WDMA },
 	{ .compatible = "mediatek,mt8183-disp-ccorr",
@@ -448,6 +468,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8183-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt2701-disp-pwm",
 	  .data = (void *)MTK_DISP_BLS },
 	{ .compatible = "mediatek,mt8173-disp-pwm",
@@ -468,6 +490,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
 	  .data = &mt8173_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8183-mmsys",
 	  .data = &mt8183_mmsys_driver_data},
+	{.compatible = "mediatek,mt8195-vdosys0",
+	  .data = &mt8195_vdosys0_driver_data},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-- 
2.18.0
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Re: [PATCH v2 7/9] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
>
> Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  6 ++++++
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 24 ++++++++++++++++++++++++
>  2 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 728aaadfea8c..00e9827acefe 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
>         .fifo_size = 5 * SZ_1K,
>  };
>
> +static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
> +       .fifo_size = 1920,
> +};
> +
>  static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
>         { .compatible = "mediatek,mt2701-disp-rdma",
>           .data = &mt2701_rdma_driver_data},
> @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
>           .data = &mt8173_rdma_driver_data},
>         { .compatible = "mediatek,mt8183-disp-rdma",
>           .data = &mt8183_rdma_driver_data},
> +       { .compatible = "mediatek,mt8195-disp-rdma",
> +         .data = &mt8195_rdma_driver_data},
>         {},
>  };
>  MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index b46bdb8985da..d6f6d1bdad85 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
>         DDP_COMPONENT_DPI0,
>  };
>
> +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> +       DDP_COMPONENT_OVL0,
> +       DDP_COMPONENT_RDMA0,
> +       DDP_COMPONENT_COLOR0,
> +       DDP_COMPONENT_CCORR,
> +       DDP_COMPONENT_AAL0,
> +       DDP_COMPONENT_GAMMA,
> +       DDP_COMPONENT_DITHER,
> +       DDP_COMPONENT_DSC0,
> +       DDP_COMPONENT_MERGE0,
> +       DDP_COMPONENT_DP_INTF0,

Where is the dp_intf driver in this series?

Regards,
Chun-Kuang.

> +};
> +
>  static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
>         .main_path = mt2701_mtk_ddp_main,
>         .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> @@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>         .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
>  };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> +       .main_path = mt8195_mtk_ddp_main,
> +       .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> +};
> +
>  static int mtk_drm_kms_init(struct drm_device *drm)
>  {
>         struct mtk_drm_private *private = drm->dev_private;
> @@ -410,6 +428,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_RDMA },
>         { .compatible = "mediatek,mt8183-disp-rdma",
>           .data = (void *)MTK_DISP_RDMA },
> +       { .compatible = "mediatek,mt8195-disp-rdma",
> +         .data = (void *)MTK_DISP_RDMA },
>         { .compatible = "mediatek,mt8173-disp-wdma",
>           .data = (void *)MTK_DISP_WDMA },
>         { .compatible = "mediatek,mt8183-disp-ccorr",
> @@ -448,6 +468,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt8183-disp-mutex",
>           .data = (void *)MTK_DISP_MUTEX },
> +       { .compatible = "mediatek,mt8195-disp-mutex",
> +         .data = (void *)MTK_DISP_MUTEX },
>         { .compatible = "mediatek,mt2701-disp-pwm",
>           .data = (void *)MTK_DISP_BLS },
>         { .compatible = "mediatek,mt8173-disp-pwm",
> @@ -468,6 +490,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
>           .data = &mt8173_mmsys_driver_data},
>         { .compatible = "mediatek,mt8183-mmsys",
>           .data = &mt8183_mmsys_driver_data},
> +       {.compatible = "mediatek,mt8195-vdosys0",
> +         .data = &mt8195_vdosys0_driver_data},
>         { }
>  };
>  MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
> --
> 2.18.0
>

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Re: [PATCH v2 7/9] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

[Jason-JH Lin]

On Wed, 2021-07-14 at 22:35 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
> > 
> > Add driver data of mt8195 vdosys0 to mediatek-drm and the sub
> > driver.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  6 ++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 24
> > ++++++++++++++++++++++++
> >  2 files changed, 30 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > index 728aaadfea8c..00e9827acefe 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data
> > mt8183_rdma_driver_data = {
> >         .fifo_size = 5 * SZ_1K,
> >  };
> > 
> > +static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
> > +       .fifo_size = 1920,
> > +};
> > +
> >  static const struct of_device_id mtk_disp_rdma_driver_dt_match[] =
> > {
> >         { .compatible = "mediatek,mt2701-disp-rdma",
> >           .data = &mt2701_rdma_driver_data},
> > @@ -362,6 +366,8 @@ static const struct of_device_id
> > mtk_disp_rdma_driver_dt_match[] = {
> >           .data = &mt8173_rdma_driver_data},
> >         { .compatible = "mediatek,mt8183-disp-rdma",
> >           .data = &mt8183_rdma_driver_data},
> > +       { .compatible = "mediatek,mt8195-disp-rdma",
> > +         .data = &mt8195_rdma_driver_data},
> >         {},
> >  };
> >  MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index b46bdb8985da..d6f6d1bdad85 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id
> > mt8183_mtk_ddp_ext[] = {
> >         DDP_COMPONENT_DPI0,
> >  };
> > 
> > +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> > +       DDP_COMPONENT_OVL0,
> > +       DDP_COMPONENT_RDMA0,
> > +       DDP_COMPONENT_COLOR0,
> > +       DDP_COMPONENT_CCORR,
> > +       DDP_COMPONENT_AAL0,
> > +       DDP_COMPONENT_GAMMA,
> > +       DDP_COMPONENT_DITHER,
> > +       DDP_COMPONENT_DSC0,
> > +       DDP_COMPONENT_MERGE0,
> > +       DDP_COMPONENT_DP_INTF0,
> 
> Where is the dp_intf driver in this series?
> 
> Regards,
> Chun-Kuang.
> 
Hi CK,

dp_intf driver will be upstream in another series patches by DP owner.

Regards,
Jason-JH.Lin

> > +};
> > +
> >  static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data
> > = {
> >         .main_path = mt2701_mtk_ddp_main,
> >         .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> > @@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> >         .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
> >  };
> > 
> > +static const struct mtk_mmsys_driver_data
> > mt8195_vdosys0_driver_data = {
> > +       .main_path = mt8195_mtk_ddp_main,
> > +       .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> > +};
> > +
> >  static int mtk_drm_kms_init(struct drm_device *drm)
> >  {
> >         struct mtk_drm_private *private = drm->dev_private;
> > @@ -410,6 +428,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >           .data = (void *)MTK_DISP_RDMA },
> >         { .compatible = "mediatek,mt8183-disp-rdma",
> >           .data = (void *)MTK_DISP_RDMA },
> > +       { .compatible = "mediatek,mt8195-disp-rdma",
> > +         .data = (void *)MTK_DISP_RDMA },
> >         { .compatible = "mediatek,mt8173-disp-wdma",
> >           .data = (void *)MTK_DISP_WDMA },
> >         { .compatible = "mediatek,mt8183-disp-ccorr",
> > @@ -448,6 +468,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >           .data = (void *)MTK_DISP_MUTEX },
> >         { .compatible = "mediatek,mt8183-disp-mutex",
> >           .data = (void *)MTK_DISP_MUTEX },
> > +       { .compatible = "mediatek,mt8195-disp-mutex",
> > +         .data = (void *)MTK_DISP_MUTEX },
> >         { .compatible = "mediatek,mt2701-disp-pwm",
> >           .data = (void *)MTK_DISP_BLS },
> >         { .compatible = "mediatek,mt8173-disp-pwm",
> > @@ -468,6 +490,8 @@ static const struct of_device_id
> > mtk_drm_of_ids[] = {
> >           .data = &mt8173_mmsys_driver_data},
> >         { .compatible = "mediatek,mt8183-mmsys",
> >           .data = &mt8183_mmsys_driver_data},
> > +       {.compatible = "mediatek,mt8195-vdosys0",
> > +         .data = &mt8195_vdosys0_driver_data},
> >         { }
> >  };
> >  MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>
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[PATCH v2 8/9] drm/mediatek: add DSC support for mt8195

[jason-jh.lin]

Add DSC module file.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_dsc.c     | 205 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  13 ++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 7 files changed, 233 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_dsc.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index dc54a7a69005..a1b239135c8f 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -5,6 +5,7 @@ mediatek-drm-y := mtk_disp_ccorr.o \
 		  mtk_disp_gamma.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_rdma.o \
+		  mtk_disp_dsc.o \
 		  mtk_drm_crtc.o \
 		  mtk_drm_ddp_comp.o \
 		  mtk_drm_drv.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index cafd9df2d63b..128d9fdbaf9e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -89,4 +89,12 @@ void mtk_rdma_enable_vblank(struct device *dev,
 			    void *vblank_cb_data);
 void mtk_rdma_disable_vblank(struct device *dev);
 
+int mtk_dsc_clk_enable(struct device *dev);
+void mtk_dsc_clk_disable(struct device *dev);
+void mtk_dsc_config(struct device *dev, unsigned int width,
+		    unsigned int height, unsigned int vrefresh,
+		    unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_dsc_start(struct device *dev);
+void mtk_dsc_stop(struct device *dev);
+
 #endif
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_dsc.c b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
new file mode 100644
index 000000000000..61187f824c19
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_gem.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_DSC_CON			0x0000
+#define DSC_EN						BIT(0)
+#define DSC_DUAL_INOUT				BIT(2)
+#define DSC_IN_SRC_SEL				BIT(3)
+#define DSC_BYPASS					BIT(4)
+#define DSC_RELAY					BIT(5)
+#define DSC_EMPTY_FLAG_SEL			0xc000
+#define DSC_UFOE_SEL				BIT(16)
+#define DISP_REG_DSC_OBUF			0x0070
+
+/**
+ * struct mtk_disp_dsc - DISP_DSC driver structure
+ * @clk - clk of dsc hardware
+ * @regs - hardware register address of dsc
+ * @comp_id - enum type of component id
+ * @cmdq_reg - structure containing cmdq hardware resource
+ */
+struct mtk_disp_dsc {
+	struct clk *clk;
+	void __iomem *regs;
+	enum mtk_ddp_comp_id comp_id;
+	struct cmdq_client_reg		cmdq_reg;
+};
+
+void mtk_dsc_start(struct device *dev)
+{
+	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
+	void __iomem *baddr = dsc->regs;
+	int ret = 0;
+
+	ret = pm_runtime_get_sync(dev);
+	if (ret < 0)
+		DRM_ERROR("Failed to enable power domain: %d\n", ret);
+
+	mtk_ddp_write_mask(NULL, DSC_EN,
+			   &dsc->cmdq_reg, baddr,
+			   DISP_REG_DSC_CON, DSC_EN);
+
+	pr_debug("dsc_start:0x%x\n", readl(baddr + DISP_REG_DSC_CON));
+}
+
+void mtk_dsc_stop(struct device *dev)
+{
+	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
+	void __iomem *baddr = dsc->regs;
+	int ret = 0;
+
+	mtk_ddp_write_mask(NULL, 0x0, &dsc->cmdq_reg, baddr,
+			   DISP_REG_DSC_CON, DSC_EN);
+
+	pr_debug("dsc_stop:0x%x\n", readl(baddr + DISP_REG_DSC_CON));
+
+	ret = pm_runtime_put(dev);
+	if (ret < 0)
+		DRM_ERROR("Failed to disable power domain: %d\n", ret);
+}
+
+int mtk_dsc_clk_enable(struct device *dev)
+{
+	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
+
+	return clk_prepare_enable(dsc->clk);
+}
+
+void mtk_dsc_clk_disable(struct device *dev)
+{
+	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(dsc->clk);
+}
+
+void mtk_dsc_config(struct device *dev, unsigned int w,
+		    unsigned int h, unsigned int vrefresh,
+		    unsigned int bpc, struct cmdq_pkt *handle)
+{
+	struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
+
+	/* dsc bypass mode */
+	mtk_ddp_write_mask(handle, DSC_BYPASS,
+			   &dsc->cmdq_reg, dsc->regs,
+			   DISP_REG_DSC_CON, DSC_BYPASS);
+	mtk_ddp_write_mask(handle, DSC_UFOE_SEL,
+			   &dsc->cmdq_reg, dsc->regs,
+			   DISP_REG_DSC_CON, DSC_UFOE_SEL);
+	mtk_ddp_write_mask(handle, DSC_DUAL_INOUT,
+			   &dsc->cmdq_reg, dsc->regs,
+			   DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static int mtk_disp_dsc_bind(struct device *dev, struct device *master,
+			     void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_dsc_unbind(struct device *dev, struct device *master,
+				void *data)
+{
+}
+
+static const struct component_ops mtk_disp_dsc_component_ops = {
+	.bind = mtk_disp_dsc_bind,
+	.unbind = mtk_disp_dsc_unbind,
+};
+
+static int mtk_disp_dsc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct mtk_disp_dsc *priv;
+	enum mtk_ddp_comp_id comp_id;
+	int irq;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_DSC);
+	if ((int)comp_id < 0) {
+		dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
+		return comp_id;
+	}
+
+	priv->comp_id = comp_id;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return irq;
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get dsc clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to ioremap dsc\n");
+		return PTR_ERR(priv->regs);
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+	platform_set_drvdata(pdev, priv);
+
+	pm_runtime_enable(dev);
+
+	ret = component_add(dev, &mtk_disp_dsc_component_ops);
+	if (ret != 0) {
+		dev_err(dev, "Failed to add component: %d\n", ret);
+		pm_runtime_disable(dev);
+	}
+
+	return ret;
+}
+
+static int mtk_disp_dsc_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_dsc_component_ops);
+
+	pm_runtime_disable(&pdev->dev);
+
+	return 0;
+}
+
+static const struct of_device_id mtk_disp_dsc_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8195-disp-dsc", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_dsc_driver_dt_match);
+
+struct platform_driver mtk_disp_dsc_driver = {
+	.probe = mtk_disp_dsc_probe,
+	.remove = mtk_disp_dsc_remove,
+	.driver = {
+		.name = "mediatek-disp-dsc",
+		.owner = THIS_MODULE,
+		.of_match_table = mtk_disp_dsc_driver_dt_match,
+	},
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 75bc00e17fc4..d0b0f41dfe5a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -333,6 +333,14 @@ static const struct mtk_ddp_comp_funcs ddp_rdma = {
 	.layer_config = mtk_rdma_layer_config,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+	.config = mtk_dsc_config,
+	.start = mtk_dsc_start,
+	.stop = mtk_dsc_stop,
+	.clk_enable = mtk_dsc_clk_enable,
+	.clk_disable = mtk_dsc_clk_disable,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_ufoe = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -356,6 +364,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
 	[MTK_DISP_BLS] = "bls",
+	[MTK_DISP_DSC] = "dsc",
 };
 
 struct mtk_ddp_comp_match {
@@ -391,6 +400,9 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_RDMA0]	= { MTK_DISP_RDMA,	0, &ddp_rdma },
 	[DDP_COMPONENT_RDMA1]	= { MTK_DISP_RDMA,	1, &ddp_rdma },
 	[DDP_COMPONENT_RDMA2]	= { MTK_DISP_RDMA,	2, &ddp_rdma },
+	[DDP_COMPONENT_DSC0]	= { MTK_DISP_DSC,	0, &ddp_dsc },
+	[DDP_COMPONENT_DSC1]	= { MTK_DISP_DSC,	1, &ddp_dsc },
+	[DDP_COMPONENT_DSC1_VIRTUAL0]	= { MTK_DISP_DSC,	-1, &ddp_dsc },
 	[DDP_COMPONENT_UFOE]	= { MTK_DISP_UFOE,	0, &ddp_ufoe },
 	[DDP_COMPONENT_WDMA0]	= { MTK_DISP_WDMA,	0, NULL },
 	[DDP_COMPONENT_WDMA1]	= { MTK_DISP_WDMA,	1, NULL },
@@ -509,6 +521,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_CCORR ||
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
+	    type == MTK_DISP_DSC ||
 	    type == MTK_DPI ||
 	    type == MTK_DSI ||
 	    type == MTK_DISP_OVL ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index bb914d976cf5..661fb620e266 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -34,6 +34,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
 	MTK_DISP_BLS,
+	MTK_DISP_DSC,
 	MTK_DDP_COMP_TYPE_MAX,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index d6f6d1bdad85..7dfca63c1042 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -446,6 +446,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-dither",
 	  .data = (void *)MTK_DISP_DITHER },
+	{ .compatible = "mediatek,mt8195-disp-dsc",
+	  .data = (void *)MTK_DISP_DSC },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
 	  .data = (void *)MTK_DISP_UFOE },
 	{ .compatible = "mediatek,mt2701-dsi",
@@ -563,6 +565,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		if (comp_type == MTK_DISP_CCORR ||
 		    comp_type == MTK_DISP_COLOR ||
 		    comp_type == MTK_DISP_GAMMA ||
+		    comp_type == MTK_DISP_DSC ||
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
@@ -667,6 +670,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_rdma_driver,
 	&mtk_dpi_driver,
 	&mtk_drm_platform_driver,
+	&mtk_disp_dsc_driver,
 	&mtk_dsi_driver,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 637f5669e895..8b722330ef7d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -51,6 +51,7 @@ extern struct platform_driver mtk_disp_color_driver;
 extern struct platform_driver mtk_disp_gamma_driver;
 extern struct platform_driver mtk_disp_ovl_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
+extern struct platform_driver mtk_disp_dsc_driver;
 extern struct platform_driver mtk_dpi_driver;
 extern struct platform_driver mtk_dsi_driver;
 
-- 
2.18.0
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Re: [PATCH v2 8/9] drm/mediatek: add DSC support for mt8195

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
>
> Add DSC module file.

Introduce DSC here.

>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/Makefile           |   1 +
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
>  drivers/gpu/drm/mediatek/mtk_disp_dsc.c     | 205 ++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  13 ++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
>  7 files changed, 233 insertions(+)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_dsc.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index dc54a7a69005..a1b239135c8f 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -5,6 +5,7 @@ mediatek-drm-y := mtk_disp_ccorr.o \
>                   mtk_disp_gamma.o \
>                   mtk_disp_ovl.o \
>                   mtk_disp_rdma.o \
> +                 mtk_disp_dsc.o \
>                   mtk_drm_crtc.o \
>                   mtk_drm_ddp_comp.o \
>                   mtk_drm_drv.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index cafd9df2d63b..128d9fdbaf9e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -89,4 +89,12 @@ void mtk_rdma_enable_vblank(struct device *dev,
>                             void *vblank_cb_data);
>  void mtk_rdma_disable_vblank(struct device *dev);
>
> +int mtk_dsc_clk_enable(struct device *dev);
> +void mtk_dsc_clk_disable(struct device *dev);
> +void mtk_dsc_config(struct device *dev, unsigned int width,
> +                   unsigned int height, unsigned int vrefresh,
> +                   unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_dsc_start(struct device *dev);
> +void mtk_dsc_stop(struct device *dev);
> +
>  #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_dsc.c b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> new file mode 100644
> index 000000000000..61187f824c19
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> @@ -0,0 +1,205 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_gem.h"
> +#include "mtk_disp_drv.h"
> +
> +#define DISP_REG_DSC_CON                       0x0000
> +#define DSC_EN                                         BIT(0)
> +#define DSC_DUAL_INOUT                         BIT(2)
> +#define DSC_IN_SRC_SEL                         BIT(3)
> +#define DSC_BYPASS                                     BIT(4)
> +#define DSC_RELAY                                      BIT(5)
> +#define DSC_EMPTY_FLAG_SEL                     0xc000
> +#define DSC_UFOE_SEL                           BIT(16)
> +#define DISP_REG_DSC_OBUF                      0x0070
> +
> +/**
> + * struct mtk_disp_dsc - DISP_DSC driver structure
> + * @clk - clk of dsc hardware
> + * @regs - hardware register address of dsc
> + * @comp_id - enum type of component id
> + * @cmdq_reg - structure containing cmdq hardware resource
> + */
> +struct mtk_disp_dsc {
> +       struct clk *clk;
> +       void __iomem *regs;
> +       enum mtk_ddp_comp_id comp_id;

comp_id is useless, so remove.

> +       struct cmdq_client_reg          cmdq_reg;
> +};
> +
> +void mtk_dsc_start(struct device *dev)
> +{
> +       struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +       void __iomem *baddr = dsc->regs;
> +       int ret = 0;
> +
> +       ret = pm_runtime_get_sync(dev);

I think no sub driver enable the power, so sync with other sub driver.

> +       if (ret < 0)
> +               DRM_ERROR("Failed to enable power domain: %d\n", ret);
> +
> +       mtk_ddp_write_mask(NULL, DSC_EN,
> +                          &dsc->cmdq_reg, baddr,
> +                          DISP_REG_DSC_CON, DSC_EN);
> +
> +       pr_debug("dsc_start:0x%x\n", readl(baddr + DISP_REG_DSC_CON));

No sub driver print this, sync with other sub driver.

> +}
> +
> +void mtk_dsc_stop(struct device *dev)
> +{
> +       struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +       void __iomem *baddr = dsc->regs;
> +       int ret = 0;
> +
> +       mtk_ddp_write_mask(NULL, 0x0, &dsc->cmdq_reg, baddr,
> +                          DISP_REG_DSC_CON, DSC_EN);
> +
> +       pr_debug("dsc_stop:0x%x\n", readl(baddr + DISP_REG_DSC_CON));

Why we need this information?

> +
> +       ret = pm_runtime_put(dev);

Ditto as pm_runtime_get_sync().

> +       if (ret < 0)
> +               DRM_ERROR("Failed to disable power domain: %d\n", ret);
> +}
> +
> +int mtk_dsc_clk_enable(struct device *dev)
> +{
> +       struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +
> +       return clk_prepare_enable(dsc->clk);
> +}
> +
> +void mtk_dsc_clk_disable(struct device *dev)
> +{
> +       struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +
> +       clk_disable_unprepare(dsc->clk);
> +}
> +
> +void mtk_dsc_config(struct device *dev, unsigned int w,
> +                   unsigned int h, unsigned int vrefresh,
> +                   unsigned int bpc, struct cmdq_pkt *handle)
> +{
> +       struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +
> +       /* dsc bypass mode */
> +       mtk_ddp_write_mask(handle, DSC_BYPASS,
> +                          &dsc->cmdq_reg, dsc->regs,
> +                          DISP_REG_DSC_CON, DSC_BYPASS);
> +       mtk_ddp_write_mask(handle, DSC_UFOE_SEL,
> +                          &dsc->cmdq_reg, dsc->regs,
> +                          DISP_REG_DSC_CON, DSC_UFOE_SEL);
> +       mtk_ddp_write_mask(handle, DSC_DUAL_INOUT,
> +                          &dsc->cmdq_reg, dsc->regs,
> +                          DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> +}
> +
> +static int mtk_disp_dsc_bind(struct device *dev, struct device *master,
> +                            void *data)
> +{
> +       return 0;
> +}
> +
> +static void mtk_disp_dsc_unbind(struct device *dev, struct device *master,
> +                               void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_dsc_component_ops = {
> +       .bind = mtk_disp_dsc_bind,
> +       .unbind = mtk_disp_dsc_unbind,
> +};
> +
> +static int mtk_disp_dsc_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct resource *res;
> +       struct mtk_disp_dsc *priv;
> +       enum mtk_ddp_comp_id comp_id;
> +       int irq;
> +       int ret;
> +
> +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_DSC);
> +       if ((int)comp_id < 0) {
> +               dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
> +               return comp_id;
> +       }
> +
> +       priv->comp_id = comp_id;
> +
> +       irq = platform_get_irq(pdev, 0);

Why do you get irq?

> +       if (irq < 0)
> +               return irq;
> +
> +       priv->clk = devm_clk_get(dev, NULL);
> +       if (IS_ERR(priv->clk)) {
> +               dev_err(dev, "failed to get dsc clk\n");
> +               return PTR_ERR(priv->clk);
> +       }
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       priv->regs = devm_ioremap_resource(dev, res);
> +       if (IS_ERR(priv->regs)) {
> +               dev_err(dev, "failed to ioremap dsc\n");
> +               return PTR_ERR(priv->regs);
> +       }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +       ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> +       if (ret)
> +               dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> +       platform_set_drvdata(pdev, priv);
> +
> +       pm_runtime_enable(dev);

Sync with other sub driver.

> +
> +       ret = component_add(dev, &mtk_disp_dsc_component_ops);
> +       if (ret != 0) {
> +               dev_err(dev, "Failed to add component: %d\n", ret);
> +               pm_runtime_disable(dev);
> +       }
> +
> +       return ret;
> +}
> +
> +static int mtk_disp_dsc_remove(struct platform_device *pdev)
> +{
> +       component_del(&pdev->dev, &mtk_disp_dsc_component_ops);
> +
> +       pm_runtime_disable(&pdev->dev);

Sync with other sub driver.

> +
> +       return 0;
> +}
> +
> +static const struct of_device_id mtk_disp_dsc_driver_dt_match[] = {
> +       { .compatible = "mediatek,mt8195-disp-dsc", },
> +       {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_disp_dsc_driver_dt_match);
> +
> +struct platform_driver mtk_disp_dsc_driver = {
> +       .probe = mtk_disp_dsc_probe,
> +       .remove = mtk_disp_dsc_remove,
> +       .driver = {
> +               .name = "mediatek-disp-dsc",
> +               .owner = THIS_MODULE,
> +               .of_match_table = mtk_disp_dsc_driver_dt_match,
> +       },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 75bc00e17fc4..d0b0f41dfe5a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -333,6 +333,14 @@ static const struct mtk_ddp_comp_funcs ddp_rdma = {
>         .layer_config = mtk_rdma_layer_config,
>  };
>
> +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> +       .config = mtk_dsc_config,
> +       .start = mtk_dsc_start,
> +       .stop = mtk_dsc_stop,
> +       .clk_enable = mtk_dsc_clk_enable,
> +       .clk_disable = mtk_dsc_clk_disable,
> +};
> +
>  static const struct mtk_ddp_comp_funcs ddp_ufoe = {
>         .clk_enable = mtk_ddp_clk_enable,
>         .clk_disable = mtk_ddp_clk_disable,
> @@ -356,6 +364,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
>         [MTK_DISP_MUTEX] = "mutex",
>         [MTK_DISP_OD] = "od",
>         [MTK_DISP_BLS] = "bls",
> +       [MTK_DISP_DSC] = "dsc",
>  };
>
>  struct mtk_ddp_comp_match {
> @@ -391,6 +400,9 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
>         [DDP_COMPONENT_RDMA0]   = { MTK_DISP_RDMA,      0, &ddp_rdma },
>         [DDP_COMPONENT_RDMA1]   = { MTK_DISP_RDMA,      1, &ddp_rdma },
>         [DDP_COMPONENT_RDMA2]   = { MTK_DISP_RDMA,      2, &ddp_rdma },
> +       [DDP_COMPONENT_DSC0]    = { MTK_DISP_DSC,       0, &ddp_dsc },
> +       [DDP_COMPONENT_DSC1]    = { MTK_DISP_DSC,       1, &ddp_dsc },
> +       [DDP_COMPONENT_DSC1_VIRTUAL0]   = { MTK_DISP_DSC,       -1, &ddp_dsc },

Alphabetic order.

>         [DDP_COMPONENT_UFOE]    = { MTK_DISP_UFOE,      0, &ddp_ufoe },
>         [DDP_COMPONENT_WDMA0]   = { MTK_DISP_WDMA,      0, NULL },
>         [DDP_COMPONENT_WDMA1]   = { MTK_DISP_WDMA,      1, NULL },
> @@ -509,6 +521,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
>             type == MTK_DISP_CCORR ||
>             type == MTK_DISP_COLOR ||
>             type == MTK_DISP_GAMMA ||
> +           type == MTK_DISP_DSC ||

Alphabetic order.

>             type == MTK_DPI ||
>             type == MTK_DSI ||
>             type == MTK_DISP_OVL ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index bb914d976cf5..661fb620e266 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -34,6 +34,7 @@ enum mtk_ddp_comp_type {
>         MTK_DISP_MUTEX,
>         MTK_DISP_OD,
>         MTK_DISP_BLS,
> +       MTK_DISP_DSC,
>         MTK_DDP_COMP_TYPE_MAX,
>  };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index d6f6d1bdad85..7dfca63c1042 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -446,6 +446,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_GAMMA, },
>         { .compatible = "mediatek,mt8183-disp-dither",
>           .data = (void *)MTK_DISP_DITHER },
> +       { .compatible = "mediatek,mt8195-disp-dsc",
> +         .data = (void *)MTK_DISP_DSC },
>         { .compatible = "mediatek,mt8173-disp-ufoe",
>           .data = (void *)MTK_DISP_UFOE },
>         { .compatible = "mediatek,mt2701-dsi",
> @@ -563,6 +565,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
>                 if (comp_type == MTK_DISP_CCORR ||
>                     comp_type == MTK_DISP_COLOR ||
>                     comp_type == MTK_DISP_GAMMA ||
> +                   comp_type == MTK_DISP_DSC ||
>                     comp_type == MTK_DISP_OVL ||
>                     comp_type == MTK_DISP_OVL_2L ||
>                     comp_type == MTK_DISP_RDMA ||
> @@ -667,6 +670,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
>         &mtk_disp_rdma_driver,
>         &mtk_dpi_driver,
>         &mtk_drm_platform_driver,
> +       &mtk_disp_dsc_driver,

Alphabetic order.

>         &mtk_dsi_driver,
>  };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index 637f5669e895..8b722330ef7d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -51,6 +51,7 @@ extern struct platform_driver mtk_disp_color_driver;
>  extern struct platform_driver mtk_disp_gamma_driver;
>  extern struct platform_driver mtk_disp_ovl_driver;
>  extern struct platform_driver mtk_disp_rdma_driver;
> +extern struct platform_driver mtk_disp_dsc_driver;

Alphabetic order.

Regards,
Chun-Kuang.

>  extern struct platform_driver mtk_dpi_driver;
>  extern struct platform_driver mtk_dsi_driver;
>
> --
> 2.18.0
>

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Re: [PATCH v2 8/9] drm/mediatek: add DSC support for mt8195

[Jason-JH Lin]

Hi CK,

On Sun, 2021-07-11 at 09:19 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
> > 
> > Add DSC module file.
> 
> Introduce DSC here.
> 

OK, I'll add this.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/Makefile           |   1 +
> >  drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
> >  drivers/gpu/drm/mediatek/mtk_disp_dsc.c     | 205
> > ++++++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  13 ++
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
> >  7 files changed, 233 insertions(+)
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> > 
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index dc54a7a69005..a1b239135c8f 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -5,6 +5,7 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> >                   mtk_disp_gamma.o \
> >                   mtk_disp_ovl.o \
> >                   mtk_disp_rdma.o \
> > +                 mtk_disp_dsc.o \
> >                   mtk_drm_crtc.o \
> >                   mtk_drm_ddp_comp.o \
> >                   mtk_drm_drv.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index cafd9df2d63b..128d9fdbaf9e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -89,4 +89,12 @@ void mtk_rdma_enable_vblank(struct device *dev,
> >                             void *vblank_cb_data);
> >  void mtk_rdma_disable_vblank(struct device *dev);
> > 
> > +int mtk_dsc_clk_enable(struct device *dev);
> > +void mtk_dsc_clk_disable(struct device *dev);
> > +void mtk_dsc_config(struct device *dev, unsigned int width,
> > +                   unsigned int height, unsigned int vrefresh,
> > +                   unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > +void mtk_dsc_start(struct device *dev);
> > +void mtk_dsc_stop(struct device *dev);
> > +
> >  #endif
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> > new file mode 100644
> > index 000000000000..61187f824c19
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> > @@ -0,0 +1,205 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_gem.h"
> > +#include "mtk_disp_drv.h"
> > +
> > +#define DISP_REG_DSC_CON                       0x0000
> > +#define DSC_EN                                         BIT(0)
> > +#define DSC_DUAL_INOUT                         BIT(2)
> > +#define DSC_IN_SRC_SEL                         BIT(3)
> > +#define DSC_BYPASS                                     BIT(4)
> > +#define DSC_RELAY                                      BIT(5)
> > +#define DSC_EMPTY_FLAG_SEL                     0xc000
> > +#define DSC_UFOE_SEL                           BIT(16)
> > +#define DISP_REG_DSC_OBUF                      0x0070
> > +
> > +/**
> > + * struct mtk_disp_dsc - DISP_DSC driver structure
> > + * @clk - clk of dsc hardware
> > + * @regs - hardware register address of dsc
> > + * @comp_id - enum type of component id
> > + * @cmdq_reg - structure containing cmdq hardware resource
> > + */
> > +struct mtk_disp_dsc {
> > +       struct clk *clk;
> > +       void __iomem *regs;
> > +       enum mtk_ddp_comp_id comp_id;
> 
> comp_id is useless, so remove.
> 
OK, I'll remove it.

> > +       struct cmdq_client_reg          cmdq_reg;
> > +};
> > +
> > +void mtk_dsc_start(struct device *dev)
> > +{
> > +       struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> > +       void __iomem *baddr = dsc->regs;
> > +       int ret = 0;
> > +
> > +       ret = pm_runtime_get_sync(dev);
> 
> I think no sub driver enable the power, so sync with other sub
> driver.
> 
OK, I'll remove it.

> > +       if (ret < 0)
> > +               DRM_ERROR("Failed to enable power domain: %d\n",
> > ret);
> > +
> > +       mtk_ddp_write_mask(NULL, DSC_EN,
> > +                          &dsc->cmdq_reg, baddr,
> > +                          DISP_REG_DSC_CON, DSC_EN);
> > +
> > +       pr_debug("dsc_start:0x%x\n", readl(baddr +
> > DISP_REG_DSC_CON));
> 
> No sub driver print this, sync with other sub driver.
> 
OK, I'll remove it.

> > +}
> > +
> > +void mtk_dsc_stop(struct device *dev)
> > +{
> > +       struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> > +       void __iomem *baddr = dsc->regs;
> > +       int ret = 0;
> > +
> > +       mtk_ddp_write_mask(NULL, 0x0, &dsc->cmdq_reg, baddr,
> > +                          DISP_REG_DSC_CON, DSC_EN);
> > +
> > +       pr_debug("dsc_stop:0x%x\n", readl(baddr +
> > DISP_REG_DSC_CON));
> 
> Why we need this information?
> 
I'll remove it.

> > +
> > +       ret = pm_runtime_put(dev);
> 
> Ditto as pm_runtime_get_sync().
> 
OK, I'll remove it.

> > +       if (ret < 0)
> > +               DRM_ERROR("Failed to disable power domain: %d\n",
> > ret);
> > +}
> > +
> > +int mtk_dsc_clk_enable(struct device *dev)
> > +{
> > +       struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> > +
> > +       return clk_prepare_enable(dsc->clk);
> > +}
> > +
> > +void mtk_dsc_clk_disable(struct device *dev)
> > +{
> > +       struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> > +
> > +       clk_disable_unprepare(dsc->clk);
> > +}
> > +
> > +void mtk_dsc_config(struct device *dev, unsigned int w,
> > +                   unsigned int h, unsigned int vrefresh,
> > +                   unsigned int bpc, struct cmdq_pkt *handle)
> > +{
> > +       struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> > +
> > +       /* dsc bypass mode */
> > +       mtk_ddp_write_mask(handle, DSC_BYPASS,
> > +                          &dsc->cmdq_reg, dsc->regs,
> > +                          DISP_REG_DSC_CON, DSC_BYPASS);
> > +       mtk_ddp_write_mask(handle, DSC_UFOE_SEL,
> > +                          &dsc->cmdq_reg, dsc->regs,
> > +                          DISP_REG_DSC_CON, DSC_UFOE_SEL);
> > +       mtk_ddp_write_mask(handle, DSC_DUAL_INOUT,
> > +                          &dsc->cmdq_reg, dsc->regs,
> > +                          DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> > +}
> > +
> > +static int mtk_disp_dsc_bind(struct device *dev, struct device
> > *master,
> > +                            void *data)
> > +{
> > +       return 0;
> > +}
> > +
> > +static void mtk_disp_dsc_unbind(struct device *dev, struct device
> > *master,
> > +                               void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_disp_dsc_component_ops = {
> > +       .bind = mtk_disp_dsc_bind,
> > +       .unbind = mtk_disp_dsc_unbind,
> > +};
> > +
> > +static int mtk_disp_dsc_probe(struct platform_device *pdev)
> > +{
> > +       struct device *dev = &pdev->dev;
> > +       struct resource *res;
> > +       struct mtk_disp_dsc *priv;
> > +       enum mtk_ddp_comp_id comp_id;
> > +       int irq;
> > +       int ret;
> > +
> > +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > +       if (!priv)
> > +               return -ENOMEM;
> > +
> > +       comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_DSC);
> > +       if ((int)comp_id < 0) {
> > +               dev_err(dev, "Failed to identify by alias: %d\n",
> > comp_id);
> > +               return comp_id;
> > +       }
> > +
> > +       priv->comp_id = comp_id;
> > +
> > +       irq = platform_get_irq(pdev, 0);
> 
> Why do you get irq?
> 

I'll remove it.

> > +       if (irq < 0)
> > +               return irq;
> > +
> > +       priv->clk = devm_clk_get(dev, NULL);
> > +       if (IS_ERR(priv->clk)) {
> > +               dev_err(dev, "failed to get dsc clk\n");
> > +               return PTR_ERR(priv->clk);
> > +       }
> > +
> > +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +       priv->regs = devm_ioremap_resource(dev, res);
> > +       if (IS_ERR(priv->regs)) {
> > +               dev_err(dev, "failed to ioremap dsc\n");
> > +               return PTR_ERR(priv->regs);
> > +       }
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > +       ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> > +       if (ret)
> > +               dev_dbg(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > +
> > +       platform_set_drvdata(pdev, priv);
> > +
> > +       pm_runtime_enable(dev);
> 
> Sync with other sub driver.
> 
OK, I'll remove it.

> > +
> > +       ret = component_add(dev, &mtk_disp_dsc_component_ops);
> > +       if (ret != 0) {
> > +               dev_err(dev, "Failed to add component: %d\n", ret);
> > +               pm_runtime_disable(dev);
> > +       }
> > +
> > +       return ret;
> > +}
> > +
> > +static int mtk_disp_dsc_remove(struct platform_device *pdev)
> > +{
> > +       component_del(&pdev->dev, &mtk_disp_dsc_component_ops);
> > +
> > +       pm_runtime_disable(&pdev->dev);
> 
> Sync with other sub driver.
> 
OK, I'll remove it.

> > +
> > +       return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_disp_dsc_driver_dt_match[] =
> > {
> > +       { .compatible = "mediatek,mt8195-disp-dsc", },
> > +       {},
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, mtk_disp_dsc_driver_dt_match);
> > +
> > +struct platform_driver mtk_disp_dsc_driver = {
> > +       .probe = mtk_disp_dsc_probe,
> > +       .remove = mtk_disp_dsc_remove,
> > +       .driver = {
> > +               .name = "mediatek-disp-dsc",
> > +               .owner = THIS_MODULE,
> > +               .of_match_table = mtk_disp_dsc_driver_dt_match,
> > +       },
> > +};
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 75bc00e17fc4..d0b0f41dfe5a 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -333,6 +333,14 @@ static const struct mtk_ddp_comp_funcs
> > ddp_rdma = {
> >         .layer_config = mtk_rdma_layer_config,
> >  };
> > 
> > +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> > +       .config = mtk_dsc_config,
> > +       .start = mtk_dsc_start,
> > +       .stop = mtk_dsc_stop,
> > +       .clk_enable = mtk_dsc_clk_enable,
> > +       .clk_disable = mtk_dsc_clk_disable,
> > +};
> > +
> >  static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> >         .clk_enable = mtk_ddp_clk_enable,
> >         .clk_disable = mtk_ddp_clk_disable,
> > @@ -356,6 +364,7 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> >         [MTK_DISP_MUTEX] = "mutex",
> >         [MTK_DISP_OD] = "od",
> >         [MTK_DISP_BLS] = "bls",
> > +       [MTK_DISP_DSC] = "dsc",
> >  };
> > 
> >  struct mtk_ddp_comp_match {
> > @@ -391,6 +400,9 @@ static const struct mtk_ddp_comp_match
> > mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> >         [DDP_COMPONENT_RDMA0]   = { MTK_DISP_RDMA,      0,
> > &ddp_rdma },
> >         [DDP_COMPONENT_RDMA1]   = { MTK_DISP_RDMA,      1,
> > &ddp_rdma },
> >         [DDP_COMPONENT_RDMA2]   = { MTK_DISP_RDMA,      2,
> > &ddp_rdma },
> > +       [DDP_COMPONENT_DSC0]    = { MTK_DISP_DSC,       0, &ddp_dsc
> > },
> > +       [DDP_COMPONENT_DSC1]    = { MTK_DISP_DSC,       1, &ddp_dsc
> > },
> > +       [DDP_COMPONENT_DSC1_VIRTUAL0]   = { MTK_DISP_DSC,       -1, 
> > &ddp_dsc },
> 
> Alphabetic order.
> 
OK, I'll fix it.
> >         [DDP_COMPONENT_UFOE]    = { MTK_DISP_UFOE,      0,
> > &ddp_ufoe },
> >         [DDP_COMPONENT_WDMA0]   = { MTK_DISP_WDMA,      0, NULL },
> >         [DDP_COMPONENT_WDMA1]   = { MTK_DISP_WDMA,      1, NULL },
> > @@ -509,6 +521,7 @@ int mtk_ddp_comp_init(struct device_node *node,
> > struct mtk_ddp_comp *comp,
> >             type == MTK_DISP_CCORR ||
> >             type == MTK_DISP_COLOR ||
> >             type == MTK_DISP_GAMMA ||
> > +           type == MTK_DISP_DSC ||
> 
> Alphabetic order.
> 
OK, I'll fix it.
> >             type == MTK_DPI ||
> >             type == MTK_DSI ||
> >             type == MTK_DISP_OVL ||
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index bb914d976cf5..661fb620e266 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -34,6 +34,7 @@ enum mtk_ddp_comp_type {
> >         MTK_DISP_MUTEX,
> >         MTK_DISP_OD,
> >         MTK_DISP_BLS,
> > +       MTK_DISP_DSC,
> >         MTK_DDP_COMP_TYPE_MAX,
> >  };
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index d6f6d1bdad85..7dfca63c1042 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -446,6 +446,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >           .data = (void *)MTK_DISP_GAMMA, },
> >         { .compatible = "mediatek,mt8183-disp-dither",
> >           .data = (void *)MTK_DISP_DITHER },
> > +       { .compatible = "mediatek,mt8195-disp-dsc",
> > +         .data = (void *)MTK_DISP_DSC },
> >         { .compatible = "mediatek,mt8173-disp-ufoe",
> >           .data = (void *)MTK_DISP_UFOE },
> >         { .compatible = "mediatek,mt2701-dsi",
> > @@ -563,6 +565,7 @@ static int mtk_drm_probe(struct platform_device
> > *pdev)
> >                 if (comp_type == MTK_DISP_CCORR ||
> >                     comp_type == MTK_DISP_COLOR ||
> >                     comp_type == MTK_DISP_GAMMA ||
> > +                   comp_type == MTK_DISP_DSC ||
> >                     comp_type == MTK_DISP_OVL ||
> >                     comp_type == MTK_DISP_OVL_2L ||
> >                     comp_type == MTK_DISP_RDMA ||
> > @@ -667,6 +670,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> >         &mtk_disp_rdma_driver,
> >         &mtk_dpi_driver,
> >         &mtk_drm_platform_driver,
> > +       &mtk_disp_dsc_driver,
> 
> Alphabetic order.
> 
OK, I'll fix it.

> >         &mtk_dsi_driver,
> >  };
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index 637f5669e895..8b722330ef7d 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -51,6 +51,7 @@ extern struct platform_driver
> > mtk_disp_color_driver;
> >  extern struct platform_driver mtk_disp_gamma_driver;
> >  extern struct platform_driver mtk_disp_ovl_driver;
> >  extern struct platform_driver mtk_disp_rdma_driver;
> > +extern struct platform_driver mtk_disp_dsc_driver;
> 
> Alphabetic order.
> 
> Regards,
> Chun-Kuang.
> 
OK, I'll fix it.

Regards,
Jason-JH.Lin
> >  extern struct platform_driver mtk_dpi_driver;
> >  extern struct platform_driver mtk_dsi_driver;
> > 
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v2 9/9] drm/mediatek: add MERGE support for mt8195

[jason-jh.lin]

1. Add MERGE module file.
2. Add REG_FLD macro in mtk_dem_crtc header to support
   bitwise register settings.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 525 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_crtc.h     |  14 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  16 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 8 files changed, 570 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index a1b239135c8f..9044c5aabae1 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_ccorr.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_rdma.o \
 		  mtk_disp_dsc.o \
+		  mtk_disp_merge.o \
 		  mtk_drm_crtc.o \
 		  mtk_drm_ddp_comp.o \
 		  mtk_drm_drv.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 128d9fdbaf9e..dfb078541430 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -97,4 +97,12 @@ void mtk_dsc_config(struct device *dev, unsigned int width,
 void mtk_dsc_start(struct device *dev);
 void mtk_dsc_stop(struct device *dev);
 
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+		      unsigned int height, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
 #endif
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..b7d633ca2f71
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,525 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL (0x000)
+#define FLD_MERGE_EN BIT(0)
+#define FLD_MERGE_RST BIT(4)
+#define FLD_MERGE_LR_SWAP BIT(8)
+#define FLD_MERGE_DCM_DIS BIT(12)
+
+#define DISP_REG_MERGE_WIDTH (0x004)
+#define FLD_IN_WIDHT_L GENMASK(15, 0)
+#define FLD_IN_WIDHT_R GENMASK(31, 16)
+
+#define DISP_REG_MERGE_HEIGHT (0x008)
+#define FLD_IN_HEIGHT GENMASK(15, 0)
+
+#define DISP_REG_MERGE_SHADOW_CRTL (0x00c)
+
+#define DISP_REG_MERGE_DGB0 (0x010)
+#define FLD_PIXEL_CNT GENMASK(15, 0)
+#define FLD_MERGE_STATE GENMASK(17, 16)
+
+#define DISP_REG_MERGE_DGB1 (0x014)
+#define FLD_LINE_CNT GENMASK(15, 0)
+
+#define DISP_REG_MERGE_CFG2_0 (0x160)
+
+#define DISP_REG_MERGE_CFG2_2 (0x168)
+
+#define DISP_MERGE_CFG_0		0x010
+#define DISP_MERGE_CFG_1		0x014
+#define DISP_MERGE_CFG_4		0x020
+#define DISP_MERGE_CFG_5		0x024
+#define DISP_MERGE_CFG_8		0x030
+#define DISP_MERGE_CFG_9		0x034
+#define DISP_MERGE_CFG_10	0x038
+#define DISP_MERGE_CFG_11	0x03c
+#define DISP_MERGE_CFG_12	0x040
+#define CFG_11_11_1PI_1PO_BYPASS	1
+#define CFG_11_11_2PI_2PO_BYPASS	2
+#define CFG_10_10_2PI_1PO_BYPASS	3
+#define CFG_10_10_2PI_2PO_BYPASS	4
+#define CFG_10_10_1PI_1PO_BUF_MODE	5
+#define CFG_10_10_1PI_2PO_BUF_MODE	6
+#define CFG_10_10_2PI_1PO_BUF_MODE	7
+#define CFG_10_10_2PI_2PO_BUF_MODE	8
+#define CFG_10_01_1PI_1PO_BUF_MODE	9
+#define CFG_10_01_2PI_1PO_BUF_MODE	10
+#define CFG_01_10_1PI_1PO_BUF_MODE	11
+#define CFG_01_10_1PI_2PO_BUF_MODE	12
+#define CFG_01_01_1PI_1PO_BUF_MODE	13
+#define CFG_10_11_1PI_1PO_SPLIT		14
+#define CFG_10_11_2PI_1PO_SPLIT		15
+#define CFG_01_11_1PI_1PO_SPLIT		16
+#define CFG_11_10_1PI_1PO_MERGE		17
+#define CFG_11_10_1PI_2PO_MERGE		18
+#define CFG_10_10_1PI_1PO_TO422		19
+#define CFG_10_10_1PI_2PO_TO444		20
+#define CFG_10_10_2PI_2PO_TO444		21
+#define DISP_MERGE_CFG_13	0x044
+#define DISP_MERGE_CFG_14	0x048
+#define DISP_MERGE_CFG_15	0x04c
+#define DISP_MERGE_CFG_17	0x054
+#define DISP_MERGE_CFG_18	0x058
+#define DISP_MERGE_CFG_19	0x05c
+#define DISP_MERGE_CFG_20	0x060
+#define DISP_MERGE_CFG_21	0x064
+#define DISP_MERGE_CFG_22	0x068
+#define DISP_MERGE_CFG_23	0x06c
+#define DISP_MERGE_CFG_24	0x070
+#define DISP_MERGE_CFG_25	0x074
+#define DISP_MERGE_CFG_26	0x078
+#define DISP_MERGE_CFG_27	0x07c
+#define DISP_MERGE_CFG_28	0x080
+#define DISP_MERGE_CFG_29	0x084
+#define DISP_MERGE_CFG_36	0x0a0
+#define DISP_MERGE_CFG_36_FLD_ULTRA_EN \
+	REG_FLD(1, 0)
+#define DISP_MERGE_CFG_36_FLD_PREULTRA_EN \
+	REG_FLD(1, 4)
+#define DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN \
+	REG_FLD(1, 8)
+#define DISP_MERGE_CFG_36_VAL_ULTRA_EN(val) \
+	REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_ULTRA_EN, val)
+#define DISP_MERGE_CFG_36_VAL_PREULTRA_EN(val) \
+	REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_PREULTRA_EN, val)
+#define DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN(val) \
+	REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN, val)
+#define DISP_MERGE_CFG_37	0x0a4
+#define DISP_MERGE_CFG_37_FLD_BUFFER_MODE \
+	REG_FLD(2, 0)
+#define DISP_MERGE_CFG_37_VAL_BUFFER_MODE(val) \
+	REG_FLD_VAL(DISP_MERGE_CFG_37_FLD_BUFFER_MODE, val)
+#define DISP_MERGE_CFG_38	0x0a8
+#define DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA \
+	REG_FLD(1, 0)
+#define DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA \
+	REG_FLD(1, 4)
+#define DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH \
+	REG_FLD(16, 16)
+#define DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA(val) \
+	REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA, val)
+#define DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA(val) \
+	REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA, val)
+#define DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH(val) \
+	REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH, val)
+#define DISP_MERGE_CFG_39	0x0ac
+#define DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA \
+	REG_FLD(1, 8)
+#define DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA \
+	REG_FLD(1, 12)
+#define DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH \
+	REG_FLD(16, 16)
+#define DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA(val) \
+	REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA, val)
+#define DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA(val) \
+	REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA, val)
+#define DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH(val) \
+	REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH, val)
+#define DISP_MERGE_CFG_40	0x0b0
+#define DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW \
+	REG_FLD(16, 0)
+#define DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH \
+	REG_FLD(16, 16)
+#define DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW(val) \
+	REG_FLD_VAL(DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW, (val))
+#define DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH(val) \
+	REG_FLD_VAL(DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH, val)
+#define DISP_MERGE_CFG_41	0x0b4
+#define DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW \
+	REG_FLD(16, 0)
+#define DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH \
+	REG_FLD(16, 16)
+#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW(val) \
+	REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW, val)
+#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(val) \
+	REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH, val)
+
+struct mtk_merge_config_struct {
+	unsigned short width_right;
+	unsigned short width_left;
+	unsigned int height;
+	unsigned int fmt;
+	unsigned int mode;
+	unsigned int swap;
+};
+
+struct mtk_disp_merge {
+	enum mtk_ddp_comp_id comp_id;
+	struct drm_crtc *crtc;
+	struct clk *clk;
+	struct clk *async_clk;
+	void __iomem *regs;
+	struct cmdq_client_reg		cmdq_reg;
+	int irq;
+	bool need_golden_setting;
+	enum mtk_ddp_comp_id gs_comp_id;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	mtk_ddp_write(NULL, 0x1, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	mtk_ddp_write(NULL, 0x0, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CTRL);
+}
+
+static int mtk_merge_check_params(struct mtk_merge_config_struct *merge_config)
+{
+	if (!merge_config->height ||
+	    !merge_config->width_left || !merge_config->width_right) {
+		pr_err("%s:merge input width l(%u) w(%u) h(%u)\n",
+		       __func__, merge_config->width_left,
+		       merge_config->width_right, merge_config->height);
+		return -EINVAL;
+	}
+	pr_debug("%s:merge input width l(%u) r(%u) height(%u)\n",
+		 __func__, merge_config->width_left,
+		 merge_config->width_right, merge_config->height);
+	return 0;
+}
+
+static int mtk_merge_golden_setting(struct mtk_disp_merge *priv,
+				    struct cmdq_pkt *handle)
+{
+	int ultra_en = 1;
+	int preultra_en = 1;
+	int halt_for_dvfs_en = 0;
+	int buffer_mode = 3;
+	int vde_block_ultra = 0;
+	int valid_th_block_ultra = 0;
+	int ultra_fifo_valid_th = 0;
+	int nvde_force_preultra = 0;
+	int nvalid_th_force_preultra = 0;
+	int preultra_fifo_valid_th = 0;
+	int ultra_th_low = 0xe10;
+	int ultra_th_high = 0x12c0;
+	int preultra_th_low = 0x12c0;
+	int preultra_th_high = 0x1518;
+
+	mtk_ddp_write_mask(handle,
+			   DISP_MERGE_CFG_36_VAL_ULTRA_EN
+				(ultra_en) |
+			   DISP_MERGE_CFG_36_VAL_PREULTRA_EN
+				(preultra_en) |
+			   DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN
+				(halt_for_dvfs_en),
+			   &priv->cmdq_reg, priv->regs,
+			   DISP_MERGE_CFG_36,
+			   REG_FLD_MASK
+				(DISP_MERGE_CFG_36_FLD_ULTRA_EN) |
+			   REG_FLD_MASK
+				(DISP_MERGE_CFG_36_FLD_PREULTRA_EN) |
+			   REG_FLD_MASK
+				(DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN));
+
+	mtk_ddp_write_mask(handle,
+			   DISP_MERGE_CFG_37_VAL_BUFFER_MODE
+				(buffer_mode),
+			   &priv->cmdq_reg, priv->regs,
+			   DISP_MERGE_CFG_37,
+			   REG_FLD_MASK
+				(DISP_MERGE_CFG_37_FLD_BUFFER_MODE));
+
+	mtk_ddp_write_mask(handle,
+			   DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA
+				(vde_block_ultra) |
+			   DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA
+				(valid_th_block_ultra) |
+			   DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH
+				(ultra_fifo_valid_th),
+			   &priv->cmdq_reg, priv->regs,
+			   DISP_MERGE_CFG_38,
+			   REG_FLD_MASK
+				(DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA) |
+			   REG_FLD_MASK
+				(DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA) |
+			   REG_FLD_MASK
+				(DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH));
+
+	mtk_ddp_write_mask(handle,
+			   DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA
+				(nvde_force_preultra) |
+			   DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA
+				(nvalid_th_force_preultra) |
+			   DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH
+				(preultra_fifo_valid_th),
+			   &priv->cmdq_reg, priv->regs,
+			   DISP_MERGE_CFG_39,
+			   REG_FLD_MASK
+				(DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA) |
+			   REG_FLD_MASK
+				(DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA) |
+			   REG_FLD_MASK
+				(DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH));
+
+	mtk_ddp_write_mask(handle,
+			   DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW
+				(ultra_th_low) |
+			   DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH
+				(ultra_th_high),
+			   &priv->cmdq_reg, priv->regs,
+			   DISP_MERGE_CFG_40,
+			   REG_FLD_MASK
+				(DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW) |
+			   REG_FLD_MASK
+				(DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH));
+
+	mtk_ddp_write_mask(handle,
+			   DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW
+				(preultra_th_low) |
+			   DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH
+				(preultra_th_high),
+			   &priv->cmdq_reg, priv->regs,
+			   DISP_MERGE_CFG_41,
+			   REG_FLD_MASK
+				(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW) |
+			   REG_FLD_MASK
+				(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH));
+
+	return 0;
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+		      unsigned int h, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *handle)
+{
+	struct mtk_merge_config_struct merge_config;
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	/*golden setting*/
+	if (priv->need_golden_setting &&
+	    priv->gs_comp_id == priv->comp_id)
+		mtk_merge_golden_setting(priv, handle);
+
+	switch (priv->comp_id) {
+	case DDP_COMPONENT_MERGE0:
+		merge_config.mode = CFG_10_10_1PI_2PO_BUF_MODE;
+		merge_config.width_left = w;
+		merge_config.width_right = w;
+		merge_config.height = h;
+		merge_config.swap = 0;
+		break;
+	case DDP_COMPONENT_MERGE5:
+		merge_config.mode = CFG_10_10_2PI_2PO_BUF_MODE;
+		merge_config.width_left = w;
+		merge_config.width_right = w;
+		merge_config.height = h;
+		merge_config.swap = 0;
+		break;
+	default:
+		pr_err("No find component merge %d\n", priv->comp_id);
+		return;
+	}
+
+	mtk_merge_check_params(&merge_config);
+
+	switch (merge_config.mode) {
+	case CFG_10_10_1PI_2PO_BUF_MODE:
+	case CFG_10_10_2PI_2PO_BUF_MODE:
+		mtk_ddp_write_mask(handle,
+				   (merge_config.height << 16 |
+				   merge_config.width_left),
+				   &priv->cmdq_reg, priv->regs,
+				   DISP_MERGE_CFG_0, ~0);
+
+		mtk_ddp_write_mask(handle,
+				   (merge_config.height << 16 |
+				   merge_config.width_left),
+				   &priv->cmdq_reg, priv->regs,
+				   DISP_MERGE_CFG_4, ~0);
+
+		mtk_ddp_write_mask(handle,
+				   (merge_config.height << 16 |
+				   merge_config.width_left),
+				   &priv->cmdq_reg, priv->regs,
+				   DISP_MERGE_CFG_24, ~0);
+
+		mtk_ddp_write_mask(handle,
+				   (merge_config.height << 16 |
+				   merge_config.width_left),
+				   &priv->cmdq_reg, priv->regs,
+				   DISP_MERGE_CFG_25, ~0);
+
+		mtk_ddp_write_mask(handle,
+				   merge_config.swap,
+				   &priv->cmdq_reg, priv->regs,
+				   DISP_MERGE_CFG_10, 0x1f);
+	break;
+	default:
+	break;
+	}
+	mtk_ddp_write_mask(handle, merge_config.mode,
+			   &priv->cmdq_reg, priv->regs,
+			   DISP_MERGE_CFG_12, 0x1f);
+	mtk_ddp_write_mask(handle, 0x1,
+			   &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CTRL, 0x1);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+	int ret = 0;
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	ret = pm_runtime_get_sync(dev);
+
+	if (priv->clk) {
+		ret = clk_prepare_enable(priv->clk);
+		if (ret)
+			pr_err("merge clk prepare enable failed\n");
+	}
+
+	if (priv->async_clk) {
+		ret = clk_prepare_enable(priv->async_clk);
+		if (ret)
+			pr_err("async clk prepare enable failed\n");
+	}
+
+	return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	if (priv->async_clk)
+		clk_disable_unprepare(priv->async_clk);
+
+	if (priv->clk)
+		clk_disable_unprepare(priv->clk);
+
+	pm_runtime_put_sync(dev);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+				  void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+	.bind	= mtk_disp_merge_bind,
+	.unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct mtk_disp_merge *priv;
+	enum mtk_ddp_comp_id comp_id;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_MERGE);
+	if ((int)comp_id < 0) {
+		dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
+		return comp_id;
+	}
+
+	priv->comp_id = comp_id;
+	priv->need_golden_setting = true;
+	priv->gs_comp_id = DDP_COMPONENT_MERGE5;
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get merge clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to ioremap merge\n");
+		return PTR_ERR(priv->regs);
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+	priv->irq = platform_get_irq(pdev, 0);
+	if (priv->irq < 0)
+		priv->irq = 0;
+
+	priv->async_clk = of_clk_get(dev->of_node, 1);
+	if (IS_ERR(priv->async_clk)) {
+		ret = PTR_ERR(priv->async_clk);
+		dev_dbg(dev, "No merge async clock: %d\n", ret);
+		priv->async_clk = NULL;
+	}
+
+	platform_set_drvdata(pdev, priv);
+
+	pm_runtime_enable(dev);
+
+	ret = component_add(dev, &mtk_disp_merge_component_ops);
+	if (ret != 0) {
+		dev_err(dev, "Failed to add component: %d\n", ret);
+		pm_runtime_disable(dev);
+	}
+
+	return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+	pm_runtime_disable(&pdev->dev);
+
+	return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8195-disp-merge", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+	.probe = mtk_disp_merge_probe,
+	.remove = mtk_disp_merge_remove,
+	.driver = {
+		.name = "mediatek-disp-merge",
+		.owner = THIS_MODULE,
+		.of_match_table = mtk_disp_merge_driver_dt_match,
+	},
+};
+
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index cb9a36c48d4f..66d1cf03dfe8 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -14,6 +14,20 @@
 #define MTK_MAX_BPC	10
 #define MTK_MIN_BPC	3
 
+#define REG_FLD(width, shift) \
+	((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
+
+#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
+
+#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
+
+#define REG_FLD_MASK(field) \
+	((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
+	 << REG_FLD_SHIFT(field))
+
+#define REG_FLD_VAL(field, val) \
+	(((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
+
 void mtk_drm_crtc_commit(struct drm_crtc *crtc);
 int mtk_drm_crtc_create(struct drm_device *drm_dev,
 			const enum mtk_ddp_comp_id *path,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index d0b0f41dfe5a..fb5f260f5ae0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -341,6 +341,14 @@ static const struct mtk_ddp_comp_funcs ddp_dsc = {
 	.clk_disable = mtk_dsc_clk_disable,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+	.clk_enable = mtk_merge_clk_enable,
+	.clk_disable = mtk_merge_clk_disable,
+	.start = mtk_merge_start,
+	.stop = mtk_merge_stop,
+	.config = mtk_merge_config,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_ufoe = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -365,6 +373,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_OD] = "od",
 	[MTK_DISP_BLS] = "bls",
 	[MTK_DISP_DSC] = "dsc",
+	[MTK_DISP_MERGE] = "merge",
 };
 
 struct mtk_ddp_comp_match {
@@ -403,6 +412,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DSC0]	= { MTK_DISP_DSC,	0, &ddp_dsc },
 	[DDP_COMPONENT_DSC1]	= { MTK_DISP_DSC,	1, &ddp_dsc },
 	[DDP_COMPONENT_DSC1_VIRTUAL0]	= { MTK_DISP_DSC,	-1, &ddp_dsc },
+	[DDP_COMPONENT_MERGE0]	= { MTK_DISP_MERGE,	0, &ddp_merge },
+	[DDP_COMPONENT_MERGE1]	= { MTK_DISP_MERGE,	1, &ddp_merge },
+	[DDP_COMPONENT_MERGE2]	= { MTK_DISP_MERGE,	2, &ddp_merge },
+	[DDP_COMPONENT_MERGE3]	= { MTK_DISP_MERGE,	3, &ddp_merge },
+	[DDP_COMPONENT_MERGE4]	= { MTK_DISP_MERGE,	4, &ddp_merge },
+	[DDP_COMPONENT_MERGE5]	= { MTK_DISP_MERGE,	5, &ddp_merge },
 	[DDP_COMPONENT_UFOE]	= { MTK_DISP_UFOE,	0, &ddp_ufoe },
 	[DDP_COMPONENT_WDMA0]	= { MTK_DISP_WDMA,	0, NULL },
 	[DDP_COMPONENT_WDMA1]	= { MTK_DISP_WDMA,	1, NULL },
@@ -522,6 +537,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
 	    type == MTK_DISP_DSC ||
+	    type == MTK_DISP_MERGE ||
 	    type == MTK_DPI ||
 	    type == MTK_DSI ||
 	    type == MTK_DISP_OVL ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 661fb620e266..0afd78c0bc92 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -35,6 +35,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_OD,
 	MTK_DISP_BLS,
 	MTK_DISP_DSC,
+	MTK_DISP_MERGE,
 	MTK_DDP_COMP_TYPE_MAX,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 7dfca63c1042..24599fc0a597 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -448,6 +448,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_DITHER },
 	{ .compatible = "mediatek,mt8195-disp-dsc",
 	  .data = (void *)MTK_DISP_DSC },
+	{ .compatible = "mediatek,mt8195-disp-merge",
+	  .data = (void *)MTK_DISP_MERGE },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
 	  .data = (void *)MTK_DISP_UFOE },
 	{ .compatible = "mediatek,mt2701-dsi",
@@ -566,6 +568,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		    comp_type == MTK_DISP_COLOR ||
 		    comp_type == MTK_DISP_GAMMA ||
 		    comp_type == MTK_DISP_DSC ||
+		    comp_type == MTK_DISP_MERGE ||
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
@@ -671,6 +674,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_dpi_driver,
 	&mtk_drm_platform_driver,
 	&mtk_disp_dsc_driver,
+	&mtk_disp_merge_driver,
 	&mtk_dsi_driver,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 8b722330ef7d..c4d802a43531 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -52,6 +52,7 @@ extern struct platform_driver mtk_disp_gamma_driver;
 extern struct platform_driver mtk_disp_ovl_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
 extern struct platform_driver mtk_disp_dsc_driver;
+extern struct platform_driver mtk_disp_merge_driver;
 extern struct platform_driver mtk_dpi_driver;
 extern struct platform_driver mtk_dsi_driver;
 
-- 
2.18.0
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Linux-mediatek@lists.infradead.org
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Re: [PATCH v2 9/9] drm/mediatek: add MERGE support for mt8195

[Chun-Kuang Hu]

 Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
>
> 1. Add MERGE module file.
> 2. Add REG_FLD macro in mtk_dem_crtc header to support
>    bitwise register settings.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/Makefile           |   1 +
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
>  drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 525 ++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.h     |  14 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  16 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
>  8 files changed, 570 insertions(+)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index a1b239135c8f..9044c5aabae1 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_ccorr.o \
>                   mtk_disp_ovl.o \
>                   mtk_disp_rdma.o \
>                   mtk_disp_dsc.o \
> +                 mtk_disp_merge.o \
>                   mtk_drm_crtc.o \
>                   mtk_drm_ddp_comp.o \
>                   mtk_drm_drv.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 128d9fdbaf9e..dfb078541430 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -97,4 +97,12 @@ void mtk_dsc_config(struct device *dev, unsigned int width,
>  void mtk_dsc_start(struct device *dev);
>  void mtk_dsc_stop(struct device *dev);
>
> +int mtk_merge_clk_enable(struct device *dev);
> +void mtk_merge_clk_disable(struct device *dev);
> +void mtk_merge_config(struct device *dev, unsigned int width,
> +                     unsigned int height, unsigned int vrefresh,
> +                     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_start(struct device *dev);
> +void mtk_merge_stop(struct device *dev);
> +
>  #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> new file mode 100644
> index 000000000000..b7d633ca2f71
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -0,0 +1,525 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_disp_drv.h"
> +
> +#define DISP_REG_MERGE_CTRL (0x000)
> +#define FLD_MERGE_EN BIT(0)
> +#define FLD_MERGE_RST BIT(4)
> +#define FLD_MERGE_LR_SWAP BIT(8)
> +#define FLD_MERGE_DCM_DIS BIT(12)
> +
> +#define DISP_REG_MERGE_WIDTH (0x004)
> +#define FLD_IN_WIDHT_L GENMASK(15, 0)
> +#define FLD_IN_WIDHT_R GENMASK(31, 16)
> +
> +#define DISP_REG_MERGE_HEIGHT (0x008)
> +#define FLD_IN_HEIGHT GENMASK(15, 0)
> +
> +#define DISP_REG_MERGE_SHADOW_CRTL (0x00c)
> +
> +#define DISP_REG_MERGE_DGB0 (0x010)
> +#define FLD_PIXEL_CNT GENMASK(15, 0)
> +#define FLD_MERGE_STATE GENMASK(17, 16)
> +
> +#define DISP_REG_MERGE_DGB1 (0x014)
> +#define FLD_LINE_CNT GENMASK(15, 0)
> +
> +#define DISP_REG_MERGE_CFG2_0 (0x160)
> +
> +#define DISP_REG_MERGE_CFG2_2 (0x168)
> +
> +#define DISP_MERGE_CFG_0               0x010
> +#define DISP_MERGE_CFG_1               0x014
> +#define DISP_MERGE_CFG_4               0x020
> +#define DISP_MERGE_CFG_5               0x024
> +#define DISP_MERGE_CFG_8               0x030
> +#define DISP_MERGE_CFG_9               0x034
> +#define DISP_MERGE_CFG_10      0x038
> +#define DISP_MERGE_CFG_11      0x03c
> +#define DISP_MERGE_CFG_12      0x040
> +#define CFG_11_11_1PI_1PO_BYPASS       1
> +#define CFG_11_11_2PI_2PO_BYPASS       2
> +#define CFG_10_10_2PI_1PO_BYPASS       3
> +#define CFG_10_10_2PI_2PO_BYPASS       4
> +#define CFG_10_10_1PI_1PO_BUF_MODE     5
> +#define CFG_10_10_1PI_2PO_BUF_MODE     6
> +#define CFG_10_10_2PI_1PO_BUF_MODE     7
> +#define CFG_10_10_2PI_2PO_BUF_MODE     8
> +#define CFG_10_01_1PI_1PO_BUF_MODE     9
> +#define CFG_10_01_2PI_1PO_BUF_MODE     10
> +#define CFG_01_10_1PI_1PO_BUF_MODE     11
> +#define CFG_01_10_1PI_2PO_BUF_MODE     12
> +#define CFG_01_01_1PI_1PO_BUF_MODE     13
> +#define CFG_10_11_1PI_1PO_SPLIT                14
> +#define CFG_10_11_2PI_1PO_SPLIT                15
> +#define CFG_01_11_1PI_1PO_SPLIT                16
> +#define CFG_11_10_1PI_1PO_MERGE                17
> +#define CFG_11_10_1PI_2PO_MERGE                18
> +#define CFG_10_10_1PI_1PO_TO422                19
> +#define CFG_10_10_1PI_2PO_TO444                20
> +#define CFG_10_10_2PI_2PO_TO444                21
> +#define DISP_MERGE_CFG_13      0x044

Useless, so remove.

> +#define DISP_MERGE_CFG_14      0x048
> +#define DISP_MERGE_CFG_15      0x04c
> +#define DISP_MERGE_CFG_17      0x054
> +#define DISP_MERGE_CFG_18      0x058
> +#define DISP_MERGE_CFG_19      0x05c
> +#define DISP_MERGE_CFG_20      0x060
> +#define DISP_MERGE_CFG_21      0x064
> +#define DISP_MERGE_CFG_22      0x068
> +#define DISP_MERGE_CFG_23      0x06c
> +#define DISP_MERGE_CFG_24      0x070
> +#define DISP_MERGE_CFG_25      0x074
> +#define DISP_MERGE_CFG_26      0x078
> +#define DISP_MERGE_CFG_27      0x07c
> +#define DISP_MERGE_CFG_28      0x080
> +#define DISP_MERGE_CFG_29      0x084
> +#define DISP_MERGE_CFG_36      0x0a0
> +#define DISP_MERGE_CFG_36_FLD_ULTRA_EN \
> +       REG_FLD(1, 0)
> +#define DISP_MERGE_CFG_36_FLD_PREULTRA_EN \
> +       REG_FLD(1, 4)
> +#define DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN \
> +       REG_FLD(1, 8)
> +#define DISP_MERGE_CFG_36_VAL_ULTRA_EN(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_ULTRA_EN, val)
> +#define DISP_MERGE_CFG_36_VAL_PREULTRA_EN(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_PREULTRA_EN, val)
> +#define DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN, val)
> +#define DISP_MERGE_CFG_37      0x0a4
> +#define DISP_MERGE_CFG_37_FLD_BUFFER_MODE \
> +       REG_FLD(2, 0)
> +#define DISP_MERGE_CFG_37_VAL_BUFFER_MODE(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_37_FLD_BUFFER_MODE, val)
> +#define DISP_MERGE_CFG_38      0x0a8
> +#define DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA \
> +       REG_FLD(1, 0)
> +#define DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA \
> +       REG_FLD(1, 4)
> +#define DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH \
> +       REG_FLD(16, 16)
> +#define DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA, val)
> +#define DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA, val)
> +#define DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH, val)
> +#define DISP_MERGE_CFG_39      0x0ac
> +#define DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA \
> +       REG_FLD(1, 8)
> +#define DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA \
> +       REG_FLD(1, 12)
> +#define DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH \
> +       REG_FLD(16, 16)
> +#define DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA, val)
> +#define DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA, val)
> +#define DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH, val)
> +#define DISP_MERGE_CFG_40      0x0b0
> +#define DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW \
> +       REG_FLD(16, 0)
> +#define DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH \
> +       REG_FLD(16, 16)
> +#define DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW, (val))
> +#define DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH, val)
> +#define DISP_MERGE_CFG_41      0x0b4
> +#define DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW \
> +       REG_FLD(16, 0)
> +#define DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH \
> +       REG_FLD(16, 16)
> +#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW, val)
> +#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH, val)
> +
> +struct mtk_merge_config_struct {
> +       unsigned short width_right;
> +       unsigned short width_left;
> +       unsigned int height;
> +       unsigned int fmt;
> +       unsigned int mode;
> +       unsigned int swap;
> +};
> +
> +struct mtk_disp_merge {
> +       enum mtk_ddp_comp_id comp_id;
> +       struct drm_crtc *crtc;
> +       struct clk *clk;
> +       struct clk *async_clk;
> +       void __iomem *regs;
> +       struct cmdq_client_reg          cmdq_reg;
> +       int irq;
> +       bool need_golden_setting;

need_golden_setting is always true, so remove this.

> +       enum mtk_ddp_comp_id gs_comp_id;
> +};
> +
> +void mtk_merge_start(struct device *dev)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       mtk_ddp_write(NULL, 0x1, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_MERGE_CTRL);

One line.

> +}
> +
> +void mtk_merge_stop(struct device *dev)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       mtk_ddp_write(NULL, 0x0, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_MERGE_CTRL);
> +}
> +
> +static int mtk_merge_check_params(struct mtk_merge_config_struct *merge_config)
> +{
> +       if (!merge_config->height ||
> +           !merge_config->width_left || !merge_config->width_right) {
> +               pr_err("%s:merge input width l(%u) w(%u) h(%u)\n",
> +                      __func__, merge_config->width_left,
> +                      merge_config->width_right, merge_config->height);
> +               return -EINVAL;
> +       }
> +       pr_debug("%s:merge input width l(%u) r(%u) height(%u)\n",
> +                __func__, merge_config->width_left,
> +                merge_config->width_right, merge_config->height);
> +       return 0;
> +}
> +
> +static int mtk_merge_golden_setting(struct mtk_disp_merge *priv,
> +                                   struct cmdq_pkt *handle)
> +{
> +       int ultra_en = 1;
> +       int preultra_en = 1;
> +       int halt_for_dvfs_en = 0;
> +       int buffer_mode = 3;
> +       int vde_block_ultra = 0;
> +       int valid_th_block_ultra = 0;
> +       int ultra_fifo_valid_th = 0;
> +       int nvde_force_preultra = 0;
> +       int nvalid_th_force_preultra = 0;
> +       int preultra_fifo_valid_th = 0;
> +       int ultra_th_low = 0xe10;
> +       int ultra_th_high = 0x12c0;
> +       int preultra_th_low = 0x12c0;
> +       int preultra_th_high = 0x1518;

I do not like a 'golden setting' which means we have no knowledge to
control these value for some special case.
Could you explain the logic why we set these value?

> +
> +       mtk_ddp_write_mask(handle,
> +                          DISP_MERGE_CFG_36_VAL_ULTRA_EN
> +                               (ultra_en) |
> +                          DISP_MERGE_CFG_36_VAL_PREULTRA_EN
> +                               (preultra_en) |
> +                          DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN
> +                               (halt_for_dvfs_en),
> +                          &priv->cmdq_reg, priv->regs,
> +                          DISP_MERGE_CFG_36,
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_36_FLD_ULTRA_EN) |
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_36_FLD_PREULTRA_EN) |
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN));
> +
> +       mtk_ddp_write_mask(handle,
> +                          DISP_MERGE_CFG_37_VAL_BUFFER_MODE
> +                               (buffer_mode),
> +                          &priv->cmdq_reg, priv->regs,
> +                          DISP_MERGE_CFG_37,
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_37_FLD_BUFFER_MODE));
> +
> +       mtk_ddp_write_mask(handle,
> +                          DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA
> +                               (vde_block_ultra) |
> +                          DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA
> +                               (valid_th_block_ultra) |
> +                          DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH
> +                               (ultra_fifo_valid_th),
> +                          &priv->cmdq_reg, priv->regs,
> +                          DISP_MERGE_CFG_38,
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA) |
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA) |
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH));
> +
> +       mtk_ddp_write_mask(handle,
> +                          DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA
> +                               (nvde_force_preultra) |
> +                          DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA
> +                               (nvalid_th_force_preultra) |
> +                          DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH
> +                               (preultra_fifo_valid_th),
> +                          &priv->cmdq_reg, priv->regs,
> +                          DISP_MERGE_CFG_39,
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA) |
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA) |
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH));
> +
> +       mtk_ddp_write_mask(handle,
> +                          DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW
> +                               (ultra_th_low) |
> +                          DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH
> +                               (ultra_th_high),
> +                          &priv->cmdq_reg, priv->regs,
> +                          DISP_MERGE_CFG_40,
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW) |
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH));
> +
> +       mtk_ddp_write_mask(handle,
> +                          DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW
> +                               (preultra_th_low) |
> +                          DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH
> +                               (preultra_th_high),
> +                          &priv->cmdq_reg, priv->regs,
> +                          DISP_MERGE_CFG_41,
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW) |
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH));
> +
> +       return 0;
> +}
> +
> +void mtk_merge_config(struct device *dev, unsigned int w,
> +                     unsigned int h, unsigned int vrefresh,
> +                     unsigned int bpc, struct cmdq_pkt *handle)
> +{
> +       struct mtk_merge_config_struct merge_config;
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       /*golden setting*/
> +       if (priv->need_golden_setting &&
> +           priv->gs_comp_id == priv->comp_id)
> +               mtk_merge_golden_setting(priv, handle);

Why only MERGE_5 set the fifo setting? I think all merge should set
fifo setting.

> +
> +       switch (priv->comp_id) {
> +       case DDP_COMPONENT_MERGE0:
> +               merge_config.mode = CFG_10_10_1PI_2PO_BUF_MODE;

Please explain what the mode means.

> +               merge_config.width_left = w;
> +               merge_config.width_right = w;
> +               merge_config.height = h;
> +               merge_config.swap = 0;
> +               break;
> +       case DDP_COMPONENT_MERGE5:
> +               merge_config.mode = CFG_10_10_2PI_2PO_BUF_MODE;
> +               merge_config.width_left = w;
> +               merge_config.width_right = w;
> +               merge_config.height = h;
> +               merge_config.swap = 0;
> +               break;
> +       default:
> +               pr_err("No find component merge %d\n", priv->comp_id);
> +               return;
> +       }
> +
> +       mtk_merge_check_params(&merge_config);
> +
> +       switch (merge_config.mode) {
> +       case CFG_10_10_1PI_2PO_BUF_MODE:
> +       case CFG_10_10_2PI_2PO_BUF_MODE:

Remove 'switch' because these two cases are always true.

> +               mtk_ddp_write_mask(handle,
> +                                  (merge_config.height << 16 |
> +                                  merge_config.width_left),
> +                                  &priv->cmdq_reg, priv->regs,
> +                                  DISP_MERGE_CFG_0, ~0);

mtk_ddp_write(handle, h << 16 | w, &priv->comdq_reg, priv->regs,
DISP_MERGE_CFG_0);

> +
> +               mtk_ddp_write_mask(handle,
> +                                  (merge_config.height << 16 |
> +                                  merge_config.width_left),
> +                                  &priv->cmdq_reg, priv->regs,
> +                                  DISP_MERGE_CFG_4, ~0);

mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
DISP_MERGE_CFG_4);

> +
> +               mtk_ddp_write_mask(handle,
> +                                  (merge_config.height << 16 |
> +                                  merge_config.width_left),
> +                                  &priv->cmdq_reg, priv->regs,
> +                                  DISP_MERGE_CFG_24, ~0);

mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
DISP_MERGE_CFG_24);

> +
> +               mtk_ddp_write_mask(handle,
> +                                  (merge_config.height << 16 |
> +                                  merge_config.width_left),
> +                                  &priv->cmdq_reg, priv->regs,
> +                                  DISP_MERGE_CFG_25, ~0);
> +

mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
DISP_MERGE_CFG_25);

> +               mtk_ddp_write_mask(handle,
> +                                  merge_config.swap,
> +                                  &priv->cmdq_reg, priv->regs,
> +                                  DISP_MERGE_CFG_10, 0x1f);

/* no swap */
mtk_ddp_write_mask(handle, 0, &priv->cmdq_reg, priv->regs,
DISP_MERGE_CFG_10, 0x1f);

> +       break;
> +       default:
> +       break;
> +       }
> +       mtk_ddp_write_mask(handle, merge_config.mode,
> +                          &priv->cmdq_reg, priv->regs,
> +                          DISP_MERGE_CFG_12, 0x1f);
> +       mtk_ddp_write_mask(handle, 0x1,
> +                          &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_MERGE_CTRL, 0x1);

Why do you enable merge in config?

Regards,
Chun-Kuang.

> +}
> +
> +int mtk_merge_clk_enable(struct device *dev)
> +{
> +       int ret = 0;
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       ret = pm_runtime_get_sync(dev);
> +
> +       if (priv->clk) {
> +               ret = clk_prepare_enable(priv->clk);
> +               if (ret)
> +                       pr_err("merge clk prepare enable failed\n");
> +       }
> +
> +       if (priv->async_clk) {
> +               ret = clk_prepare_enable(priv->async_clk);
> +               if (ret)
> +                       pr_err("async clk prepare enable failed\n");
> +       }
> +
> +       return ret;
> +}
> +
> +void mtk_merge_clk_disable(struct device *dev)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       if (priv->async_clk)
> +               clk_disable_unprepare(priv->async_clk);
> +
> +       if (priv->clk)
> +               clk_disable_unprepare(priv->clk);
> +
> +       pm_runtime_put_sync(dev);
> +}
> +
> +static int mtk_disp_merge_bind(struct device *dev, struct device *master,
> +                              void *data)
> +{
> +       return 0;
> +}
> +
> +static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
> +                                 void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_merge_component_ops = {
> +       .bind   = mtk_disp_merge_bind,
> +       .unbind = mtk_disp_merge_unbind,
> +};
> +
> +static int mtk_disp_merge_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct resource *res;
> +       struct mtk_disp_merge *priv;
> +       enum mtk_ddp_comp_id comp_id;
> +       int ret;
> +
> +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_MERGE);
> +       if ((int)comp_id < 0) {
> +               dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
> +               return comp_id;
> +       }
> +
> +       priv->comp_id = comp_id;
> +       priv->need_golden_setting = true;
> +       priv->gs_comp_id = DDP_COMPONENT_MERGE5;
> +
> +       priv->clk = devm_clk_get(dev, NULL);
> +       if (IS_ERR(priv->clk)) {
> +               dev_err(dev, "failed to get merge clk\n");
> +               return PTR_ERR(priv->clk);
> +       }
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       priv->regs = devm_ioremap_resource(dev, res);
> +       if (IS_ERR(priv->regs)) {
> +               dev_err(dev, "failed to ioremap merge\n");
> +               return PTR_ERR(priv->regs);
> +       }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +       ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> +       if (ret)
> +               dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> +       priv->irq = platform_get_irq(pdev, 0);
> +       if (priv->irq < 0)
> +               priv->irq = 0;
> +
> +       priv->async_clk = of_clk_get(dev->of_node, 1);
> +       if (IS_ERR(priv->async_clk)) {
> +               ret = PTR_ERR(priv->async_clk);
> +               dev_dbg(dev, "No merge async clock: %d\n", ret);
> +               priv->async_clk = NULL;
> +       }
> +
> +       platform_set_drvdata(pdev, priv);
> +
> +       pm_runtime_enable(dev);
> +
> +       ret = component_add(dev, &mtk_disp_merge_component_ops);
> +       if (ret != 0) {
> +               dev_err(dev, "Failed to add component: %d\n", ret);
> +               pm_runtime_disable(dev);
> +       }
> +
> +       return ret;
> +}
> +
> +static int mtk_disp_merge_remove(struct platform_device *pdev)
> +{
> +       component_del(&pdev->dev, &mtk_disp_merge_component_ops);
> +
> +       pm_runtime_disable(&pdev->dev);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
> +       { .compatible = "mediatek,mt8195-disp-merge", },
> +       {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
> +
> +struct platform_driver mtk_disp_merge_driver = {
> +       .probe = mtk_disp_merge_probe,
> +       .remove = mtk_disp_merge_remove,
> +       .driver = {
> +               .name = "mediatek-disp-merge",
> +               .owner = THIS_MODULE,
> +               .of_match_table = mtk_disp_merge_driver_dt_match,
> +       },
> +};
> +
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> index cb9a36c48d4f..66d1cf03dfe8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> @@ -14,6 +14,20 @@
>  #define MTK_MAX_BPC    10
>  #define MTK_MIN_BPC    3
>
> +#define REG_FLD(width, shift) \
> +       ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
> +
> +#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
> +
> +#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
> +
> +#define REG_FLD_MASK(field) \
> +       ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
> +        << REG_FLD_SHIFT(field))
> +
> +#define REG_FLD_VAL(field, val) \
> +       (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
> +
>  void mtk_drm_crtc_commit(struct drm_crtc *crtc);
>  int mtk_drm_crtc_create(struct drm_device *drm_dev,
>                         const enum mtk_ddp_comp_id *path,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index d0b0f41dfe5a..fb5f260f5ae0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -341,6 +341,14 @@ static const struct mtk_ddp_comp_funcs ddp_dsc = {
>         .clk_disable = mtk_dsc_clk_disable,
>  };
>
> +static const struct mtk_ddp_comp_funcs ddp_merge = {
> +       .clk_enable = mtk_merge_clk_enable,
> +       .clk_disable = mtk_merge_clk_disable,
> +       .start = mtk_merge_start,
> +       .stop = mtk_merge_stop,
> +       .config = mtk_merge_config,
> +};
> +
>  static const struct mtk_ddp_comp_funcs ddp_ufoe = {
>         .clk_enable = mtk_ddp_clk_enable,
>         .clk_disable = mtk_ddp_clk_disable,
> @@ -365,6 +373,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
>         [MTK_DISP_OD] = "od",
>         [MTK_DISP_BLS] = "bls",
>         [MTK_DISP_DSC] = "dsc",
> +       [MTK_DISP_MERGE] = "merge",
>  };
>
>  struct mtk_ddp_comp_match {
> @@ -403,6 +412,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
>         [DDP_COMPONENT_DSC0]    = { MTK_DISP_DSC,       0, &ddp_dsc },
>         [DDP_COMPONENT_DSC1]    = { MTK_DISP_DSC,       1, &ddp_dsc },
>         [DDP_COMPONENT_DSC1_VIRTUAL0]   = { MTK_DISP_DSC,       -1, &ddp_dsc },
> +       [DDP_COMPONENT_MERGE0]  = { MTK_DISP_MERGE,     0, &ddp_merge },
> +       [DDP_COMPONENT_MERGE1]  = { MTK_DISP_MERGE,     1, &ddp_merge },
> +       [DDP_COMPONENT_MERGE2]  = { MTK_DISP_MERGE,     2, &ddp_merge },
> +       [DDP_COMPONENT_MERGE3]  = { MTK_DISP_MERGE,     3, &ddp_merge },
> +       [DDP_COMPONENT_MERGE4]  = { MTK_DISP_MERGE,     4, &ddp_merge },
> +       [DDP_COMPONENT_MERGE5]  = { MTK_DISP_MERGE,     5, &ddp_merge },
>         [DDP_COMPONENT_UFOE]    = { MTK_DISP_UFOE,      0, &ddp_ufoe },
>         [DDP_COMPONENT_WDMA0]   = { MTK_DISP_WDMA,      0, NULL },
>         [DDP_COMPONENT_WDMA1]   = { MTK_DISP_WDMA,      1, NULL },
> @@ -522,6 +537,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
>             type == MTK_DISP_COLOR ||
>             type == MTK_DISP_GAMMA ||
>             type == MTK_DISP_DSC ||
> +           type == MTK_DISP_MERGE ||
>             type == MTK_DPI ||
>             type == MTK_DSI ||
>             type == MTK_DISP_OVL ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 661fb620e266..0afd78c0bc92 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -35,6 +35,7 @@ enum mtk_ddp_comp_type {
>         MTK_DISP_OD,
>         MTK_DISP_BLS,
>         MTK_DISP_DSC,
> +       MTK_DISP_MERGE,
>         MTK_DDP_COMP_TYPE_MAX,
>  };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 7dfca63c1042..24599fc0a597 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -448,6 +448,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_DITHER },
>         { .compatible = "mediatek,mt8195-disp-dsc",
>           .data = (void *)MTK_DISP_DSC },
> +       { .compatible = "mediatek,mt8195-disp-merge",
> +         .data = (void *)MTK_DISP_MERGE },
>         { .compatible = "mediatek,mt8173-disp-ufoe",
>           .data = (void *)MTK_DISP_UFOE },
>         { .compatible = "mediatek,mt2701-dsi",
> @@ -566,6 +568,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
>                     comp_type == MTK_DISP_COLOR ||
>                     comp_type == MTK_DISP_GAMMA ||
>                     comp_type == MTK_DISP_DSC ||
> +                   comp_type == MTK_DISP_MERGE ||
>                     comp_type == MTK_DISP_OVL ||
>                     comp_type == MTK_DISP_OVL_2L ||
>                     comp_type == MTK_DISP_RDMA ||
> @@ -671,6 +674,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
>         &mtk_dpi_driver,
>         &mtk_drm_platform_driver,
>         &mtk_disp_dsc_driver,
> +       &mtk_disp_merge_driver,
>         &mtk_dsi_driver,
>  };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index 8b722330ef7d..c4d802a43531 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -52,6 +52,7 @@ extern struct platform_driver mtk_disp_gamma_driver;
>  extern struct platform_driver mtk_disp_ovl_driver;
>  extern struct platform_driver mtk_disp_rdma_driver;
>  extern struct platform_driver mtk_disp_dsc_driver;
> +extern struct platform_driver mtk_disp_merge_driver;
>  extern struct platform_driver mtk_dpi_driver;
>  extern struct platform_driver mtk_dsi_driver;
>
> --
> 2.18.0
>

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Re: [PATCH v2 9/9] drm/mediatek: add MERGE support for mt8195

[Jason-JH Lin]

Hi CK,

On Sun, 2021-07-11 at 07:42 +0800, Chun-Kuang Hu wrote:
>  Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
> > 
> > 1. Add MERGE module file.
> > 2. Add REG_FLD macro in mtk_dem_crtc header to support
> >    bitwise register settings.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/Makefile           |   1 +
> >  drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
> >  drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 525
> > ++++++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_drm_crtc.h     |  14 +
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  16 +
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
> >  8 files changed, 570 insertions(+)
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > 
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index a1b239135c8f..9044c5aabae1 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> >                   mtk_disp_ovl.o \
> >                   mtk_disp_rdma.o \
> >                   mtk_disp_dsc.o \
> > +                 mtk_disp_merge.o \
> >                   mtk_drm_crtc.o \
> >                   mtk_drm_ddp_comp.o \
> >                   mtk_drm_drv.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 128d9fdbaf9e..dfb078541430 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -97,4 +97,12 @@ void mtk_dsc_config(struct device *dev, unsigned
> > int width,
> >  void mtk_dsc_start(struct device *dev);
> >  void mtk_dsc_stop(struct device *dev);
> > 
> > +int mtk_merge_clk_enable(struct device *dev);
> > +void mtk_merge_clk_disable(struct device *dev);
> > +void mtk_merge_config(struct device *dev, unsigned int width,
> > +                     unsigned int height, unsigned int vrefresh,
> > +                     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > +void mtk_merge_start(struct device *dev);
> > +void mtk_merge_stop(struct device *dev);
> > +
> >  #endif
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > new file mode 100644
> > index 000000000000..b7d633ca2f71
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > @@ -0,0 +1,525 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_disp_drv.h"
> > +
> > +#define DISP_REG_MERGE_CTRL (0x000)
> > +#define FLD_MERGE_EN BIT(0)
> > +#define FLD_MERGE_RST BIT(4)
> > +#define FLD_MERGE_LR_SWAP BIT(8)
> > +#define FLD_MERGE_DCM_DIS BIT(12)
> > +
> > +#define DISP_REG_MERGE_WIDTH (0x004)
> > +#define FLD_IN_WIDHT_L GENMASK(15, 0)
> > +#define FLD_IN_WIDHT_R GENMASK(31, 16)
> > +
> > +#define DISP_REG_MERGE_HEIGHT (0x008)
> > +#define FLD_IN_HEIGHT GENMASK(15, 0)
> > +
> > +#define DISP_REG_MERGE_SHADOW_CRTL (0x00c)
> > +
> > +#define DISP_REG_MERGE_DGB0 (0x010)
> > +#define FLD_PIXEL_CNT GENMASK(15, 0)
> > +#define FLD_MERGE_STATE GENMASK(17, 16)
> > +
> > +#define DISP_REG_MERGE_DGB1 (0x014)
> > +#define FLD_LINE_CNT GENMASK(15, 0)
> > +
> > +#define DISP_REG_MERGE_CFG2_0 (0x160)
> > +
> > +#define DISP_REG_MERGE_CFG2_2 (0x168)
> > +
> > +#define DISP_MERGE_CFG_0               0x010
> > +#define DISP_MERGE_CFG_1               0x014
> > +#define DISP_MERGE_CFG_4               0x020
> > +#define DISP_MERGE_CFG_5               0x024
> > +#define DISP_MERGE_CFG_8               0x030
> > +#define DISP_MERGE_CFG_9               0x034
> > +#define DISP_MERGE_CFG_10      0x038
> > +#define DISP_MERGE_CFG_11      0x03c
> > +#define DISP_MERGE_CFG_12      0x040
> > +#define CFG_11_11_1PI_1PO_BYPASS       1
> > +#define CFG_11_11_2PI_2PO_BYPASS       2
> > +#define CFG_10_10_2PI_1PO_BYPASS       3
> > +#define CFG_10_10_2PI_2PO_BYPASS       4
> > +#define CFG_10_10_1PI_1PO_BUF_MODE     5
> > +#define CFG_10_10_1PI_2PO_BUF_MODE     6
> > +#define CFG_10_10_2PI_1PO_BUF_MODE     7
> > +#define CFG_10_10_2PI_2PO_BUF_MODE     8
> > +#define CFG_10_01_1PI_1PO_BUF_MODE     9
> > +#define CFG_10_01_2PI_1PO_BUF_MODE     10
> > +#define CFG_01_10_1PI_1PO_BUF_MODE     11
> > +#define CFG_01_10_1PI_2PO_BUF_MODE     12
> > +#define CFG_01_01_1PI_1PO_BUF_MODE     13
> > +#define CFG_10_11_1PI_1PO_SPLIT                14
> > +#define CFG_10_11_2PI_1PO_SPLIT                15
> > +#define CFG_01_11_1PI_1PO_SPLIT                16
> > +#define CFG_11_10_1PI_1PO_MERGE                17
> > +#define CFG_11_10_1PI_2PO_MERGE                18
> > +#define CFG_10_10_1PI_1PO_TO422                19
> > +#define CFG_10_10_1PI_2PO_TO444                20
> > +#define CFG_10_10_2PI_2PO_TO444                21
> > +#define DISP_MERGE_CFG_13      0x044
> 
> Useless, so remove.
> 
OK, I'll remove it.

> > +#define DISP_MERGE_CFG_14      0x048
> > +#define DISP_MERGE_CFG_15      0x04c
> > +#define DISP_MERGE_CFG_17      0x054
> > +#define DISP_MERGE_CFG_18      0x058
> > +#define DISP_MERGE_CFG_19      0x05c
> > +#define DISP_MERGE_CFG_20      0x060
> > +#define DISP_MERGE_CFG_21      0x064
> > +#define DISP_MERGE_CFG_22      0x068
> > +#define DISP_MERGE_CFG_23      0x06c
> > +#define DISP_MERGE_CFG_24      0x070
> > +#define DISP_MERGE_CFG_25      0x074
> > +#define DISP_MERGE_CFG_26      0x078
> > +#define DISP_MERGE_CFG_27      0x07c
> > +#define DISP_MERGE_CFG_28      0x080
> > +#define DISP_MERGE_CFG_29      0x084
> > +#define DISP_MERGE_CFG_36      0x0a0
> > +#define DISP_MERGE_CFG_36_FLD_ULTRA_EN \
> > +       REG_FLD(1, 0)
> > +#define DISP_MERGE_CFG_36_FLD_PREULTRA_EN \
> > +       REG_FLD(1, 4)
> > +#define DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN \
> > +       REG_FLD(1, 8)
> > +#define DISP_MERGE_CFG_36_VAL_ULTRA_EN(val) \
> > +       REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_ULTRA_EN, val)
> > +#define DISP_MERGE_CFG_36_VAL_PREULTRA_EN(val) \
> > +       REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_PREULTRA_EN, val)
> > +#define DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN(val) \
> > +       REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN, val)
> > +#define DISP_MERGE_CFG_37      0x0a4
> > +#define DISP_MERGE_CFG_37_FLD_BUFFER_MODE \
> > +       REG_FLD(2, 0)
> > +#define DISP_MERGE_CFG_37_VAL_BUFFER_MODE(val) \
> > +       REG_FLD_VAL(DISP_MERGE_CFG_37_FLD_BUFFER_MODE, val)
> > +#define DISP_MERGE_CFG_38      0x0a8
> > +#define DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA \
> > +       REG_FLD(1, 0)
> > +#define DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA \
> > +       REG_FLD(1, 4)
> > +#define DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH \
> > +       REG_FLD(16, 16)
> > +#define DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA(val) \
> > +       REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA, val)
> > +#define DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA(val) \
> > +       REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA,
> > val)
> > +#define DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH(val) \
> > +       REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH, val)
> > +#define DISP_MERGE_CFG_39      0x0ac
> > +#define DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA \
> > +       REG_FLD(1, 8)
> > +#define DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA \
> > +       REG_FLD(1, 12)
> > +#define DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH \
> > +       REG_FLD(16, 16)
> > +#define DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA(val) \
> > +       REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA, val)
> > +#define DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA(val) \
> > +       REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA,
> > val)
> > +#define DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH(val) \
> > +       REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH,
> > val)
> > +#define DISP_MERGE_CFG_40      0x0b0
> > +#define DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW \
> > +       REG_FLD(16, 0)
> > +#define DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH \
> > +       REG_FLD(16, 16)
> > +#define DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW(val) \
> > +       REG_FLD_VAL(DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW, (val))
> > +#define DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH(val) \
> > +       REG_FLD_VAL(DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH, val)
> > +#define DISP_MERGE_CFG_41      0x0b4
> > +#define DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW \
> > +       REG_FLD(16, 0)
> > +#define DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH \
> > +       REG_FLD(16, 16)
> > +#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW(val) \
> > +       REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW, val)
> > +#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(val) \
> > +       REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH, val)
> > +
> > +struct mtk_merge_config_struct {
> > +       unsigned short width_right;
> > +       unsigned short width_left;
> > +       unsigned int height;
> > +       unsigned int fmt;
> > +       unsigned int mode;
> > +       unsigned int swap;
> > +};
> > +
> > +struct mtk_disp_merge {
> > +       enum mtk_ddp_comp_id comp_id;
> > +       struct drm_crtc *crtc;
> > +       struct clk *clk;
> > +       struct clk *async_clk;
> > +       void __iomem *regs;
> > +       struct cmdq_client_reg          cmdq_reg;
> > +       int irq;
> > +       bool need_golden_setting;
> 
> need_golden_setting is always true, so remove this.
> 
OK, I'll remove it.

> > +       enum mtk_ddp_comp_id gs_comp_id;
> > +};
> > +
> > +void mtk_merge_start(struct device *dev)
> > +{
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       mtk_ddp_write(NULL, 0x1, &priv->cmdq_reg, priv->regs,
> > +                     DISP_REG_MERGE_CTRL);
> 
> One line.
> 
OK, I'll fix it.

> > +}
> > +
> > +void mtk_merge_stop(struct device *dev)
> > +{
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       mtk_ddp_write(NULL, 0x0, &priv->cmdq_reg, priv->regs,
> > +                     DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +static int mtk_merge_check_params(struct mtk_merge_config_struct
> > *merge_config)
> > +{
> > +       if (!merge_config->height ||
> > +           !merge_config->width_left || !merge_config-
> > >width_right) {
> > +               pr_err("%s:merge input width l(%u) w(%u) h(%u)\n",
> > +                      __func__, merge_config->width_left,
> > +                      merge_config->width_right, merge_config-
> > >height);
> > +               return -EINVAL;
> > +       }
> > +       pr_debug("%s:merge input width l(%u) r(%u) height(%u)\n",
> > +                __func__, merge_config->width_left,
> > +                merge_config->width_right, merge_config->height);
> > +       return 0;
> > +}
> > +
> > +static int mtk_merge_golden_setting(struct mtk_disp_merge *priv,
> > +                                   struct cmdq_pkt *handle)
> > +{
> > +       int ultra_en = 1;
> > +       int preultra_en = 1;
> > +       int halt_for_dvfs_en = 0;
> > +       int buffer_mode = 3;
> > +       int vde_block_ultra = 0;
> > +       int valid_th_block_ultra = 0;
> > +       int ultra_fifo_valid_th = 0;
> > +       int nvde_force_preultra = 0;
> > +       int nvalid_th_force_preultra = 0;
> > +       int preultra_fifo_valid_th = 0;
> > +       int ultra_th_low = 0xe10;
> > +       int ultra_th_high = 0x12c0;
> > +       int preultra_th_low = 0x12c0;
> > +       int preultra_th_high = 0x1518;
> 
> I do not like a 'golden setting' which means we have no knowledge to
> control these value for some special case.
> Could you explain the logic why we set these value?
> 
I'll change it to fifo setting and add the MERGE fifo description in
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
at the next version.

> > +
> > +       mtk_ddp_write_mask(handle,
> > +                          DISP_MERGE_CFG_36_VAL_ULTRA_EN
> > +                               (ultra_en) |
> > +                          DISP_MERGE_CFG_36_VAL_PREULTRA_EN
> > +                               (preultra_en) |
> > +                          DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN
> > +                               (halt_for_dvfs_en),
> > +                          &priv->cmdq_reg, priv->regs,
> > +                          DISP_MERGE_CFG_36,
> > +                          REG_FLD_MASK
> > +                               (DISP_MERGE_CFG_36_FLD_ULTRA_EN) |
> > +                          REG_FLD_MASK
> > +                               (DISP_MERGE_CFG_36_FLD_PREULTRA_EN)
> > |
> > +                          REG_FLD_MASK
> > +                               (DISP_MERGE_CFG_36_FLD_HALT_FOR_DVF
> > S_EN));
> > +
> > +       mtk_ddp_write_mask(handle,
> > +                          DISP_MERGE_CFG_37_VAL_BUFFER_MODE
> > +                               (buffer_mode),
> > +                          &priv->cmdq_reg, priv->regs,
> > +                          DISP_MERGE_CFG_37,
> > +                          REG_FLD_MASK
> > +                               (DISP_MERGE_CFG_37_FLD_BUFFER_MODE)
> > );
> > +
> > +       mtk_ddp_write_mask(handle,
> > +                          DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA
> > +                               (vde_block_ultra) |
> > +                          DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULT
> > RA
> > +                               (valid_th_block_ultra) |
> > +                          DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_T
> > H
> > +                               (ultra_fifo_valid_th),
> > +                          &priv->cmdq_reg, priv->regs,
> > +                          DISP_MERGE_CFG_38,
> > +                          REG_FLD_MASK
> > +                               (DISP_MERGE_CFG_38_FLD_VDE_BLOCK_UL
> > TRA) |
> > +                          REG_FLD_MASK
> > +                               (DISP_MERGE_CFG_38_FLD_VALID_TH_BLO
> > CK_ULTRA) |
> > +                          REG_FLD_MASK
> > +                               (DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_V
> > ALID_TH));
> > +
> > +       mtk_ddp_write_mask(handle,
> > +                          DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTR
> > A
> > +                               (nvde_force_preultra) |
> > +                          DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PR
> > EULTRA
> > +                               (nvalid_th_force_preultra) |
> > +                          DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALI
> > D_TH
> > +                               (preultra_fifo_valid_th),
> > +                          &priv->cmdq_reg, priv->regs,
> > +                          DISP_MERGE_CFG_39,
> > +                          REG_FLD_MASK
> > +                               (DISP_MERGE_CFG_39_FLD_NVDE_FORCE_P
> > REULTRA) |
> > +                          REG_FLD_MASK
> > +                               (DISP_MERGE_CFG_39_FLD_NVALID_TH_FO
> > RCE_PREULTRA) |
> > +                          REG_FLD_MASK
> > +                               (DISP_MERGE_CFG_39_FLD_PREULTRA_FIF
> > O_VALID_TH));
> > +
> > +       mtk_ddp_write_mask(handle,
> > +                          DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW
> > +                               (ultra_th_low) |
> > +                          DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH
> > +                               (ultra_th_high),
> > +                          &priv->cmdq_reg, priv->regs,
> > +                          DISP_MERGE_CFG_40,
> > +                          REG_FLD_MASK
> > +                               (DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW
> > ) |
> > +                          REG_FLD_MASK
> > +                               (DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIG
> > H));
> > +
> > +       mtk_ddp_write_mask(handle,
> > +                          DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW
> > +                               (preultra_th_low) |
> > +                          DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH
> > +                               (preultra_th_high),
> > +                          &priv->cmdq_reg, priv->regs,
> > +                          DISP_MERGE_CFG_41,
> > +                          REG_FLD_MASK
> > +                               (DISP_MERGE_CFG_41_FLD_PREULTRA_TH_
> > LOW) |
> > +                          REG_FLD_MASK
> > +                               (DISP_MERGE_CFG_41_FLD_PREULTRA_TH_
> > HIGH));
> > +
> > +       return 0;
> > +}
> > +
> > +void mtk_merge_config(struct device *dev, unsigned int w,
> > +                     unsigned int h, unsigned int vrefresh,
> > +                     unsigned int bpc, struct cmdq_pkt *handle)
> > +{
> > +       struct mtk_merge_config_struct merge_config;
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       /*golden setting*/
> > +       if (priv->need_golden_setting &&
> > +           priv->gs_comp_id == priv->comp_id)
> > +               mtk_merge_golden_setting(priv, handle);
> 
> Why only MERGE_5 set the fifo setting? I think all merge should set
> fifo setting.
> 
Only MERGE5 need to set the fifo setting and MERGE0~4 can't config the
fifo settings. I'll add the new property in binding document and
describe it.

> > +
> > +       switch (priv->comp_id) {
> > +       case DDP_COMPONENT_MERGE0:
> > +               merge_config.mode = CFG_10_10_1PI_2PO_BUF_MODE;
> 
> Please explain what the mode means.
> 
The mode setting here is to set the input and output pixel number per
times in buffer mode or bypass mode.
E.g.
CFG_10_10_1PI_2PO_BUF_MODE:
1 pixel in, 2pixel out per times in buffer mode.
CFG_10_10_2PI_2PO_BUF_MODE:
2 pixel in, 2pixel out per times in buffer mode.

> > +               merge_config.width_left = w;
> > +               merge_config.width_right = w;
> > +               merge_config.height = h;
> > +               merge_config.swap = 0;
> > +               break;
> > +       case DDP_COMPONENT_MERGE5:
> > +               merge_config.mode = CFG_10_10_2PI_2PO_BUF_MODE;
> > +               merge_config.width_left = w;
> > +               merge_config.width_right = w;
> > +               merge_config.height = h;
> > +               merge_config.swap = 0;
> > +               break;
> > +       default:
> > +               pr_err("No find component merge %d\n", priv-
> > >comp_id);
> > +               return;
> > +       }
> > +
> > +       mtk_merge_check_params(&merge_config);
> > +
> > +       switch (merge_config.mode) {
> > +       case CFG_10_10_1PI_2PO_BUF_MODE:
> > +       case CFG_10_10_2PI_2PO_BUF_MODE:
> 
> Remove 'switch' because these two cases are always true.
> 
OK, I'll remove it.

> > +               mtk_ddp_write_mask(handle,
> > +                                  (merge_config.height << 16 |
> > +                                  merge_config.width_left),
> > +                                  &priv->cmdq_reg, priv->regs,
> > +                                  DISP_MERGE_CFG_0, ~0);
> 
> mtk_ddp_write(handle, h << 16 | w, &priv->comdq_reg, priv->regs,
> DISP_MERGE_CFG_0);
> 
I'll fix it.

> > +
> > +               mtk_ddp_write_mask(handle,
> > +                                  (merge_config.height << 16 |
> > +                                  merge_config.width_left),
> > +                                  &priv->cmdq_reg, priv->regs,
> > +                                  DISP_MERGE_CFG_4, ~0);
> 
> mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
> DISP_MERGE_CFG_4);
> 
I'll fix it.

> > +
> > +               mtk_ddp_write_mask(handle,
> > +                                  (merge_config.height << 16 |
> > +                                  merge_config.width_left),
> > +                                  &priv->cmdq_reg, priv->regs,
> > +                                  DISP_MERGE_CFG_24, ~0);
> 
> mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
> DISP_MERGE_CFG_24);
> 
I'll fix it.

> > +
> > +               mtk_ddp_write_mask(handle,
> > +                                  (merge_config.height << 16 |
> > +                                  merge_config.width_left),
> > +                                  &priv->cmdq_reg, priv->regs,
> > +                                  DISP_MERGE_CFG_25, ~0);
> > +
> 
> mtk_ddp_write(handle, h << 16 | w, &priv->cmdq_reg, priv->regs,
> DISP_MERGE_CFG_25);
> 
I'll fix it.

> > +               mtk_ddp_write_mask(handle,
> > +                                  merge_config.swap,
> > +                                  &priv->cmdq_reg, priv->regs,
> > +                                  DISP_MERGE_CFG_10, 0x1f);
> 
> /* no swap */
> mtk_ddp_write_mask(handle, 0, &priv->cmdq_reg, priv->regs,
> DISP_MERGE_CFG_10, 0x1f);
> 
I'll fix it.
> > +       break;
> > +       default:
> > +       break;
> > +       }
> > +       mtk_ddp_write_mask(handle, merge_config.mode,
> > +                          &priv->cmdq_reg, priv->regs,
> > +                          DISP_MERGE_CFG_12, 0x1f);
> > +       mtk_ddp_write_mask(handle, 0x1,
> > +                          &priv->cmdq_reg, priv->regs,
> > +                          DISP_REG_MERGE_CTRL, 0x1);
> 
> Why do you enable merge in config?
> 
> Regards,
> Chun-Kuang.
> 
I'll remove it.

Regards,
Jason-JH.Lin

> > +}
> > +
> > +int mtk_merge_clk_enable(struct device *dev)
> > +{
> > +       int ret = 0;
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       ret = pm_runtime_get_sync(dev);
> > +
> > +       if (priv->clk) {
> > +               ret = clk_prepare_enable(priv->clk);
> > +               if (ret)
> > +                       pr_err("merge clk prepare enable
> > failed\n");
> > +       }
> > +
> > +       if (priv->async_clk) {
> > +               ret = clk_prepare_enable(priv->async_clk);
> > +               if (ret)
> > +                       pr_err("async clk prepare enable
> > failed\n");
> > +       }
> > +
> > +       return ret;
> > +}
> > +
> > +void mtk_merge_clk_disable(struct device *dev)
> > +{
> > +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > +       if (priv->async_clk)
> > +               clk_disable_unprepare(priv->async_clk);
> > +
> > +       if (priv->clk)
> > +               clk_disable_unprepare(priv->clk);
> > +
> > +       pm_runtime_put_sync(dev);
> > +}
> > +
> > +static int mtk_disp_merge_bind(struct device *dev, struct device
> > *master,
> > +                              void *data)
> > +{
> > +       return 0;
> > +}
> > +
> > +static void mtk_disp_merge_unbind(struct device *dev, struct
> > device *master,
> > +                                 void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_disp_merge_component_ops = {
> > +       .bind   = mtk_disp_merge_bind,
> > +       .unbind = mtk_disp_merge_unbind,
> > +};
> > +
> > +static int mtk_disp_merge_probe(struct platform_device *pdev)
> > +{
> > +       struct device *dev = &pdev->dev;
> > +       struct resource *res;
> > +       struct mtk_disp_merge *priv;
> > +       enum mtk_ddp_comp_id comp_id;
> > +       int ret;
> > +
> > +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > +       if (!priv)
> > +               return -ENOMEM;
> > +
> > +       comp_id = mtk_ddp_comp_get_id(dev->of_node,
> > MTK_DISP_MERGE);
> > +       if ((int)comp_id < 0) {
> > +               dev_err(dev, "Failed to identify by alias: %d\n",
> > comp_id);
> > +               return comp_id;
> > +       }
> > +
> > +       priv->comp_id = comp_id;
> > +       priv->need_golden_setting = true;
> > +       priv->gs_comp_id = DDP_COMPONENT_MERGE5;
> > +
> > +       priv->clk = devm_clk_get(dev, NULL);
> > +       if (IS_ERR(priv->clk)) {
> > +               dev_err(dev, "failed to get merge clk\n");
> > +               return PTR_ERR(priv->clk);
> > +       }
> > +
> > +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +       priv->regs = devm_ioremap_resource(dev, res);
> > +       if (IS_ERR(priv->regs)) {
> > +               dev_err(dev, "failed to ioremap merge\n");
> > +               return PTR_ERR(priv->regs);
> > +       }
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > +       ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> > +       if (ret)
> > +               dev_dbg(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > +
> > +       priv->irq = platform_get_irq(pdev, 0);
> > +       if (priv->irq < 0)
> > +               priv->irq = 0;
> > +
> > +       priv->async_clk = of_clk_get(dev->of_node, 1);
> > +       if (IS_ERR(priv->async_clk)) {
> > +               ret = PTR_ERR(priv->async_clk);
> > +               dev_dbg(dev, "No merge async clock: %d\n", ret);
> > +               priv->async_clk = NULL;
> > +       }
> > +
> > +       platform_set_drvdata(pdev, priv);
> > +
> > +       pm_runtime_enable(dev);
> > +
> > +       ret = component_add(dev, &mtk_disp_merge_component_ops);
> > +       if (ret != 0) {
> > +               dev_err(dev, "Failed to add component: %d\n", ret);
> > +               pm_runtime_disable(dev);
> > +       }
> > +
> > +       return ret;
> > +}
> > +
> > +static int mtk_disp_merge_remove(struct platform_device *pdev)
> > +{
> > +       component_del(&pdev->dev, &mtk_disp_merge_component_ops);
> > +
> > +       pm_runtime_disable(&pdev->dev);
> > +
> > +       return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_disp_merge_driver_dt_match[]
> > = {
> > +       { .compatible = "mediatek,mt8195-disp-merge", },
> > +       {},
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
> > +
> > +struct platform_driver mtk_disp_merge_driver = {
> > +       .probe = mtk_disp_merge_probe,
> > +       .remove = mtk_disp_merge_remove,
> > +       .driver = {
> > +               .name = "mediatek-disp-merge",
> > +               .owner = THIS_MODULE,
> > +               .of_match_table = mtk_disp_merge_driver_dt_match,
> > +       },
> > +};
> > +
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > index cb9a36c48d4f..66d1cf03dfe8 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > @@ -14,6 +14,20 @@
> >  #define MTK_MAX_BPC    10
> >  #define MTK_MIN_BPC    3
> > 
> > +#define REG_FLD(width, shift) \
> > +       ((unsigned int)((((width) & 0xff) << 16) | ((shift) &
> > 0xff)))
> > +
> > +#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) &
> > 0xff))
> > +
> > +#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
> > +
> > +#define REG_FLD_MASK(field) \
> > +       ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
> > +        << REG_FLD_SHIFT(field))
> > +
> > +#define REG_FLD_VAL(field, val) \
> > +       (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
> > +
> >  void mtk_drm_crtc_commit(struct drm_crtc *crtc);
> >  int mtk_drm_crtc_create(struct drm_device *drm_dev,
> >                         const enum mtk_ddp_comp_id *path,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index d0b0f41dfe5a..fb5f260f5ae0 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -341,6 +341,14 @@ static const struct mtk_ddp_comp_funcs ddp_dsc
> > = {
> >         .clk_disable = mtk_dsc_clk_disable,
> >  };
> > 
> > +static const struct mtk_ddp_comp_funcs ddp_merge = {
> > +       .clk_enable = mtk_merge_clk_enable,
> > +       .clk_disable = mtk_merge_clk_disable,
> > +       .start = mtk_merge_start,
> > +       .stop = mtk_merge_stop,
> > +       .config = mtk_merge_config,
> > +};
> > +
> >  static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> >         .clk_enable = mtk_ddp_clk_enable,
> >         .clk_disable = mtk_ddp_clk_disable,
> > @@ -365,6 +373,7 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> >         [MTK_DISP_OD] = "od",
> >         [MTK_DISP_BLS] = "bls",
> >         [MTK_DISP_DSC] = "dsc",
> > +       [MTK_DISP_MERGE] = "merge",
> >  };
> > 
> >  struct mtk_ddp_comp_match {
> > @@ -403,6 +412,12 @@ static const struct mtk_ddp_comp_match
> > mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> >         [DDP_COMPONENT_DSC0]    = { MTK_DISP_DSC,       0, &ddp_dsc
> > },
> >         [DDP_COMPONENT_DSC1]    = { MTK_DISP_DSC,       1, &ddp_dsc
> > },
> >         [DDP_COMPONENT_DSC1_VIRTUAL0]   = { MTK_DISP_DSC,       -1, 
> > &ddp_dsc },
> > +       [DDP_COMPONENT_MERGE0]  = { MTK_DISP_MERGE,     0,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE1]  = { MTK_DISP_MERGE,     1,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE2]  = { MTK_DISP_MERGE,     2,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE3]  = { MTK_DISP_MERGE,     3,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE4]  = { MTK_DISP_MERGE,     4,
> > &ddp_merge },
> > +       [DDP_COMPONENT_MERGE5]  = { MTK_DISP_MERGE,     5,
> > &ddp_merge },
> >         [DDP_COMPONENT_UFOE]    = { MTK_DISP_UFOE,      0,
> > &ddp_ufoe },
> >         [DDP_COMPONENT_WDMA0]   = { MTK_DISP_WDMA,      0, NULL },
> >         [DDP_COMPONENT_WDMA1]   = { MTK_DISP_WDMA,      1, NULL },
> > @@ -522,6 +537,7 @@ int mtk_ddp_comp_init(struct device_node *node,
> > struct mtk_ddp_comp *comp,
> >             type == MTK_DISP_COLOR ||
> >             type == MTK_DISP_GAMMA ||
> >             type == MTK_DISP_DSC ||
> > +           type == MTK_DISP_MERGE ||
> >             type == MTK_DPI ||
> >             type == MTK_DSI ||
> >             type == MTK_DISP_OVL ||
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 661fb620e266..0afd78c0bc92 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -35,6 +35,7 @@ enum mtk_ddp_comp_type {
> >         MTK_DISP_OD,
> >         MTK_DISP_BLS,
> >         MTK_DISP_DSC,
> > +       MTK_DISP_MERGE,
> >         MTK_DDP_COMP_TYPE_MAX,
> >  };
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 7dfca63c1042..24599fc0a597 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -448,6 +448,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> >           .data = (void *)MTK_DISP_DITHER },
> >         { .compatible = "mediatek,mt8195-disp-dsc",
> >           .data = (void *)MTK_DISP_DSC },
> > +       { .compatible = "mediatek,mt8195-disp-merge",
> > +         .data = (void *)MTK_DISP_MERGE },
> >         { .compatible = "mediatek,mt8173-disp-ufoe",
> >           .data = (void *)MTK_DISP_UFOE },
> >         { .compatible = "mediatek,mt2701-dsi",
> > @@ -566,6 +568,7 @@ static int mtk_drm_probe(struct platform_device
> > *pdev)
> >                     comp_type == MTK_DISP_COLOR ||
> >                     comp_type == MTK_DISP_GAMMA ||
> >                     comp_type == MTK_DISP_DSC ||
> > +                   comp_type == MTK_DISP_MERGE ||
> >                     comp_type == MTK_DISP_OVL ||
> >                     comp_type == MTK_DISP_OVL_2L ||
> >                     comp_type == MTK_DISP_RDMA ||
> > @@ -671,6 +674,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> >         &mtk_dpi_driver,
> >         &mtk_drm_platform_driver,
> >         &mtk_disp_dsc_driver,
> > +       &mtk_disp_merge_driver,
> >         &mtk_dsi_driver,
> >  };
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index 8b722330ef7d..c4d802a43531 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -52,6 +52,7 @@ extern struct platform_driver
> > mtk_disp_gamma_driver;
> >  extern struct platform_driver mtk_disp_ovl_driver;
> >  extern struct platform_driver mtk_disp_rdma_driver;
> >  extern struct platform_driver mtk_disp_dsc_driver;
> > +extern struct platform_driver mtk_disp_merge_driver;
> >  extern struct platform_driver mtk_dpi_driver;
> >  extern struct platform_driver mtk_dsi_driver;
> > 
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>
_______________________________________________
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Linux-mediatek@lists.infradead.org
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Re: [PATCH v2 9/9] drm/mediatek: add MERGE support for mt8195

[Fei Shao]

On Sat, Jul 10, 2021 at 7:38 PM jason-jh.lin <jason-jh.lin@mediatek.com> wrote:
>
> 1. Add MERGE module file.
> 2. Add REG_FLD macro in mtk_dem_crtc header to support
>    bitwise register settings.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/Makefile           |   1 +
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
>  drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 525 ++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.h     |  14 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  16 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
>  8 files changed, 570 insertions(+)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index a1b239135c8f..9044c5aabae1 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_ccorr.o \
>                   mtk_disp_ovl.o \
>                   mtk_disp_rdma.o \
>                   mtk_disp_dsc.o \
> +                 mtk_disp_merge.o \
>                   mtk_drm_crtc.o \
>                   mtk_drm_ddp_comp.o \
>                   mtk_drm_drv.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 128d9fdbaf9e..dfb078541430 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -97,4 +97,12 @@ void mtk_dsc_config(struct device *dev, unsigned int width,
>  void mtk_dsc_start(struct device *dev);
>  void mtk_dsc_stop(struct device *dev);
>
> +int mtk_merge_clk_enable(struct device *dev);
> +void mtk_merge_clk_disable(struct device *dev);
> +void mtk_merge_config(struct device *dev, unsigned int width,
> +                     unsigned int height, unsigned int vrefresh,
> +                     unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_start(struct device *dev);
> +void mtk_merge_stop(struct device *dev);
> +
>  #endif
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> new file mode 100644
> index 000000000000..b7d633ca2f71
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -0,0 +1,525 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_disp_drv.h"
> +
> +#define DISP_REG_MERGE_CTRL (0x000)
> +#define FLD_MERGE_EN BIT(0)
> +#define FLD_MERGE_RST BIT(4)
> +#define FLD_MERGE_LR_SWAP BIT(8)
> +#define FLD_MERGE_DCM_DIS BIT(12)
> +
> +#define DISP_REG_MERGE_WIDTH (0x004)
> +#define FLD_IN_WIDHT_L GENMASK(15, 0)
> +#define FLD_IN_WIDHT_R GENMASK(31, 16)
> +
> +#define DISP_REG_MERGE_HEIGHT (0x008)
> +#define FLD_IN_HEIGHT GENMASK(15, 0)
> +
> +#define DISP_REG_MERGE_SHADOW_CRTL (0x00c)
> +
> +#define DISP_REG_MERGE_DGB0 (0x010)
> +#define FLD_PIXEL_CNT GENMASK(15, 0)
> +#define FLD_MERGE_STATE GENMASK(17, 16)
> +
> +#define DISP_REG_MERGE_DGB1 (0x014)
> +#define FLD_LINE_CNT GENMASK(15, 0)
> +
> +#define DISP_REG_MERGE_CFG2_0 (0x160)
> +
> +#define DISP_REG_MERGE_CFG2_2 (0x168)
> +
> +#define DISP_MERGE_CFG_0               0x010
> +#define DISP_MERGE_CFG_1               0x014
> +#define DISP_MERGE_CFG_4               0x020
> +#define DISP_MERGE_CFG_5               0x024
> +#define DISP_MERGE_CFG_8               0x030
> +#define DISP_MERGE_CFG_9               0x034
> +#define DISP_MERGE_CFG_10      0x038
> +#define DISP_MERGE_CFG_11      0x03c
> +#define DISP_MERGE_CFG_12      0x040
> +#define CFG_11_11_1PI_1PO_BYPASS       1
> +#define CFG_11_11_2PI_2PO_BYPASS       2
> +#define CFG_10_10_2PI_1PO_BYPASS       3
> +#define CFG_10_10_2PI_2PO_BYPASS       4
> +#define CFG_10_10_1PI_1PO_BUF_MODE     5
> +#define CFG_10_10_1PI_2PO_BUF_MODE     6
> +#define CFG_10_10_2PI_1PO_BUF_MODE     7
> +#define CFG_10_10_2PI_2PO_BUF_MODE     8
> +#define CFG_10_01_1PI_1PO_BUF_MODE     9
> +#define CFG_10_01_2PI_1PO_BUF_MODE     10
> +#define CFG_01_10_1PI_1PO_BUF_MODE     11
> +#define CFG_01_10_1PI_2PO_BUF_MODE     12
> +#define CFG_01_01_1PI_1PO_BUF_MODE     13
> +#define CFG_10_11_1PI_1PO_SPLIT                14
> +#define CFG_10_11_2PI_1PO_SPLIT                15
> +#define CFG_01_11_1PI_1PO_SPLIT                16
> +#define CFG_11_10_1PI_1PO_MERGE                17
> +#define CFG_11_10_1PI_2PO_MERGE                18
> +#define CFG_10_10_1PI_1PO_TO422                19
> +#define CFG_10_10_1PI_2PO_TO444                20
> +#define CFG_10_10_2PI_2PO_TO444                21
> +#define DISP_MERGE_CFG_13      0x044
> +#define DISP_MERGE_CFG_14      0x048
> +#define DISP_MERGE_CFG_15      0x04c
> +#define DISP_MERGE_CFG_17      0x054
> +#define DISP_MERGE_CFG_18      0x058
> +#define DISP_MERGE_CFG_19      0x05c
> +#define DISP_MERGE_CFG_20      0x060
> +#define DISP_MERGE_CFG_21      0x064
> +#define DISP_MERGE_CFG_22      0x068
> +#define DISP_MERGE_CFG_23      0x06c
> +#define DISP_MERGE_CFG_24      0x070
> +#define DISP_MERGE_CFG_25      0x074
> +#define DISP_MERGE_CFG_26      0x078
> +#define DISP_MERGE_CFG_27      0x07c
> +#define DISP_MERGE_CFG_28      0x080
> +#define DISP_MERGE_CFG_29      0x084
> +#define DISP_MERGE_CFG_36      0x0a0
> +#define DISP_MERGE_CFG_36_FLD_ULTRA_EN \
> +       REG_FLD(1, 0)

If I understand correctly, all the REG_FLD encodings can be replaced
by BIT and GENMASK.
With those you can simply apply a mask to a value, which means the
getter macros can be removed as well.

>
> +#define DISP_MERGE_CFG_36_FLD_PREULTRA_EN \
> +       REG_FLD(1, 4)
> +#define DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN \
> +       REG_FLD(1, 8)
> +#define DISP_MERGE_CFG_36_VAL_ULTRA_EN(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_ULTRA_EN, val)
> +#define DISP_MERGE_CFG_36_VAL_PREULTRA_EN(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_PREULTRA_EN, val)
> +#define DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN, val)
> +#define DISP_MERGE_CFG_37      0x0a4
> +#define DISP_MERGE_CFG_37_FLD_BUFFER_MODE \
> +       REG_FLD(2, 0)
> +#define DISP_MERGE_CFG_37_VAL_BUFFER_MODE(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_37_FLD_BUFFER_MODE, val)
> +#define DISP_MERGE_CFG_38      0x0a8
> +#define DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA \
> +       REG_FLD(1, 0)
> +#define DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA \
> +       REG_FLD(1, 4)
> +#define DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH \
> +       REG_FLD(16, 16)
> +#define DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA, val)
> +#define DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA, val)
> +#define DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH, val)
> +#define DISP_MERGE_CFG_39      0x0ac
> +#define DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA \
> +       REG_FLD(1, 8)
> +#define DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA \
> +       REG_FLD(1, 12)
> +#define DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH \
> +       REG_FLD(16, 16)
> +#define DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA, val)
> +#define DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA, val)
> +#define DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH, val)
> +#define DISP_MERGE_CFG_40      0x0b0
> +#define DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW \
> +       REG_FLD(16, 0)
> +#define DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH \
> +       REG_FLD(16, 16)
> +#define DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW, (val))
> +#define DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH, val)
> +#define DISP_MERGE_CFG_41      0x0b4
> +#define DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW \
> +       REG_FLD(16, 0)
> +#define DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH \
> +       REG_FLD(16, 16)
> +#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW, val)
> +#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(val) \
> +       REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH, val)
> +
> +struct mtk_merge_config_struct {
> +       unsigned short width_right;
> +       unsigned short width_left;
> +       unsigned int height;
> +       unsigned int fmt;
> +       unsigned int mode;
> +       unsigned int swap;
> +};
> +
> +struct mtk_disp_merge {
> +       enum mtk_ddp_comp_id comp_id;
> +       struct drm_crtc *crtc;
> +       struct clk *clk;
> +       struct clk *async_clk;
> +       void __iomem *regs;
> +       struct cmdq_client_reg          cmdq_reg;
> +       int irq;
> +       bool need_golden_setting;
> +       enum mtk_ddp_comp_id gs_comp_id;
> +};
> +
> +void mtk_merge_start(struct device *dev)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       mtk_ddp_write(NULL, 0x1, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_MERGE_CTRL);
> +}
> +
> +void mtk_merge_stop(struct device *dev)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       mtk_ddp_write(NULL, 0x0, &priv->cmdq_reg, priv->regs,
> +                     DISP_REG_MERGE_CTRL);
> +}
> +
> +static int mtk_merge_check_params(struct mtk_merge_config_struct *merge_config)
> +{
> +       if (!merge_config->height ||
> +           !merge_config->width_left || !merge_config->width_right) {
> +               pr_err("%s:merge input width l(%u) w(%u) h(%u)\n",
> +                      __func__, merge_config->width_left,
> +                      merge_config->width_right, merge_config->height);
> +               return -EINVAL;
> +       }
> +       pr_debug("%s:merge input width l(%u) r(%u) height(%u)\n",
> +                __func__, merge_config->width_left,
> +                merge_config->width_right, merge_config->height);
> +       return 0;
> +}
> +
> +static int mtk_merge_golden_setting(struct mtk_disp_merge *priv,
> +                                   struct cmdq_pkt *handle)
> +{
> +       int ultra_en = 1;
> +       int preultra_en = 1;
> +       int halt_for_dvfs_en = 0;
> +       int buffer_mode = 3;
> +       int vde_block_ultra = 0;
> +       int valid_th_block_ultra = 0;
> +       int ultra_fifo_valid_th = 0;
> +       int nvde_force_preultra = 0;
> +       int nvalid_th_force_preultra = 0;
> +       int preultra_fifo_valid_th = 0;
> +       int ultra_th_low = 0xe10;
> +       int ultra_th_high = 0x12c0;
> +       int preultra_th_low = 0x12c0;
> +       int preultra_th_high = 0x1518;
> +
> +       mtk_ddp_write_mask(handle,
> +                          DISP_MERGE_CFG_36_VAL_ULTRA_EN
> +                               (ultra_en) |
> +                          DISP_MERGE_CFG_36_VAL_PREULTRA_EN
> +                               (preultra_en) |
> +                          DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN
> +                               (halt_for_dvfs_en),
> +                          &priv->cmdq_reg, priv->regs,
> +                          DISP_MERGE_CFG_36,
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_36_FLD_ULTRA_EN) |
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_36_FLD_PREULTRA_EN) |
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN));
> +
> +       mtk_ddp_write_mask(handle,
> +                          DISP_MERGE_CFG_37_VAL_BUFFER_MODE
> +                               (buffer_mode),
> +                          &priv->cmdq_reg, priv->regs,
> +                          DISP_MERGE_CFG_37,
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_37_FLD_BUFFER_MODE));
> +
> +       mtk_ddp_write_mask(handle,
> +                          DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA
> +                               (vde_block_ultra) |
> +                          DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA
> +                               (valid_th_block_ultra) |
> +                          DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH
> +                               (ultra_fifo_valid_th),
> +                          &priv->cmdq_reg, priv->regs,
> +                          DISP_MERGE_CFG_38,
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA) |
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA) |
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH));
> +
> +       mtk_ddp_write_mask(handle,
> +                          DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA
> +                               (nvde_force_preultra) |
> +                          DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA
> +                               (nvalid_th_force_preultra) |
> +                          DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH
> +                               (preultra_fifo_valid_th),
> +                          &priv->cmdq_reg, priv->regs,
> +                          DISP_MERGE_CFG_39,
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA) |
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA) |
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH));
> +
> +       mtk_ddp_write_mask(handle,
> +                          DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW
> +                               (ultra_th_low) |
> +                          DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH
> +                               (ultra_th_high),
> +                          &priv->cmdq_reg, priv->regs,
> +                          DISP_MERGE_CFG_40,
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW) |
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH));
> +
> +       mtk_ddp_write_mask(handle,
> +                          DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW
> +                               (preultra_th_low) |
> +                          DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH
> +                               (preultra_th_high),
> +                          &priv->cmdq_reg, priv->regs,
> +                          DISP_MERGE_CFG_41,
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW) |
> +                          REG_FLD_MASK
> +                               (DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH));
> +
> +       return 0;
> +}
> +
> +void mtk_merge_config(struct device *dev, unsigned int w,
> +                     unsigned int h, unsigned int vrefresh,
> +                     unsigned int bpc, struct cmdq_pkt *handle)
> +{
> +       struct mtk_merge_config_struct merge_config;
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       /*golden setting*/
> +       if (priv->need_golden_setting &&
> +           priv->gs_comp_id == priv->comp_id)
> +               mtk_merge_golden_setting(priv, handle);
> +
> +       switch (priv->comp_id) {
> +       case DDP_COMPONENT_MERGE0:
> +               merge_config.mode = CFG_10_10_1PI_2PO_BUF_MODE;
> +               merge_config.width_left = w;
> +               merge_config.width_right = w;
> +               merge_config.height = h;
> +               merge_config.swap = 0;
> +               break;
> +       case DDP_COMPONENT_MERGE5:
> +               merge_config.mode = CFG_10_10_2PI_2PO_BUF_MODE;
> +               merge_config.width_left = w;
> +               merge_config.width_right = w;
> +               merge_config.height = h;
> +               merge_config.swap = 0;
> +               break;
> +       default:
> +               pr_err("No find component merge %d\n", priv->comp_id);
> +               return;
> +       }
> +
> +       mtk_merge_check_params(&merge_config);
> +
> +       switch (merge_config.mode) {
> +       case CFG_10_10_1PI_2PO_BUF_MODE:
> +       case CFG_10_10_2PI_2PO_BUF_MODE:
> +               mtk_ddp_write_mask(handle,
> +                                  (merge_config.height << 16 |
> +                                  merge_config.width_left),
> +                                  &priv->cmdq_reg, priv->regs,
> +                                  DISP_MERGE_CFG_0, ~0);
> +
> +               mtk_ddp_write_mask(handle,
> +                                  (merge_config.height << 16 |
> +                                  merge_config.width_left),
> +                                  &priv->cmdq_reg, priv->regs,
> +                                  DISP_MERGE_CFG_4, ~0);
> +
> +               mtk_ddp_write_mask(handle,
> +                                  (merge_config.height << 16 |
> +                                  merge_config.width_left),
> +                                  &priv->cmdq_reg, priv->regs,
> +                                  DISP_MERGE_CFG_24, ~0);
> +
> +               mtk_ddp_write_mask(handle,
> +                                  (merge_config.height << 16 |
> +                                  merge_config.width_left),
> +                                  &priv->cmdq_reg, priv->regs,
> +                                  DISP_MERGE_CFG_25, ~0);
> +
> +               mtk_ddp_write_mask(handle,
> +                                  merge_config.swap,
> +                                  &priv->cmdq_reg, priv->regs,
> +                                  DISP_MERGE_CFG_10, 0x1f);
> +       break;
> +       default:
> +       break;
> +       }
> +       mtk_ddp_write_mask(handle, merge_config.mode,
> +                          &priv->cmdq_reg, priv->regs,
> +                          DISP_MERGE_CFG_12, 0x1f);
> +       mtk_ddp_write_mask(handle, 0x1,
> +                          &priv->cmdq_reg, priv->regs,
> +                          DISP_REG_MERGE_CTRL, 0x1);
> +}
> +
> +int mtk_merge_clk_enable(struct device *dev)
> +{
> +       int ret = 0;
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       ret = pm_runtime_get_sync(dev);
> +
> +       if (priv->clk) {
> +               ret = clk_prepare_enable(priv->clk);
> +               if (ret)
> +                       pr_err("merge clk prepare enable failed\n");
> +       }
> +
> +       if (priv->async_clk) {
> +               ret = clk_prepare_enable(priv->async_clk);
> +               if (ret)
> +                       pr_err("async clk prepare enable failed\n");
> +       }
> +
> +       return ret;
> +}
> +
> +void mtk_merge_clk_disable(struct device *dev)
> +{
> +       struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> +       if (priv->async_clk)
> +               clk_disable_unprepare(priv->async_clk);
> +
> +       if (priv->clk)
> +               clk_disable_unprepare(priv->clk);
> +
> +       pm_runtime_put_sync(dev);
> +}
> +
> +static int mtk_disp_merge_bind(struct device *dev, struct device *master,
> +                              void *data)
> +{
> +       return 0;
> +}
> +
> +static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
> +                                 void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_merge_component_ops = {
> +       .bind   = mtk_disp_merge_bind,
> +       .unbind = mtk_disp_merge_unbind,
> +};
> +
> +static int mtk_disp_merge_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct resource *res;
> +       struct mtk_disp_merge *priv;
> +       enum mtk_ddp_comp_id comp_id;
> +       int ret;
> +
> +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_MERGE);
> +       if ((int)comp_id < 0) {
> +               dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
> +               return comp_id;
> +       }
> +
> +       priv->comp_id = comp_id;
> +       priv->need_golden_setting = true;
> +       priv->gs_comp_id = DDP_COMPONENT_MERGE5;
> +
> +       priv->clk = devm_clk_get(dev, NULL);
> +       if (IS_ERR(priv->clk)) {
> +               dev_err(dev, "failed to get merge clk\n");
> +               return PTR_ERR(priv->clk);
> +       }
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +       priv->regs = devm_ioremap_resource(dev, res);
> +       if (IS_ERR(priv->regs)) {
> +               dev_err(dev, "failed to ioremap merge\n");
> +               return PTR_ERR(priv->regs);
> +       }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> +       ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> +       if (ret)
> +               dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> +       priv->irq = platform_get_irq(pdev, 0);
> +       if (priv->irq < 0)
> +               priv->irq = 0;
> +
> +       priv->async_clk = of_clk_get(dev->of_node, 1);
> +       if (IS_ERR(priv->async_clk)) {
> +               ret = PTR_ERR(priv->async_clk);
> +               dev_dbg(dev, "No merge async clock: %d\n", ret);
> +               priv->async_clk = NULL;
> +       }
> +
> +       platform_set_drvdata(pdev, priv);
> +
> +       pm_runtime_enable(dev);
> +
> +       ret = component_add(dev, &mtk_disp_merge_component_ops);
> +       if (ret != 0) {
> +               dev_err(dev, "Failed to add component: %d\n", ret);
> +               pm_runtime_disable(dev);
> +       }
> +
> +       return ret;
> +}
> +
> +static int mtk_disp_merge_remove(struct platform_device *pdev)
> +{
> +       component_del(&pdev->dev, &mtk_disp_merge_component_ops);
> +
> +       pm_runtime_disable(&pdev->dev);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
> +       { .compatible = "mediatek,mt8195-disp-merge", },
> +       {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
> +
> +struct platform_driver mtk_disp_merge_driver = {
> +       .probe = mtk_disp_merge_probe,
> +       .remove = mtk_disp_merge_remove,
> +       .driver = {
> +               .name = "mediatek-disp-merge",
> +               .owner = THIS_MODULE,
> +               .of_match_table = mtk_disp_merge_driver_dt_match,
> +       },
> +};
> +
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> index cb9a36c48d4f..66d1cf03dfe8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> @@ -14,6 +14,20 @@
>  #define MTK_MAX_BPC    10
>  #define MTK_MIN_BPC    3
>
> +#define REG_FLD(width, shift) \
> +       ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
> +
> +#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
> +
> +#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
> +
> +#define REG_FLD_MASK(field) \
> +       ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
> +        << REG_FLD_SHIFT(field))
> +
> +#define REG_FLD_VAL(field, val) \
> +       (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
> +
>  void mtk_drm_crtc_commit(struct drm_crtc *crtc);
>  int mtk_drm_crtc_create(struct drm_device *drm_dev,
>                         const enum mtk_ddp_comp_id *path,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index d0b0f41dfe5a..fb5f260f5ae0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -341,6 +341,14 @@ static const struct mtk_ddp_comp_funcs ddp_dsc = {
>         .clk_disable = mtk_dsc_clk_disable,
>  };
>
> +static const struct mtk_ddp_comp_funcs ddp_merge = {
> +       .clk_enable = mtk_merge_clk_enable,
> +       .clk_disable = mtk_merge_clk_disable,
> +       .start = mtk_merge_start,
> +       .stop = mtk_merge_stop,
> +       .config = mtk_merge_config,
> +};
> +
>  static const struct mtk_ddp_comp_funcs ddp_ufoe = {
>         .clk_enable = mtk_ddp_clk_enable,
>         .clk_disable = mtk_ddp_clk_disable,
> @@ -365,6 +373,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
>         [MTK_DISP_OD] = "od",
>         [MTK_DISP_BLS] = "bls",
>         [MTK_DISP_DSC] = "dsc",
> +       [MTK_DISP_MERGE] = "merge",
>  };
>
>  struct mtk_ddp_comp_match {
> @@ -403,6 +412,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
>         [DDP_COMPONENT_DSC0]    = { MTK_DISP_DSC,       0, &ddp_dsc },
>         [DDP_COMPONENT_DSC1]    = { MTK_DISP_DSC,       1, &ddp_dsc },
>         [DDP_COMPONENT_DSC1_VIRTUAL0]   = { MTK_DISP_DSC,       -1, &ddp_dsc },
> +       [DDP_COMPONENT_MERGE0]  = { MTK_DISP_MERGE,     0, &ddp_merge },
> +       [DDP_COMPONENT_MERGE1]  = { MTK_DISP_MERGE,     1, &ddp_merge },
> +       [DDP_COMPONENT_MERGE2]  = { MTK_DISP_MERGE,     2, &ddp_merge },
> +       [DDP_COMPONENT_MERGE3]  = { MTK_DISP_MERGE,     3, &ddp_merge },
> +       [DDP_COMPONENT_MERGE4]  = { MTK_DISP_MERGE,     4, &ddp_merge },
> +       [DDP_COMPONENT_MERGE5]  = { MTK_DISP_MERGE,     5, &ddp_merge },
>         [DDP_COMPONENT_UFOE]    = { MTK_DISP_UFOE,      0, &ddp_ufoe },
>         [DDP_COMPONENT_WDMA0]   = { MTK_DISP_WDMA,      0, NULL },
>         [DDP_COMPONENT_WDMA1]   = { MTK_DISP_WDMA,      1, NULL },
> @@ -522,6 +537,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
>             type == MTK_DISP_COLOR ||
>             type == MTK_DISP_GAMMA ||
>             type == MTK_DISP_DSC ||
> +           type == MTK_DISP_MERGE ||
>             type == MTK_DPI ||
>             type == MTK_DSI ||
>             type == MTK_DISP_OVL ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 661fb620e266..0afd78c0bc92 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -35,6 +35,7 @@ enum mtk_ddp_comp_type {
>         MTK_DISP_OD,
>         MTK_DISP_BLS,
>         MTK_DISP_DSC,
> +       MTK_DISP_MERGE,
>         MTK_DDP_COMP_TYPE_MAX,
>  };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 7dfca63c1042..24599fc0a597 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -448,6 +448,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DISP_DITHER },
>         { .compatible = "mediatek,mt8195-disp-dsc",
>           .data = (void *)MTK_DISP_DSC },
> +       { .compatible = "mediatek,mt8195-disp-merge",
> +         .data = (void *)MTK_DISP_MERGE },
>         { .compatible = "mediatek,mt8173-disp-ufoe",
>           .data = (void *)MTK_DISP_UFOE },
>         { .compatible = "mediatek,mt2701-dsi",
> @@ -566,6 +568,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
>                     comp_type == MTK_DISP_COLOR ||
>                     comp_type == MTK_DISP_GAMMA ||
>                     comp_type == MTK_DISP_DSC ||
> +                   comp_type == MTK_DISP_MERGE ||
>                     comp_type == MTK_DISP_OVL ||
>                     comp_type == MTK_DISP_OVL_2L ||
>                     comp_type == MTK_DISP_RDMA ||
> @@ -671,6 +674,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
>         &mtk_dpi_driver,
>         &mtk_drm_platform_driver,
>         &mtk_disp_dsc_driver,
> +       &mtk_disp_merge_driver,
>         &mtk_dsi_driver,
>  };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index 8b722330ef7d..c4d802a43531 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -52,6 +52,7 @@ extern struct platform_driver mtk_disp_gamma_driver;
>  extern struct platform_driver mtk_disp_ovl_driver;
>  extern struct platform_driver mtk_disp_rdma_driver;
>  extern struct platform_driver mtk_disp_dsc_driver;
> +extern struct platform_driver mtk_disp_merge_driver;
>  extern struct platform_driver mtk_dpi_driver;
>  extern struct platform_driver mtk_dsi_driver;
>
> --
> 2.18.0

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Re: [PATCH v2 0/9] Add MediaTek SoC DRM (vdosys0) support for mt8195

[Chun-Kuang Hu]

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
>
> The hardware path of vdosys0 with eDP panel output need to go through
> by several modules, such as, OVL, RDMA, COLOR, CCORR, AAL, GAMMA,
> DITHER, DSC and MERGE.

You should add the difference in each version. [1] is an example for this.

[1] https://patchwork.kernel.org/project/linux-mediatek/cover/20210709022324.1607884-1-eizan@chromium.org/

Regards,
Chun-Kuang.

>
> Add DRM and these modules support by the patches below:
>
> jason-jh.lin (9):
>   dt-bindings: mediatek: add definition for mt8195 display
>   dt-bindings: mediatek: add DSC definition for mt8195
>   dt-bindings: arm: mediatek: add definition for mt8195 mmsys
>   arm64: dts: mt8195: add display node for vdosys0
>   soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
>   soc: mediatek: add mtk-mutex support for mt8195 vdosys0
>   drm/mediatek: add mediatek-drm of vdosys0 support for MT8195
>   drm/mediatek: add DSC support for MT8195
>   drm/mediatek: add MERGE support for MT8195
>
>  .../bindings/arm/mediatek/mediatek,mmsys.txt  |  15 +
>  .../display/mediatek/mediatek,disp.txt        |   9 +-
>  .../display/mediatek/mediatek,dsc.yaml        |  57 ++
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi      | 111 ++++
>  drivers/gpu/drm/mediatek/Makefile             |   2 +
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h       |  16 +
>  drivers/gpu/drm/mediatek/mtk_disp_dsc.c       | 205 +++++++
>  drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 525 ++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.h       |  14 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  29 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  32 ++
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   2 +
>  drivers/soc/mediatek/mt8195-mmsys.h           | 191 +++++++
>  drivers/soc/mediatek/mtk-mmsys.c              |  11 +
>  drivers/soc/mediatek/mtk-mutex.c              | 107 +++-
>  include/linux/soc/mediatek/mtk-mmsys.h        |  10 +
>  18 files changed, 1337 insertions(+), 7 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_dsc.c
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
>  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
> --
> 2.18.0
>

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Re: [PATCH v2 0/9] Add MediaTek SoC DRM (vdosys0) support for mt8195

[Jason-JH Lin]

On Sun, 2021-07-11 at 09:24 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
> 
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月10日 週六 下午7:38寫道：
> > 
> > The hardware path of vdosys0 with eDP panel output need to go
> > through
> > by several modules, such as, OVL, RDMA, COLOR, CCORR, AAL, GAMMA,
> > DITHER, DSC and MERGE.
> 
> You should add the difference in each version. [1] is an example for
> this.
> 
> [1] 
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/cover/20210709022324.1607884-1-eizan@chromium.org/__;!!CTRNKA9wMg0ARbw!1EwjwrNBixHVZwmgU4wIRyVUYiL40xPc64oURf6mVeiJ5j__sO-kMNLyaLBfRc53u9qX$
>  
> 
> Regards,
> Chun-Kuang.
> 
Hi CK,

I'll add this at the next version.

Regards,
Jason-JH.Lin
> > 
> > Add DRM and these modules support by the patches below:
> > 
> > jason-jh.lin (9):
> >   dt-bindings: mediatek: add definition for mt8195 display
> >   dt-bindings: mediatek: add DSC definition for mt8195
> >   dt-bindings: arm: mediatek: add definition for mt8195 mmsys
> >   arm64: dts: mt8195: add display node for vdosys0
> >   soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
> >   soc: mediatek: add mtk-mutex support for mt8195 vdosys0
> >   drm/mediatek: add mediatek-drm of vdosys0 support for MT8195
> >   drm/mediatek: add DSC support for MT8195
> >   drm/mediatek: add MERGE support for MT8195
> > 
> >  .../bindings/arm/mediatek/mediatek,mmsys.txt  |  15 +
> >  .../display/mediatek/mediatek,disp.txt        |   9 +-
> >  .../display/mediatek/mediatek,dsc.yaml        |  57 ++
> >  arch/arm64/boot/dts/mediatek/mt8195.dtsi      | 111 ++++
> >  drivers/gpu/drm/mediatek/Makefile             |   2 +
> >  drivers/gpu/drm/mediatek/mtk_disp_drv.h       |  16 +
> >  drivers/gpu/drm/mediatek/mtk_disp_dsc.c       | 205 +++++++
> >  drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 525
> > ++++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
> >  drivers/gpu/drm/mediatek/mtk_drm_crtc.h       |  14 +
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  29 +
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  32 ++
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   2 +
> >  drivers/soc/mediatek/mt8195-mmsys.h           | 191 +++++++
> >  drivers/soc/mediatek/mtk-mmsys.c              |  11 +
> >  drivers/soc/mediatek/mtk-mutex.c              | 107 +++-
> >  include/linux/soc/mediatek/mtk-mmsys.h        |  10 +
> >  18 files changed, 1337 insertions(+), 7 deletions(-)
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yam
> > l
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> >  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > 
> > --
> > 2.18.0
> > 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>
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