* [PATCH v4 1/6] arm64: dts: mt8195: add display node for vdosys0
2021-07-23 9:02 [PATCH v4 0/6] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
@ 2021-07-23 9:02 ` jason-jh.lin
2021-07-23 9:02 ` [PATCH v4 2/6] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: jason-jh.lin @ 2021-07-23 9:02 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, fshao
Cc: David Airlie, Daniel Vetter, Enric Balletbo i Serra, hsinyi,
jason-jh . lin, Yongqiang Niu, nancy.lin, singo.chang,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
dri-devel
Add display node for vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is based on [1][2][3][4]
[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2]arm64: dts: mt8195: add IOMMU and smi nodes
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3]arm64: dts: mt8195: add gce node
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210705053429.4380-4-jason-jh.lin@mediatek.com/
[4]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 111 +++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 04d3e95175fa..aa2a7849b822 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1155,9 +1155,120 @@
#clock-cells = <1>;
};
+ ovl0: disp_ovl@1c000000 {
+ compatible = "mediatek,mt8195-disp-ovl",
+ "mediatek,mt8183-disp-ovl";
+ reg = <0 0x1c000000 0 0x1000>;
+ interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x0000 0x1000>;
+ };
+
+ rdma0: disp_rdma@1c002000 {
+ compatible = "mediatek,mt8195-disp-rdma";
+ reg = <0 0x1c002000 0 0x1000>;
+ interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x2000 0x1000>;
+ };
+
+ color0: disp_color@1c003000 {
+ compatible = "mediatek,mt8195-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x1c003000 0 0x1000>;
+ interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x3000 0x1000>;
+ };
+
+ ccorr0: disp_ccorr@1c004000 {
+ compatible = "mediatek,mt8195-disp-ccorr",
+ "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x1c004000 0 0x1000>;
+ interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x4000 0x1000>;
+ };
+
+ aal0: disp_aal@1c005000 {
+ compatible = "mediatek,mt8195-disp-aal",
+ "mediatek,mt8173-disp-aal";
+ reg = <0 0x1c005000 0 0x1000>;
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x5000 0x1000>;
+ };
+
+ gamma0: disp_gamma@1c006000 {
+ compatible = "mediatek,mt8195-disp-gamma",
+ "mediatek,mt8173-disp-gamma";
+ reg = <0 0x1c006000 0 0x1000>;
+ interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x6000 0x1000>;
+ };
+
+ dither0: disp_dither@1c007000 {
+ compatible = "mediatek,mt8195-disp-dither",
+ "mediatek,mt8183-disp-dither";
+ reg = <0 0x1c007000 0 0x1000>;
+ interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x7000 0x1000>;
+ };
+
+ dsc0: disp_dsc_wrap@1c009000 {
+ compatible = "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>;
+ interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+ };
+
+ merge0: disp_vpp_merge0@1c014000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c014000 0 0x1000>;
+ interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c01XXXX 0x4000 0x1000>;
+ };
+
+ mutex: disp_mutex0@1c016000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c016000 0 0x1000>;
+ reg-names = "vdo0_mutex";
+ interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+ clock-names = "vdo0_mutex";
+ mediatek,gce-events =
+ <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+ };
+
vdosys0: syscon@1c01a000 {
compatible = "mediatek,mt8195-vdosys0", "syscon";
reg = <0 0x1c01a000 0 0x1000>;
+ mboxes = <&gce1 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>;
};
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v4 2/6] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2021-07-23 9:02 [PATCH v4 0/6] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
2021-07-23 9:02 ` [PATCH v4 1/6] arm64: dts: mt8195: add display node for vdosys0 jason-jh.lin
@ 2021-07-23 9:02 ` jason-jh.lin
2021-07-23 10:09 ` Enric Balletbo Serra
2021-07-23 9:02 ` [PATCH v4 3/6] soc: mediatek: add mtk-mutex " jason-jh.lin
` (3 subsequent siblings)
5 siblings, 1 reply; 8+ messages in thread
From: jason-jh.lin @ 2021-07-23 9:02 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, fshao
Cc: David Airlie, Daniel Vetter, Enric Balletbo i Serra, hsinyi,
jason-jh . lin, Yongqiang Niu, nancy.lin, singo.chang,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
dri-devel
Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/soc/mediatek/mt8195-mmsys.h | 191 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 11 ++
include/linux/soc/mediatek/mtk-mmsys.h | 9 ++
3 files changed, 211 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..73e9e8286d50
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN 0xf14
+#define MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
+#define MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
+#define MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
+#define MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
+#define MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
+#define MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
+
+#define MT8195_VDO0_SEL_IN 0xf34
+#define SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
+#define SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
+#define SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
+#define SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
+#define SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
+#define SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
+#define SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
+#define SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
+#define SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
+#define SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
+#define SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 12)
+#define SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
+#define SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
+#define SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
+#define SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
+#define SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
+#define SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
+#define SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
+#define SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
+#define SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
+#define SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
+#define SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
+#define SEL_IN_DISP_WDMA0_FROM_VPP_MERGE (1 << 22)
+
+#define MT8195_VDO0_SEL_OUT 0xf38
+#define SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
+#define SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
+#define SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
+#define SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
+#define SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
+#define SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
+#define SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
+#define SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
+#define SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
+#define SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
+#define SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
+#define SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
+#define SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
+#define SOUT_VPP_MERGE_TO_DISP_WDMA0 (1 << 11)
+#define SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
+#define SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
+#define SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
+#define SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
+#define SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
+#define SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
+#define SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+
+#define MT8195_VDO1_VPP3_ASYNC_SOUT 0xf54
+#define SOUT_TO_VPP_MERGE0_P0_SEL (0 << 0)
+#define SOUT_TO_VPP_MERGE0_P1_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
+#define SOUT_TO_HDR_VDO_FE0 (0 << 0)
+
+#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
+#define SOUT_TO_HDR_VDO_FE1 (0 << 0)
+
+#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
+#define SOUT_TO_HDR_GFX_FE0 (0 << 0)
+
+#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
+#define SOUT_TO_HDR_GFX_FE1 (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
+#define MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
+#define MIXER_IN2_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
+#define MIXER_IN3_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
+#define MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
+#define MIXER_SOUT_TO_HDR_VDO_BE0 (0 << 0)
+
+#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
+#define MERGE4_SOUT_TO_VDOSYS0 (0 << 0)
+#define MERGE4_SOUT_TO_DPI0_SEL (1 << 0)
+#define MERGE4_SOUT_TO_DPI1_SEL (2 << 0)
+#define MERGE4_SOUT_TO_DP_INTF0_SEL (3 << 0)
+
+#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
+#define VPP_MERGE0_P0_SEL_IN_FROM_SVPP2 (0 << 0)
+#define VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 (1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
+#define VPP_MERGE0_P1_SEL_IN_FROM_SVPP3 (0 << 0)
+#define VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 (1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
+#define VPP_MERGE1_P0_SEL_IN_FROM_VPP3_ASYNC_SOUT (0 << 0)
+#define VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
+#define MIXER_IN1_SEL_IN_FROM_HDR_VDO_FE0 (0 << 0)
+#define MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
+#define MIXER_IN2_SEL_IN_FROM_HDR_VDO_FE1 (0 << 0)
+#define MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
+#define MIXER_IN3_SEL_IN_FROM_HDR_GFX_FE0 (0 << 0)
+#define MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
+#define MIXER_IN4_SEL_IN_FROM_HDR_GFX_FE1 (0 << 0)
+#define MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
+#define MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN1_SOUT (1 << 0)
+#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN2_SOUT (2 << 0)
+#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN3_SOUTR (3 << 0)
+#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN4_SOUTR (4 << 0)
+
+#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
+#define MERGE4_ASYNC_SEL_IN_FROM_HDR_VDO_BE0 (0 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT (1 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MERGE0_ASYNC_SOUT (2 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MERGE1_ASYNC_SOUT (3 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MERGE2_ASYNC_SOUT (4 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MERGE3_ASYNC_SOUT (5 << 0)
+
+#define MT8195_VDO1_DISP_DPI0_SEL_IN 0xf0c
+#define DISP_DPI0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+#define DISP_DPI0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
+#define DISP_DPI0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
+
+#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
+#define DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+#define DISP_DPI1_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
+#define DISP_DPI1_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
+
+#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
+#define DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
+#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+ {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL0_TO_DISP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+ MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL1_TO_DISP_RDMA1
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_IN, SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DISP_DITHER0
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_OUT, SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_OUT, DDP_COMPONENT_DSI0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_DSI0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+ }
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 080660ef11bf..1fb241750897 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -13,6 +13,7 @@
#include "mtk-mmsys.h"
#include "mt8167-mmsys.h"
#include "mt8183-mmsys.h"
+#include "mt8195-mmsys.h"
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
@@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .clk_driver = "clk-mt8195-vdo0",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
@@ -157,6 +164,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6133da..01bedfb08094 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -39,6 +39,15 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_UFOE,
DDP_COMPONENT_WDMA0,
DDP_COMPONENT_WDMA1,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_MERGE1,
+ DDP_COMPONENT_MERGE2,
+ DDP_COMPONENT_MERGE3,
+ DDP_COMPONENT_MERGE4,
+ DDP_COMPONENT_MERGE5,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_DSC1,
+ DDP_COMPONENT_DP_INTF0,
DDP_COMPONENT_ID_MAX,
};
--
2.18.0
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v4 2/6] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2021-07-23 9:02 ` [PATCH v4 2/6] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
@ 2021-07-23 10:09 ` Enric Balletbo Serra
0 siblings, 0 replies; 8+ messages in thread
From: Enric Balletbo Serra @ 2021-07-23 10:09 UTC (permalink / raw)
To: jason-jh.lin
Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
fshao, devicetree, David Airlie, singo.chang, linux-kernel,
dri-devel, nancy.lin, moderated list:ARM/Mediatek SoC support,
Yongqiang Niu, Hsin-Yi Wang, Enric Balletbo i Serra, Linux ARM
Hi Jason,
Thank you for your patch.
Missatge de jason-jh.lin <jason-jh.lin@mediatek.com> del dia dv., 23
de jul. 2021 a les 11:02:
>
> Add mt8195 vdosys0 clock driver name and routing table to
> the driver data of mtk-mmsys.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> This patch is base on [1]
>
> [1]add mt8195 SoC DRM binding
> - https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 191 +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 11 ++
> include/linux/soc/mediatek/mtk-mmsys.h | 9 ++
> 3 files changed, 211 insertions(+)
> create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> new file mode 100644
> index 000000000000..73e9e8286d50
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -0,0 +1,191 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> +
> +#define MT8195_VDO0_OVL_MOUT_EN 0xf14
> +#define MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
This define and the others should use the MT8195_ prefix, as these are
MT8195 afaik
> +#define MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
> +#define MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
> +#define MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
> +#define MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
> +#define MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
> +
> +#define MT8195_VDO0_SEL_IN 0xf34
> +#define SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
> +#define SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
> +#define SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
> +#define SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
> +#define SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
> +#define SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
> +#define SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
> +#define SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
> +#define SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
> +#define SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
> +#define SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 12)
> +#define SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
> +#define SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
> +#define SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
> +#define SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
> +#define SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
> +#define SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
> +#define SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
> +#define SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
> +#define SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
> +#define SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
> +#define SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
> +#define SEL_IN_DISP_WDMA0_FROM_VPP_MERGE (1 << 22)
> +
> +#define MT8195_VDO0_SEL_OUT 0xf38
> +#define SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
> +#define SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
> +#define SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
> +#define SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
> +#define SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
> +#define SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
> +#define SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
> +#define SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
> +#define SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
> +#define SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
> +#define SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
> +#define SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
> +#define SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
> +#define SOUT_VPP_MERGE_TO_DISP_WDMA0 (1 << 11)
> +#define SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
> +#define SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
> +#define SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
> +#define SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
> +#define SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
> +#define SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
> +#define SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
> +
> +#define MT8195_VDO1_VPP3_ASYNC_SOUT 0xf54
> +#define SOUT_TO_VPP_MERGE0_P0_SEL (0 << 0)
> +#define SOUT_TO_VPP_MERGE0_P1_SEL (1 << 0)
> +
> +#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
> +#define SOUT_TO_HDR_VDO_FE0 (0 << 0)
> +
> +#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
> +#define SOUT_TO_HDR_VDO_FE1 (0 << 0)
> +
> +#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
> +#define SOUT_TO_HDR_GFX_FE0 (0 << 0)
> +
> +#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
> +#define SOUT_TO_HDR_GFX_FE1 (0 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
> +#define MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
> +#define MIXER_IN2_SOUT_TO_DISP_MIXER (0 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
> +#define MIXER_IN3_SOUT_TO_DISP_MIXER (0 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
> +#define MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
> +
> +#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
> +#define MIXER_SOUT_TO_HDR_VDO_BE0 (0 << 0)
> +
> +#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
Please order the file by register value. i.e
MT8195_VDO1_MERGE4_SOUT_SEL (0xf18) should go before
MT8195_VDO1_MIXER_OUT_SOUT_SE (0xf34). Having the register in order
makes reviewers' life a bit easier and can help to avoid redefinitions
in future.
> +#define MERGE4_SOUT_TO_VDOSYS0 (0 << 0)
> +#define MERGE4_SOUT_TO_DPI0_SEL (1 << 0)
> +#define MERGE4_SOUT_TO_DPI1_SEL (2 << 0)
> +#define MERGE4_SOUT_TO_DP_INTF0_SEL (3 << 0)
> +
> +#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
> +#define VPP_MERGE0_P0_SEL_IN_FROM_SVPP2 (0 << 0)
> +#define VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 (1 << 0)
> +
> +#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
> +#define VPP_MERGE0_P1_SEL_IN_FROM_SVPP3 (0 << 0)
> +#define VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 (1 << 0)
> +
> +#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
> +#define VPP_MERGE1_P0_SEL_IN_FROM_VPP3_ASYNC_SOUT (0 << 0)
> +#define VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 (1 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
> +#define MIXER_IN1_SEL_IN_FROM_HDR_VDO_FE0 (0 << 0)
> +#define MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT (1 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
> +#define MIXER_IN2_SEL_IN_FROM_HDR_VDO_FE1 (0 << 0)
> +#define MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT (1 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
> +#define MIXER_IN3_SEL_IN_FROM_HDR_GFX_FE0 (0 << 0)
> +#define MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT (1 << 0)
> +
> +#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
> +#define MIXER_IN4_SEL_IN_FROM_HDR_GFX_FE1 (0 << 0)
> +#define MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT (1 << 0)
> +
> +#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
> +#define MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
> +#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN1_SOUT (1 << 0)
> +#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN2_SOUT (2 << 0)
> +#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN3_SOUTR (3 << 0)
> +#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN4_SOUTR (4 << 0)
> +
> +#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
> +#define MERGE4_ASYNC_SEL_IN_FROM_HDR_VDO_BE0 (0 << 0)
> +#define MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT (1 << 0)
> +#define MERGE4_ASYNC_SEL_IN_FROM_MERGE0_ASYNC_SOUT (2 << 0)
> +#define MERGE4_ASYNC_SEL_IN_FROM_MERGE1_ASYNC_SOUT (3 << 0)
> +#define MERGE4_ASYNC_SEL_IN_FROM_MERGE2_ASYNC_SOUT (4 << 0)
> +#define MERGE4_ASYNC_SEL_IN_FROM_MERGE3_ASYNC_SOUT (5 << 0)
> +
> +#define MT8195_VDO1_DISP_DPI0_SEL_IN 0xf0c
> +#define DISP_DPI0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
> +#define DISP_DPI0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
> +#define DISP_DPI0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
> +
> +#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
> +#define DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
> +#define DISP_DPI1_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
> +#define DISP_DPI1_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
> +
> +#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
> +#define DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
I see some definitions that are not used. Is it a good practice to
only include the ones that are used and remove the others. Then
introduce the other when are really required.
Thanks,
Enric
> +#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
> +#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
> +
> +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> + MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL0_TO_DISP_RDMA0
> + }, {
> + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> + MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL1_TO_DISP_RDMA1
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_IN, SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_IN, SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DISP_DITHER0
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> + MT8195_VDO0_SEL_OUT, SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_OUT, DDP_COMPONENT_DSI0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> + MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_DSI0
> + }, {
> + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> + MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> + }
> +};
> +
> +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 080660ef11bf..1fb241750897 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -13,6 +13,7 @@
> #include "mtk-mmsys.h"
> #include "mt8167-mmsys.h"
> #include "mt8183-mmsys.h"
> +#include "mt8195-mmsys.h"
>
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .clk_driver = "clk-mt2701-mm",
> @@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> + .clk_driver = "clk-mt8195-vdo0",
> + .routes = mmsys_mt8195_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> +};
> +
> struct mtk_mmsys {
> void __iomem *regs;
> const struct mtk_mmsys_driver_data *data;
> @@ -157,6 +164,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
> .compatible = "mediatek,mt8183-mmsys",
> .data = &mt8183_mmsys_driver_data,
> },
> + {
> + .compatible = "mediatek,mt8195-vdosys0",
I'm not against it but I think it would be more coherent following the
current compatible naming, why not 'mediatek,mt8195-mmsys' ?
Thanks,
Enric
> + .data = &mt8195_vdosys0_driver_data,
> + },
> { }
> };
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 2228bf6133da..01bedfb08094 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -39,6 +39,15 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_UFOE,
> DDP_COMPONENT_WDMA0,
> DDP_COMPONENT_WDMA1,
> + DDP_COMPONENT_MERGE0,
> + DDP_COMPONENT_MERGE1,
> + DDP_COMPONENT_MERGE2,
> + DDP_COMPONENT_MERGE3,
> + DDP_COMPONENT_MERGE4,
> + DDP_COMPONENT_MERGE5,
> + DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_DSC1,
> + DDP_COMPONENT_DP_INTF0,
> DDP_COMPONENT_ID_MAX,
> };
>
> --
> 2.18.0
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v4 3/6] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
2021-07-23 9:02 [PATCH v4 0/6] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
2021-07-23 9:02 ` [PATCH v4 1/6] arm64: dts: mt8195: add display node for vdosys0 jason-jh.lin
2021-07-23 9:02 ` [PATCH v4 2/6] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
@ 2021-07-23 9:02 ` jason-jh.lin
2021-07-23 9:02 ` [PATCH v4 4/6] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 jason-jh.lin
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: jason-jh.lin @ 2021-07-23 9:02 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, fshao
Cc: David Airlie, Daniel Vetter, Enric Balletbo i Serra, hsinyi,
jason-jh . lin, Yongqiang Niu, nancy.lin, singo.chang,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
dri-devel
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/soc/mediatek/mtk-mutex.c | 93 ++++++++++++++++++++++++++++++--
1 file changed, 90 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2e4bcc300576..cb8bbf7f3fd8 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -17,6 +17,9 @@
#define MT8183_MUTEX0_MOD0 0x30
#define MT8183_MUTEX0_SOF0 0x2c
+#define MT8195_DISP_MUTEX0_MOD0 0x30
+#define MT8195_DISP_MUTEX0_SOF 0x2c
+
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
@@ -67,6 +70,36 @@
#define MT8173_MUTEX_MOD_DISP_PWM1 24
#define MT8173_MUTEX_MOD_DISP_OD 25
+#define MT8195_MUTEX_MOD_DISP_OVL0 0
+#define MT8195_MUTEX_MOD_DISP_WDMA0 1
+#define MT8195_MUTEX_MOD_DISP_RDMA0 2
+#define MT8195_MUTEX_MOD_DISP_COLOR0 3
+#define MT8195_MUTEX_MOD_DISP_CCORR0 4
+#define MT8195_MUTEX_MOD_DISP_AAL0 5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
+#define MT8195_MUTEX_MOD_DISP_DITHER0 7
+#define MT8195_MUTEX_MOD_DISP_DSI0 8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
+#define MT8195_MUTEX_MOD_DISP_OVL1 10
+#define MT8195_MUTEX_MOD_DISP_WDMA1 11
+#define MT8195_MUTEX_MOD_DISP_RDMA1 12
+#define MT8195_MUTEX_MOD_DISP_COLOR1 13
+#define MT8195_MUTEX_MOD_DISP_CCORR1 14
+#define MT8195_MUTEX_MOD_DISP_AAL1 15
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
+#define MT8195_MUTEX_MOD_DISP_DITHER1 17
+#define MT8195_MUTEX_MOD_DISP_DSI1 18
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
+#define MT8195_MUTEX_MOD_DISP_PWM0 27
+#define MT8195_MUTEX_MOD_DISP_PWM1 28
+
#define MT2712_MUTEX_MOD_DISP_PWM2 10
#define MT2712_MUTEX_MOD_DISP_OVL0 11
#define MT2712_MUTEX_MOD_DISP_OVL1 12
@@ -101,12 +134,27 @@
#define MT2712_MUTEX_SOF_DSI3 6
#define MT8167_MUTEX_SOF_DPI0 2
#define MT8167_MUTEX_SOF_DPI1 3
+
#define MT8183_MUTEX_SOF_DSI0 1
#define MT8183_MUTEX_SOF_DPI0 2
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8195_MUTEX_SOF_DSI0 1
+#define MT8195_MUTEX_SOF_DSI1 2
+#define MT8195_MUTEX_SOF_DP_INTF0 3
+#define MT8195_MUTEX_SOF_DP_INTF1 4
+#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
+
+#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
+#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
+#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
+
struct mtk_mutex {
int id;
bool claimed;
@@ -120,6 +168,9 @@ enum mtk_mutex_sof_id {
MUTEX_SOF_DPI1,
MUTEX_SOF_DSI2,
MUTEX_SOF_DSI3,
+ MUTEX_SOF_DP_INTF0,
+ MUTEX_SOF_DP_INTF1,
+ DDP_MUTEX_SOF_MAX,
};
struct mtk_mutex_data {
@@ -214,7 +265,22 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+ [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+ [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+ [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+ [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+ [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+ [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -224,7 +290,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
};
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -232,12 +298,24 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
};
/* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
};
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+ [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+ [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+ [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+ [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+ [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+ [MUTEX_SOF_DP_INTF0] =
+ MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+ [MUTEX_SOF_DP_INTF1] =
+ MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -275,6 +353,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.no_clk = true,
};
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+ .mutex_mod = mt8195_mutex_mod,
+ .mutex_sof = mt8195_mutex_sof,
+ .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
struct mtk_mutex *mtk_mutex_get(struct device *dev)
{
struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -507,6 +592,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
.data = &mt8173_mutex_driver_data},
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = &mt8183_mutex_driver_data},
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = &mt8195_mutex_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
--
2.18.0
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v4 4/6] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
2021-07-23 9:02 [PATCH v4 0/6] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
` (2 preceding siblings ...)
2021-07-23 9:02 ` [PATCH v4 3/6] soc: mediatek: add mtk-mutex " jason-jh.lin
@ 2021-07-23 9:02 ` jason-jh.lin
2021-07-23 9:02 ` [PATCH v4 5/6] drm/mediatek: add DSC " jason-jh.lin
2021-07-23 9:02 ` [PATCH v4 6/6] drm/mediatek: add MERGE " jason-jh.lin
5 siblings, 0 replies; 8+ messages in thread
From: jason-jh.lin @ 2021-07-23 9:02 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, fshao
Cc: David Airlie, Daniel Vetter, Enric Balletbo i Serra, hsinyi,
jason-jh . lin, Yongqiang Niu, nancy.lin, singo.chang,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
dri-devel
Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 24 ++++++++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 728aaadfea8c..00e9827acefe 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
.fifo_size = 5 * SZ_1K,
};
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+ .fifo_size = 1920,
+};
+
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = &mt2701_rdma_driver_data},
@@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
.data = &mt8173_rdma_driver_data},
{ .compatible = "mediatek,mt8183-disp-rdma",
.data = &mt8183_rdma_driver_data},
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = &mt8195_rdma_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b46bdb8985da..d6f6d1bdad85 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_DP_INTF0,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .main_path = mt8195_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
@@ -410,6 +428,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8183-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-wdma",
.data = (void *)MTK_DISP_WDMA },
{ .compatible = "mediatek,mt8183-disp-ccorr",
@@ -448,6 +468,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2701-disp-pwm",
.data = (void *)MTK_DISP_BLS },
{ .compatible = "mediatek,mt8173-disp-pwm",
@@ -468,6 +490,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = &mt8173_mmsys_driver_data},
{ .compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data},
+ {.compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data},
{ }
};
MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v4 5/6] drm/mediatek: add DSC support for mt8195
2021-07-23 9:02 [PATCH v4 0/6] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
` (3 preceding siblings ...)
2021-07-23 9:02 ` [PATCH v4 4/6] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 jason-jh.lin
@ 2021-07-23 9:02 ` jason-jh.lin
2021-07-23 9:02 ` [PATCH v4 6/6] drm/mediatek: add MERGE " jason-jh.lin
5 siblings, 0 replies; 8+ messages in thread
From: jason-jh.lin @ 2021-07-23 9:02 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, fshao
Cc: David Airlie, Daniel Vetter, Enric Balletbo i Serra, hsinyi,
jason-jh . lin, Yongqiang Niu, nancy.lin, singo.chang,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
dri-devel
Add DSC into mtk_drm_ddp_comp to support for mt8195.
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 46 +++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +
3 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 75bc00e17fc4..6f4a9b8c9914 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -65,6 +65,12 @@
#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
#define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0)
+#define DISP_REG_DSC_CON 0x0000
+#define DSC_EN BIT(0)
+#define DSC_DUAL_INOUT BIT(2)
+#define DSC_BYPASS BIT(4)
+#define DSC_UFOE_SEL BIT(16)
+
struct mtk_ddp_comp_dev {
struct clk *clk;
void __iomem *regs;
@@ -246,6 +252,35 @@ static void mtk_dither_stop(struct device *dev)
writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
}
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ /* dsc bypass mode */
+ mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_BYPASS);
+ mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_UFOE_SEL);
+ mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+ DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ writel_relaxed(DSC_EN, &priv->regs + DISP_REG_DSC_CON);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
static const struct mtk_ddp_comp_funcs ddp_aal = {
.clk_enable = mtk_ddp_clk_enable,
.clk_disable = mtk_ddp_clk_disable,
@@ -284,6 +319,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
.stop = mtk_dpi_stop,
};
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+ .clk_enable = mtk_ddp_clk_enable,
+ .clk_disable = mtk_ddp_clk_disable,
+ .config = mtk_dsc_config,
+ .start = mtk_dsc_start,
+ .stop = mtk_dsc_stop,
+};
+
static const struct mtk_ddp_comp_funcs ddp_dsi = {
.start = mtk_dsi_ddp_start,
.stop = mtk_dsi_ddp_stop,
@@ -356,6 +399,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
[MTK_DISP_BLS] = "bls",
+ [MTK_DISP_DSC] = "dsc",
};
struct mtk_ddp_comp_match {
@@ -374,6 +418,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
+ [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
+ [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index bb914d976cf5..661fb620e266 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -34,6 +34,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_MUTEX,
MTK_DISP_OD,
MTK_DISP_BLS,
+ MTK_DISP_DSC,
MTK_DDP_COMP_TYPE_MAX,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index d6f6d1bdad85..0f6bb4bdc58a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -446,6 +446,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8183-disp-dither",
.data = (void *)MTK_DISP_DITHER },
+ { .compatible = "mediatek,mt8195-disp-dsc",
+ .data = (void *)MTK_DISP_DSC },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt2701-dsi",
--
2.18.0
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Linux-mediatek@lists.infradead.org
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^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v4 6/6] drm/mediatek: add MERGE support for mt8195
2021-07-23 9:02 [PATCH v4 0/6] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
` (4 preceding siblings ...)
2021-07-23 9:02 ` [PATCH v4 5/6] drm/mediatek: add DSC " jason-jh.lin
@ 2021-07-23 9:02 ` jason-jh.lin
5 siblings, 0 replies; 8+ messages in thread
From: jason-jh.lin @ 2021-07-23 9:02 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, fshao
Cc: David Airlie, Daniel Vetter, Enric Balletbo i Serra, hsinyi,
jason-jh . lin, Yongqiang Niu, nancy.lin, singo.chang,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
dri-devel
Add MERGE module file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is base on [1]
[1]add mt8195 SoC DRM binding
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 277 ++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 16 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 6 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
7 files changed, 309 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index dc54a7a69005..538e0087a44c 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -3,6 +3,7 @@
mediatek-drm-y := mtk_disp_ccorr.o \
mtk_disp_color.o \
mtk_disp_gamma.o \
+ mtk_disp_merge.o \
mtk_disp_ovl.o \
mtk_disp_rdma.o \
mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index cafd9df2d63b..f407cd9d873e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -46,6 +46,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
void mtk_gamma_start(struct device *dev);
void mtk_gamma_stop(struct device *dev);
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+ unsigned int height, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
void mtk_ovl_bgclr_in_on(struct device *dev);
void mtk_ovl_bgclr_in_off(struct device *dev);
void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..594d76ccd205
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL 0x000
+#define FLD_MERGE_EN BIT(0)
+#define FLD_MERGE_RST BIT(4)
+#define FLD_MERGE_LR_SWAP BIT(8)
+#define FLD_MERGE_DCM_DIS BIT(12)
+
+#define DISP_MERGE_CFG_0 0x010
+#define DISP_MERGE_CFG_4 0x020
+#define DISP_MERGE_CFG_10 0x038
+#define DISP_MERGE_CFG_12 0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE 6
+#define CFG_10_10_2PI_2PO_BUF_MODE 8
+#define DISP_MERGE_CFG_24 0x070
+#define DISP_MERGE_CFG_25 0x074
+
+#define DISP_MERGE_CFG_36 0x0a0
+#define DISP_MERGE_CFG_36_FLD_ULTRA_EN GENMASK(0, 0)
+#define DISP_MERGE_CFG_36_FLD_PREULTRA_EN GENMASK(4, 4)
+#define DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN GENMASK(8, 8)
+#define DISP_MERGE_CFG_37 0x0a4
+#define DISP_MERGE_CFG_37_FLD_BUFFER_MODE GENMASK(1, 0)
+#define DISP_MERGE_CFG_38 0x0a8
+#define DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA GENMASK(0, 0)
+#define DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA GENMASK(4, 4)
+#define DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH GENMASK(31, 16)
+#define DISP_MERGE_CFG_39 0x0ac
+#define DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA GENMASK(8, 8)
+#define DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA GENMASK(12, 12)
+#define DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH GENMASK(31, 16)
+#define DISP_MERGE_CFG_40 0x0b0
+#define DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW GENMASK(15, 0)
+#define DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH GENMASK(31, 16)
+#define DISP_MERGE_CFG_41 0x0b4
+#define DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW GENMASK(15, 0)
+#define DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
+
+struct mtk_disp_merge {
+ void __iomem *regs;
+ struct clk *clk;
+ struct clk *async_clk;
+ struct cmdq_client_reg cmdq_reg;
+ bool fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write(NULL, 0x1, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write(NULL, 0x0, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+ struct cmdq_pkt *handle)
+{
+ unsigned int ultra_en = 1;
+ unsigned int preultra_en = 1;
+ unsigned int halt_for_dvfs_en = 0;
+ /*
+ * 0 : Off
+ * 1 : SRAM 0
+ * 2 : SRAM 1
+ * 3 : SRAM 0 + SRAM 1
+ */
+ unsigned int buffer_mode = 3;
+ /* 6 us, 600M pixel/sec */
+ unsigned int ultra_th_low = 6 * 600;
+ /* 8 us, 600M pixel/sec */
+ unsigned int ultra_th_high = 8 * 600;
+ /* 8 us, 600M pixel/sec */
+ unsigned int preultra_th_low = 8 * 600;
+ /* 9 us, 600M pixel/sec */
+ unsigned int preultra_th_high = 9 * 600;
+
+ mtk_ddp_write_mask(handle, ultra_en << 0 | preultra_en << 4 | halt_for_dvfs_en << 8,
+ &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_36,
+ DISP_MERGE_CFG_36_FLD_ULTRA_EN | DISP_MERGE_CFG_36_FLD_PREULTRA_EN |
+ DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN);
+
+ mtk_ddp_write_mask(handle, buffer_mode << 0,
+ &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_37,
+ DISP_MERGE_CFG_37_FLD_BUFFER_MODE);
+
+ mtk_ddp_write_mask(handle, 0,
+ &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_38,
+ DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA |
+ DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA |
+ DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH);
+
+ mtk_ddp_write_mask(handle, 0,
+ &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_39,
+ DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA |
+ DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA |
+ DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH);
+
+ mtk_ddp_write_mask(handle, ultra_th_low << 0 | ultra_th_high << 16,
+ &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_40,
+ DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW |
+ DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH);
+
+ mtk_ddp_write_mask(handle, preultra_th_low << 0 | preultra_th_high << 16,
+ &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_41,
+ DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW |
+ DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *handle)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+ unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+ if (!h || !w) {
+ pr_err("%s: input width(%d) or height(%d) is invalid\n",
+ __func__, w, h);
+ return;
+ }
+
+ if (priv->fifo_en) {
+ mtk_merge_fifo_setting(priv, handle);
+ mode = CFG_10_10_2PI_2PO_BUF_MODE;
+ }
+
+ mtk_ddp_write(handle, (h << 16 | w), &priv->cmdq_reg, priv->regs,
+ DISP_MERGE_CFG_0);
+ mtk_ddp_write(handle, (h << 16 | w), &priv->cmdq_reg, priv->regs,
+ DISP_MERGE_CFG_4);
+ mtk_ddp_write(handle, (h << 16 | w), &priv->cmdq_reg, priv->regs,
+ DISP_MERGE_CFG_24);
+ mtk_ddp_write(handle, (h << 16 | w), &priv->cmdq_reg, priv->regs,
+ DISP_MERGE_CFG_25);
+ /* no swap */
+ mtk_ddp_write_mask(handle, 0, &priv->cmdq_reg, priv->regs,
+ DISP_MERGE_CFG_10, 0x1f);
+ mtk_ddp_write_mask(handle, mode, &priv->cmdq_reg, priv->regs,
+ DISP_MERGE_CFG_12, 0x1f);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+ int ret = 0;
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret)
+ pr_err("merge clk prepare enable failed\n");
+
+ if (priv->async_clk) {
+ ret = clk_prepare_enable(priv->async_clk);
+ if (ret)
+ pr_err("async clk prepare enable failed\n");
+ }
+
+ return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ if (priv->async_clk)
+ clk_disable_unprepare(priv->async_clk);
+
+ clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+ .bind = mtk_disp_merge_bind,
+ .unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct mtk_disp_merge *priv;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "failed to ioremap merge\n");
+ return PTR_ERR(priv->regs);
+ }
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get merge clk\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ priv->async_clk = of_clk_get(dev->of_node, 1);
+ if (IS_ERR(priv->async_clk)) {
+ ret = PTR_ERR(priv->async_clk);
+ dev_dbg(dev, "No merge async clock: %d\n", ret);
+ priv->async_clk = NULL;
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ priv->fifo_en = of_property_read_bool(dev->of_node,
+ "mediatek,merge-fifo-en");
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_disp_merge_component_ops);
+ if (ret != 0)
+ dev_err(dev, "Failed to add component: %d\n", ret);
+
+ return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-merge", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+ .probe = mtk_disp_merge_probe,
+ .remove = mtk_disp_merge_remove,
+ .driver = {
+ .name = "mediatek-disp-merge",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_disp_merge_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 6f4a9b8c9914..a037b564052e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -376,6 +376,14 @@ static const struct mtk_ddp_comp_funcs ddp_rdma = {
.layer_config = mtk_rdma_layer_config,
};
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+ .clk_enable = mtk_merge_clk_enable,
+ .clk_disable = mtk_merge_clk_disable,
+ .start = mtk_merge_start,
+ .stop = mtk_merge_stop,
+ .config = mtk_merge_config,
+};
+
static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.clk_enable = mtk_ddp_clk_enable,
.clk_disable = mtk_ddp_clk_disable,
@@ -400,6 +408,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_OD] = "od",
[MTK_DISP_BLS] = "bls",
[MTK_DISP_DSC] = "dsc",
+ [MTK_DISP_MERGE] = "merge",
};
struct mtk_ddp_comp_match {
@@ -425,6 +434,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
+ [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
+ [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
+ [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
+ [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
+ [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
+ [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
[DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
[DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
@@ -557,6 +572,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_GAMMA ||
type == MTK_DPI ||
type == MTK_DSI ||
+ type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 661fb620e266..0afd78c0bc92 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -35,6 +35,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_OD,
MTK_DISP_BLS,
MTK_DISP_DSC,
+ MTK_DISP_MERGE,
MTK_DDP_COMP_TYPE_MAX,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 0f6bb4bdc58a..53e0de3f17d7 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -448,6 +448,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_DITHER },
{ .compatible = "mediatek,mt8195-disp-dsc",
.data = (void *)MTK_DISP_DSC },
+ { .compatible = "mediatek,mt8195-disp-merge",
+ .data = (void *)MTK_DISP_MERGE },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt2701-dsi",
@@ -558,13 +560,14 @@ static int mtk_drm_probe(struct platform_device *pdev)
private->comp_node[comp_id] = of_node_get(node);
/*
- * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
+ * Currently only the CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
* blocks have separate component platform drivers and initialize their own
* DDP component structure. The others are initialized here.
*/
if (comp_type == MTK_DISP_CCORR ||
comp_type == MTK_DISP_COLOR ||
comp_type == MTK_DISP_GAMMA ||
+ comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_RDMA ||
@@ -665,6 +668,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_ccorr_driver,
&mtk_disp_color_driver,
&mtk_disp_gamma_driver,
+ &mtk_disp_merge_driver,
&mtk_disp_ovl_driver,
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 637f5669e895..0fa417219a69 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -49,6 +49,7 @@ struct mtk_drm_private {
extern struct platform_driver mtk_disp_ccorr_driver;
extern struct platform_driver mtk_disp_color_driver;
extern struct platform_driver mtk_disp_gamma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
--
2.18.0
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^ permalink raw reply related [flat|nested] 8+ messages in thread