* [PATCH] arm64: dts: mt8183: support coresight-cpu-debug for mt8183
@ 2021-09-13 9:27 Seiya Wang
2021-09-14 18:05 ` Matthias Brugger
0 siblings, 1 reply; 2+ messages in thread
From: Seiya Wang @ 2021-09-13 9:27 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger
Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
srv_heupstream, Seiya Wang
Add coresight-cpu-debug nodes to mt8183 for dumping
EDPRSR, EDPCSR, EDCIDSR, EDVIDSR
while kernel panic happens
Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 64 ++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 409cf827970c..3ad4dd47518a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -367,6 +367,70 @@
reg = <0 0x0c530a80 0 0x50>;
};
+ cpu_debug0: cpu-debug@d410000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0x0 0xd410000 0x0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ };
+
+ cpu_debug1: cpu-debug@d510000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0x0 0xd510000 0x0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu1>;
+ };
+
+ cpu_debug2: cpu-debug@d610000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0x0 0xd610000 0x0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu2>;
+ };
+
+ cpu_debug3: cpu-debug@d710000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0x0 0xd710000 0x0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu3>;
+ };
+
+ cpu_debug4: cpu-debug@d810000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0x0 0xd810000 0x0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu4>;
+ };
+
+ cpu_debug5: cpu-debug@d910000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0x0 0xd910000 0x0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu5>;
+ };
+
+ cpu_debug6: cpu-debug@da10000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0x0 0xda10000 0x0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu6>;
+ };
+
+ cpu_debug7: cpu-debug@db10000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0x0 0xdb10000 0x0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu7>;
+ };
+
topckgen: syscon@10000000 {
compatible = "mediatek,mt8183-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
--
2.14.1
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] arm64: dts: mt8183: support coresight-cpu-debug for mt8183
2021-09-13 9:27 [PATCH] arm64: dts: mt8183: support coresight-cpu-debug for mt8183 Seiya Wang
@ 2021-09-14 18:05 ` Matthias Brugger
0 siblings, 0 replies; 2+ messages in thread
From: Matthias Brugger @ 2021-09-14 18:05 UTC (permalink / raw)
To: Seiya Wang, Rob Herring
Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
srv_heupstream
On 13/09/2021 11:27, Seiya Wang wrote:
> Add coresight-cpu-debug nodes to mt8183 for dumping
> EDPRSR, EDPCSR, EDCIDSR, EDVIDSR
> while kernel panic happens
>
> Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 64 ++++++++++++++++++++++++++++++++
> 1 file changed, 64 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 409cf827970c..3ad4dd47518a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -367,6 +367,70 @@
> reg = <0 0x0c530a80 0 0x50>;
> };
>
> + cpu_debug0: cpu-debug@d410000 {
> + compatible = "arm,coresight-cpu-debug","arm,primecell";
Missing a space: "arm,coresight-cpu-debug", "arm,primecell";
I suppose that's a copy-paste from the binding doc which is wrong. Other then
that, things look fine.
Regards,
Matthias
> + reg = <0x0 0xd410000 0x0 0x1000>;
> + clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu0>;
> + };
> +
> + cpu_debug1: cpu-debug@d510000 {
> + compatible = "arm,coresight-cpu-debug","arm,primecell";
> + reg = <0x0 0xd510000 0x0 0x1000>;
> + clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu1>;
> + };
> +
> + cpu_debug2: cpu-debug@d610000 {
> + compatible = "arm,coresight-cpu-debug","arm,primecell";
> + reg = <0x0 0xd610000 0x0 0x1000>;
> + clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu2>;
> + };
> +
> + cpu_debug3: cpu-debug@d710000 {
> + compatible = "arm,coresight-cpu-debug","arm,primecell";
> + reg = <0x0 0xd710000 0x0 0x1000>;
> + clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu3>;
> + };
> +
> + cpu_debug4: cpu-debug@d810000 {
> + compatible = "arm,coresight-cpu-debug","arm,primecell";
> + reg = <0x0 0xd810000 0x0 0x1000>;
> + clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu4>;
> + };
> +
> + cpu_debug5: cpu-debug@d910000 {
> + compatible = "arm,coresight-cpu-debug","arm,primecell";
> + reg = <0x0 0xd910000 0x0 0x1000>;
> + clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu5>;
> + };
> +
> + cpu_debug6: cpu-debug@da10000 {
> + compatible = "arm,coresight-cpu-debug","arm,primecell";
> + reg = <0x0 0xda10000 0x0 0x1000>;
> + clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu6>;
> + };
> +
> + cpu_debug7: cpu-debug@db10000 {
> + compatible = "arm,coresight-cpu-debug","arm,primecell";
> + reg = <0x0 0xdb10000 0x0 0x1000>;
> + clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu7>;
> + };
> +
> topckgen: syscon@10000000 {
> compatible = "mediatek,mt8183-topckgen", "syscon";
> reg = <0 0x10000000 0 0x1000>;
>
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