* [PATCH v2 0/4] add new SoC mt8186 support for spi-mtk-nor
@ 2022-01-18 14:15 guochun.mao
2022-01-18 14:15 ` [PATCH 1/4] dt-bindings: spi: add mt8186-nor compatible string guochun.mao
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: guochun.mao @ 2022-01-18 14:15 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Mark Brown, Rob Herring
Cc: Matthias Brugger, Zhen Zhang, Bayi Cheng, Chuanhong Guo,
Bin Zhang, linux-mediatek, srv_heupstream,
project_global_chrome_upstream_group
These patches is mainly for adding mt8186 support.
The spi nor controller of mt8186 has some differences,
it needs one more clk, axi_s, for dma feature.
And also needs one extra dummy bit when read flash registers.
The version 2 patches fix some typos for bindings file,
correct return value of probe function in spi-mtk-nor.c file,
and add some comments to explain why add extra dummy bit.
Guochun Mao (4):
dt-bindings: spi: add mt8186-nor compatible string
spi: spi-mtk-nor: improve device table for adding more capabilities
spi: spi-mtk-nor: add new soc mt8186 support
spi: spi-mtk-nor: add axi_s clock for mt8186
.../bindings/spi/mediatek,spi-mtk-nor.yaml | 4 ++
drivers/spi/spi-mtk-nor.c | 71 ++++++++++++++++---
2 files changed, 65 insertions(+), 10 deletions(-)
--
2.18.0
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/4] dt-bindings: spi: add mt8186-nor compatible string
2022-01-18 14:15 [PATCH v2 0/4] add new SoC mt8186 support for spi-mtk-nor guochun.mao
@ 2022-01-18 14:15 ` guochun.mao
2022-01-18 14:15 ` [PATCH 2/4] spi: spi-mtk-nor: improve device table for adding more capabilities guochun.mao
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: guochun.mao @ 2022-01-18 14:15 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Mark Brown, Rob Herring
Cc: Matthias Brugger, Zhen Zhang, Bayi Cheng, Chuanhong Guo,
Bin Zhang, linux-mediatek, srv_heupstream,
project_global_chrome_upstream_group, Guochun Mao
From: Guochun Mao <guochun.mao@mediatek.com>
Add MT8186 spi-nor controller support.
MT8186 needs a new clock name, axi_s, for spi nor axi slave bus clock.
Signed-off-by: Guochun Mao <guochun.mao@mediatek.com>
Signed-off-by: Zhen Zhang <zhen.zhang@mediatek.com>
---
.../devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml
index 4e4694e3d539..be3cc7faed53 100644
--- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml
+++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml
@@ -30,6 +30,7 @@ properties:
- mediatek,mt7622-nor
- mediatek,mt7623-nor
- mediatek,mt7629-nor
+ - mediatek,mt8186-nor
- mediatek,mt8192-nor
- mediatek,mt8195-nor
- enum:
@@ -49,6 +50,8 @@ properties:
- description: clock used for controller
- description: clock used for nor dma bus. this depends on hardware
design, so this is optional.
+ - description: clock used for controller axi slave bus.
+ this depends on hardware design, so it is optional.
clock-names:
minItems: 2
@@ -56,6 +59,7 @@ properties:
- const: spi
- const: sf
- const: axi
+ - const: axi_s
required:
- compatible
--
2.25.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/4] spi: spi-mtk-nor: improve device table for adding more capabilities
2022-01-18 14:15 [PATCH v2 0/4] add new SoC mt8186 support for spi-mtk-nor guochun.mao
2022-01-18 14:15 ` [PATCH 1/4] dt-bindings: spi: add mt8186-nor compatible string guochun.mao
@ 2022-01-18 14:15 ` guochun.mao
2022-01-18 14:15 ` [PATCH 3/4] spi: spi-mtk-nor: add new soc mt8186 support guochun.mao
2022-01-18 14:15 ` [PATCH 4/4] spi: spi-mtk-nor: add axi_s clock for mt8186 guochun.mao
3 siblings, 0 replies; 5+ messages in thread
From: guochun.mao @ 2022-01-18 14:15 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Mark Brown, Rob Herring
Cc: Matthias Brugger, Zhen Zhang, Bayi Cheng, Chuanhong Guo,
Bin Zhang, linux-mediatek, srv_heupstream,
project_global_chrome_upstream_group, Guochun Mao
From: Guochun Mao <guochun.mao@mediatek.com>
Define a structure for adding more capabilities.
Add a item extra_dummy_bit for new SoCs, due to design changed.
Signed-off-by: Guochun Mao <guochun.mao@mediatek.com>
Signed-off-by: Zhen Zhang <zhen.zhang@mediatek.com>
---
drivers/spi/spi-mtk-nor.c | 48 +++++++++++++++++++++++++++++++--------
1 file changed, 39 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c
index 5c93730615f8..f5ff01f61f42 100644
--- a/drivers/spi/spi-mtk-nor.c
+++ b/drivers/spi/spi-mtk-nor.c
@@ -95,6 +95,17 @@
#define CLK_TO_US(sp, clkcnt) DIV_ROUND_UP(clkcnt, sp->spi_freq / 1000000)
+struct mtk_nor_caps {
+ u8 dma_bits;
+
+ /* extra_dummy_bit is adding for the IP of new SoCs.
+ * Some new SoCs modify the timing of fetching registers' values
+ * and IDs of nor flash, they need a extra_dummy_bit which can add
+ * more clock cycles for fetching data.
+ */
+ u8 extra_dummy_bit;
+};
+
struct mtk_nor {
struct spi_controller *ctlr;
struct device *dev;
@@ -109,6 +120,7 @@ struct mtk_nor {
bool has_irq;
bool high_dma;
struct completion op_done;
+ const struct mtk_nor_caps *caps;
};
static inline void mtk_nor_rmw(struct mtk_nor *sp, u32 reg, u32 set, u32 clr)
@@ -554,7 +566,12 @@ static int mtk_nor_spi_mem_prg(struct mtk_nor *sp, const struct spi_mem_op *op)
}
// trigger op
- writel(prg_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT);
+ if (rx_len)
+ writel(prg_len * BITS_PER_BYTE + sp->caps->extra_dummy_bit,
+ sp->base + MTK_NOR_REG_PRG_CNT);
+ else
+ writel(prg_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT);
+
ret = mtk_nor_cmd_exec(sp, MTK_NOR_CMD_PROGRAM,
prg_len * BITS_PER_BYTE);
if (ret)
@@ -743,9 +760,19 @@ static const struct spi_controller_mem_ops mtk_nor_mem_ops = {
.exec_op = mtk_nor_exec_op
};
+const struct mtk_nor_caps mtk_nor_caps_mt8173 = {
+ .dma_bits = 32,
+ .extra_dummy_bit = 0,
+};
+
+const struct mtk_nor_caps mtk_nor_caps_mt8192 = {
+ .dma_bits = 36,
+ .extra_dummy_bit = 0,
+};
+
static const struct of_device_id mtk_nor_match[] = {
- { .compatible = "mediatek,mt8192-nor", .data = (void *)36 },
- { .compatible = "mediatek,mt8173-nor", .data = (void *)32 },
+ { .compatible = "mediatek,mt8173-nor", .data = &mtk_nor_caps_mt8173 },
+ { .compatible = "mediatek,mt8192-nor", .data = &mtk_nor_caps_mt8192 },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_nor_match);
@@ -754,10 +781,10 @@ static int mtk_nor_probe(struct platform_device *pdev)
{
struct spi_controller *ctlr;
struct mtk_nor *sp;
+ struct mtk_nor_caps *caps;
void __iomem *base;
struct clk *spi_clk, *ctlr_clk, *axi_clk;
int ret, irq;
- unsigned long dma_bits;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
@@ -775,10 +802,12 @@ static int mtk_nor_probe(struct platform_device *pdev)
if (IS_ERR(axi_clk))
return PTR_ERR(axi_clk);
- dma_bits = (unsigned long)of_device_get_match_data(&pdev->dev);
- if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits))) {
- dev_err(&pdev->dev, "failed to set dma mask(%lu)\n", dma_bits);
- return -EINVAL;
+ caps = (struct mtk_nor_caps *)of_device_get_match_data(&pdev->dev);
+
+ ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(caps->dma_bits));
+ if (ret) {
+ dev_err(&pdev->dev, "failed to set dma mask(%u)\n", caps->dma_bits);
+ return ret;
}
ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*sp));
@@ -808,7 +837,8 @@ static int mtk_nor_probe(struct platform_device *pdev)
sp->spi_clk = spi_clk;
sp->ctlr_clk = ctlr_clk;
sp->axi_clk = axi_clk;
- sp->high_dma = (dma_bits > 32);
+ sp->caps = caps;
+ sp->high_dma = caps->dma_bits > 32;
sp->buffer = dmam_alloc_coherent(&pdev->dev,
MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN,
&sp->buffer_dma, GFP_KERNEL);
--
2.25.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 3/4] spi: spi-mtk-nor: add new soc mt8186 support
2022-01-18 14:15 [PATCH v2 0/4] add new SoC mt8186 support for spi-mtk-nor guochun.mao
2022-01-18 14:15 ` [PATCH 1/4] dt-bindings: spi: add mt8186-nor compatible string guochun.mao
2022-01-18 14:15 ` [PATCH 2/4] spi: spi-mtk-nor: improve device table for adding more capabilities guochun.mao
@ 2022-01-18 14:15 ` guochun.mao
2022-01-18 14:15 ` [PATCH 4/4] spi: spi-mtk-nor: add axi_s clock for mt8186 guochun.mao
3 siblings, 0 replies; 5+ messages in thread
From: guochun.mao @ 2022-01-18 14:15 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Mark Brown, Rob Herring
Cc: Matthias Brugger, Zhen Zhang, Bayi Cheng, Chuanhong Guo,
Bin Zhang, linux-mediatek, srv_heupstream,
project_global_chrome_upstream_group, Guochun Mao
From: Guochun Mao <guochun.mao@mediatek.com>
Add compatible mediatek,mt8186-nor implementation.
Signed-off-by: Guochun Mao <guochun.mao@mediatek.com>
Signed-off-by: Zhen Zhang <zhen.zhang@mediatek.com>
---
drivers/spi/spi-mtk-nor.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c
index f5ff01f61f42..e44fdf7c9e4b 100644
--- a/drivers/spi/spi-mtk-nor.c
+++ b/drivers/spi/spi-mtk-nor.c
@@ -765,6 +765,11 @@ const struct mtk_nor_caps mtk_nor_caps_mt8173 = {
.extra_dummy_bit = 0,
};
+const struct mtk_nor_caps mtk_nor_caps_mt8186 = {
+ .dma_bits = 32,
+ .extra_dummy_bit = 1,
+};
+
const struct mtk_nor_caps mtk_nor_caps_mt8192 = {
.dma_bits = 36,
.extra_dummy_bit = 0,
@@ -772,6 +777,7 @@ const struct mtk_nor_caps mtk_nor_caps_mt8192 = {
static const struct of_device_id mtk_nor_match[] = {
{ .compatible = "mediatek,mt8173-nor", .data = &mtk_nor_caps_mt8173 },
+ { .compatible = "mediatek,mt8186-nor", .data = &mtk_nor_caps_mt8186 },
{ .compatible = "mediatek,mt8192-nor", .data = &mtk_nor_caps_mt8192 },
{ /* sentinel */ }
};
--
2.25.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 4/4] spi: spi-mtk-nor: add axi_s clock for mt8186
2022-01-18 14:15 [PATCH v2 0/4] add new SoC mt8186 support for spi-mtk-nor guochun.mao
` (2 preceding siblings ...)
2022-01-18 14:15 ` [PATCH 3/4] spi: spi-mtk-nor: add new soc mt8186 support guochun.mao
@ 2022-01-18 14:15 ` guochun.mao
3 siblings, 0 replies; 5+ messages in thread
From: guochun.mao @ 2022-01-18 14:15 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Mark Brown, Rob Herring
Cc: Matthias Brugger, Zhen Zhang, Bayi Cheng, Chuanhong Guo,
Bin Zhang, linux-mediatek, srv_heupstream,
project_global_chrome_upstream_group, Guochun Mao
From: Guochun Mao <guochun.mao@mediatek.com>
MT8186 needs axi_s clock for DMA feature.
Signed-off-by: Guochun Mao <guochun.mao@mediatek.com>
Signed-off-by: Zhen Zhang <zhen.zhang@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/spi/spi-mtk-nor.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c
index e44fdf7c9e4b..455b4dcb26e9 100644
--- a/drivers/spi/spi-mtk-nor.c
+++ b/drivers/spi/spi-mtk-nor.c
@@ -115,6 +115,7 @@ struct mtk_nor {
struct clk *spi_clk;
struct clk *ctlr_clk;
struct clk *axi_clk;
+ struct clk *axi_s_clk;
unsigned int spi_freq;
bool wbuf_en;
bool has_irq;
@@ -691,6 +692,7 @@ static void mtk_nor_disable_clk(struct mtk_nor *sp)
clk_disable_unprepare(sp->spi_clk);
clk_disable_unprepare(sp->ctlr_clk);
clk_disable_unprepare(sp->axi_clk);
+ clk_disable_unprepare(sp->axi_s_clk);
}
static int mtk_nor_enable_clk(struct mtk_nor *sp)
@@ -714,6 +716,14 @@ static int mtk_nor_enable_clk(struct mtk_nor *sp)
return ret;
}
+ ret = clk_prepare_enable(sp->axi_s_clk);
+ if (ret) {
+ clk_disable_unprepare(sp->spi_clk);
+ clk_disable_unprepare(sp->ctlr_clk);
+ clk_disable_unprepare(sp->axi_clk);
+ return ret;
+ }
+
return 0;
}
@@ -789,7 +799,7 @@ static int mtk_nor_probe(struct platform_device *pdev)
struct mtk_nor *sp;
struct mtk_nor_caps *caps;
void __iomem *base;
- struct clk *spi_clk, *ctlr_clk, *axi_clk;
+ struct clk *spi_clk, *ctlr_clk, *axi_clk, *axi_s_clk;
int ret, irq;
base = devm_platform_ioremap_resource(pdev, 0);
@@ -808,6 +818,10 @@ static int mtk_nor_probe(struct platform_device *pdev)
if (IS_ERR(axi_clk))
return PTR_ERR(axi_clk);
+ axi_s_clk = devm_clk_get_optional(&pdev->dev, "axi_s");
+ if (IS_ERR(axi_s_clk))
+ return PTR_ERR(axi_s_clk);
+
caps = (struct mtk_nor_caps *)of_device_get_match_data(&pdev->dev);
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(caps->dma_bits));
@@ -843,6 +857,7 @@ static int mtk_nor_probe(struct platform_device *pdev)
sp->spi_clk = spi_clk;
sp->ctlr_clk = ctlr_clk;
sp->axi_clk = axi_clk;
+ sp->axi_s_clk = axi_s_clk;
sp->caps = caps;
sp->high_dma = caps->dma_bits > 32;
sp->buffer = dmam_alloc_coherent(&pdev->dev,
--
2.25.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-01-18 14:16 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2022-01-18 14:15 [PATCH v2 0/4] add new SoC mt8186 support for spi-mtk-nor guochun.mao
2022-01-18 14:15 ` [PATCH 1/4] dt-bindings: spi: add mt8186-nor compatible string guochun.mao
2022-01-18 14:15 ` [PATCH 2/4] spi: spi-mtk-nor: improve device table for adding more capabilities guochun.mao
2022-01-18 14:15 ` [PATCH 3/4] spi: spi-mtk-nor: add new soc mt8186 support guochun.mao
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