* [PATCH v6 0/2] Add support for MT8195 MDP3
@ 2023-09-22 6:50 Moudy Ho
2023-09-22 6:50 ` [PATCH v6 1/2] arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes Moudy Ho
2023-09-22 6:50 ` [PATCH v6 2/2] arm64: dts: mediatek: mt8195: add MDP3 nodes Moudy Ho
0 siblings, 2 replies; 6+ messages in thread
From: Moudy Ho @ 2023-09-22 6:50 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Moudy Ho
Changes since v5:
- Rebase on v6.6-rc2
- Add the required property - interrupts in components
AAL, COLOR and OVL.
Hi,
The purpose of this patch is to separate the MDP3-related dtsi from
the original mailing list mentioned below:
https://lore.kernel.org/all/20230912075805.11432-2-moudy.ho@mediatek.com/
Introducing more components for MDP3 in MT8195.
Moudy Ho (2):
arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes
arm64: dts: mediatek: mt8195: add MDP3 nodes
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 +-
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 388 +++++++++++++++++++++++
2 files changed, 392 insertions(+), 2 deletions(-)
--
2.18.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v6 1/2] arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes
2023-09-22 6:50 [PATCH v6 0/2] Add support for MT8195 MDP3 Moudy Ho
@ 2023-09-22 6:50 ` Moudy Ho
2023-09-22 8:29 ` AngeloGioacchino Del Regno
2023-09-22 6:50 ` [PATCH v6 2/2] arm64: dts: mediatek: mt8195: add MDP3 nodes Moudy Ho
1 sibling, 1 reply; 6+ messages in thread
From: Moudy Ho @ 2023-09-22 6:50 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Moudy Ho
In order to generalize the node names, the DMA-related nodes
corresponding to MT8183 MDP3 need to be corrected.
Fixes: 60a2fb8d202a ("arm64: dts: mt8183: add MediaTek MDP3 nodes")
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5169779d01df..bab68c233792 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1781,7 +1781,7 @@
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
- mdp3-rdma0@14001000 {
+ dma-controller0@14001000 {
compatible = "mediatek,mt8183-mdp3-rdma";
reg = <0 0x14001000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
@@ -1793,6 +1793,7 @@
iommus = <&iommu M4U_PORT_MDP_RDMA0>;
mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
<&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
+ #dma-cells = <1>;
};
mdp3-rsz0@14003000 {
@@ -1813,7 +1814,7 @@
clocks = <&mmsys CLK_MM_MDP_RSZ1>;
};
- mdp3-wrot0@14005000 {
+ dma-controller@14005000 {
compatible = "mediatek,mt8183-mdp3-wrot";
reg = <0 0x14005000 0 0x1000>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
@@ -1822,6 +1823,7 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_MDP_WROT0>;
iommus = <&iommu M4U_PORT_MDP_WROT0>;
+ #dma-cells = <1>;
};
mdp3-wdma@14006000 {
--
2.18.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v6 2/2] arm64: dts: mediatek: mt8195: add MDP3 nodes
2023-09-22 6:50 [PATCH v6 0/2] Add support for MT8195 MDP3 Moudy Ho
2023-09-22 6:50 ` [PATCH v6 1/2] arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes Moudy Ho
@ 2023-09-22 6:50 ` Moudy Ho
2023-09-22 8:29 ` AngeloGioacchino Del Regno
1 sibling, 1 reply; 6+ messages in thread
From: Moudy Ho @ 2023-09-22 6:50 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Moudy Ho
Add device nodes for Media Data Path 3 (MDP3) modules.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 388 +++++++++++++++++++++++
1 file changed, 388 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 4dbbf8fdab75..cf61ba7b8956 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1960,6 +1960,114 @@
#clock-cells = <1>;
};
+ dma-controller@14001000 {
+ compatible = "mediatek,mt8195-mdp3-rdma";
+ reg = <0 0x14001000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
+ mboxes = <&gce1 12 CMDQ_THR_PRIO_1>,
+ <&gce1 13 CMDQ_THR_PRIO_1>,
+ <&gce1 14 CMDQ_THR_PRIO_1>,
+ <&gce1 21 CMDQ_THR_PRIO_1>,
+ <&gce1 22 CMDQ_THR_PRIO_1>;
+ #dma-cells = <1>;
+ };
+
+ display@14002000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ reg = <0 0x14002000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
+ };
+
+ display@14003000 {
+ compatible = "mediatek,mt8195-mdp3-stitch";
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_STITCH>;
+ };
+
+ display@14004000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
+ };
+
+ display@14005000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ reg = <0 0x14005000 0 0x1000>;
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ display@14006000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14006000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
+ };
+
+ display@14007000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ reg = <0 0x14007000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
+ };
+
+ display@14008000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ reg = <0 0x14008000 0 0x1000>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ display@14009000 {
+ compatible = "mediatek,mt8195-mdp3-ovl";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ iommus = <&iommu_vpp M4U_PORT_L4_MDP_OVL>;
+ };
+
+ display@1400a000 {
+ compatible = "mediatek,mt8195-mdp3-pad";
+ reg = <0 0x1400a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_PADDING>;
+ };
+
+ display@1400b000 {
+ compatible = "mediatek,mt8195-mdp3-tcc";
+ reg = <0 0x1400b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
+ };
+
+ dma-controller@1400c000 {
+ compatible = "mediatek,mt8183-mdp3-wrot";
+ reg = <0 0x1400c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
+ iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ #dma-cells = <1>;
+ };
+
mutex@1400f000 {
compatible = "mediatek,mt8195-vpp-mutex";
reg = <0 0x1400f000 0 0x1000>;
@@ -2107,6 +2215,286 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
+ display@14f06000 {
+ compatible = "mediatek,mt8195-mdp3-split";
+ reg = <0 0x14f06000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>,
+ <&vppsys1 CLK_VPP1_HDMI_META>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f07000 {
+ compatible = "mediatek,mt8195-mdp3-tcc";
+ reg = <0 0x14f07000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>;
+ };
+
+ dma-controller@14f08000 {
+ compatible = "mediatek,mt8195-mdp3-rdma";
+ reg = <0 0x14f08000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>;
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
+ dma-controller@14f09000 {
+ compatible = "mediatek,mt8195-mdp3-rdma";
+ reg = <0 0x14f09000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>;
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
+ dma-controller@14f0a000 {
+ compatible = "mediatek,mt8195-mdp3-rdma";
+ reg = <0 0x14f0a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>;
+ iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
+ display@14f0b000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ reg = <0 0x14f0b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>;
+ };
+
+ display@14f0c000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ reg = <0 0x14f0c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
+ };
+
+ display@14f0d000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ reg = <0 0x14f0d000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
+ };
+
+ display@14f0e000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ reg = <0 0x14f0e000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>;
+ };
+
+ display@14f0f000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ reg = <0 0x14f0f000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
+ };
+
+ display@14f10000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ reg = <0 0x14f10000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
+ };
+
+ display@14f11000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ reg = <0 0x14f11000 0 0x1000>;
+ interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f12000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ reg = <0 0x14f12000 0 0x1000>;
+ interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f13000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ reg = <0 0x14f13000 0 0x1000>;
+ interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f14000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14f14000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>;
+ };
+
+ display@14f15000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14f15000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
+ };
+
+ display@14f16000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ reg = <0 0x14f16000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
+ };
+
+ display@14f17000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ reg = <0 0x14f17000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>;
+ };
+
+ display@14f18000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ reg = <0 0x14f18000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
+ };
+
+ display@14f19000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ reg = <0 0x14f19000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
+ };
+
+ display@14f1a000 {
+ compatible = "mediatek,mt8195-mdp3-merge";
+ reg = <0 0x14f1a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f1b000 {
+ compatible = "mediatek,mt8195-mdp3-merge";
+ reg = <0 0x14f1b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f1c000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ reg = <0 0x14f1c000 0 0x1000>;
+ interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f1d000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ reg = <0 0x14f1d000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>;
+ interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f1e000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ reg = <0 0x14f1e000 0 0x1000>;
+ interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ display@14f1f000 {
+ compatible = "mediatek,mt8195-mdp3-ovl";
+ reg = <0 0x14f1f000 0 0x1000>;
+ interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>;
+ };
+
+ display@14f20000 {
+ compatible = "mediatek,mt8195-mdp3-pad";
+ reg = <0 0x14f20000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>;
+ };
+
+ display@14f21000 {
+ compatible = "mediatek,mt8195-mdp3-pad";
+ reg = <0 0x14f21000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
+ };
+
+ display@14f22000 {
+ compatible = "mediatek,mt8195-mdp3-pad";
+ reg = <0 0x14f22000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
+ };
+
+ dma-controller@14f23000 {
+ compatible = "mediatek,mt8183-mdp3-wrot";
+ reg = <0 0x14f23000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>;
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
+ dma-controller@14f24000 {
+ compatible = "mediatek,mt8183-mdp3-wrot";
+ reg = <0 0x14f24000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
+ dma-controller@14f25000 {
+ compatible = "mediatek,mt8183-mdp3-wrot";
+ reg = <0 0x14f25000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
+ iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ #dma-cells = <1>;
+ };
+
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8195-imgsys";
reg = <0 0x15000000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v6 2/2] arm64: dts: mediatek: mt8195: add MDP3 nodes
2023-09-22 6:50 ` [PATCH v6 2/2] arm64: dts: mediatek: mt8195: add MDP3 nodes Moudy Ho
@ 2023-09-22 8:29 ` AngeloGioacchino Del Regno
2023-09-27 9:02 ` Moudy Ho (何宗原)
0 siblings, 1 reply; 6+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-09-22 8:29 UTC (permalink / raw)
To: Moudy Ho, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Matthias Brugger
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mediatek
Il 22/09/23 08:50, Moudy Ho ha scritto:
> Add device nodes for Media Data Path 3 (MDP3) modules.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 388 +++++++++++++++++++++++
> 1 file changed, 388 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 4dbbf8fdab75..cf61ba7b8956 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1960,6 +1960,114 @@
> #clock-cells = <1>;
> };
>
..snip..
> +
> + display@14006000 {
> + compatible = "mediatek,mt8183-mdp3-rsz";
Please always add a SoC-specific compatible (both here and in bindings).
compatible = "medaitek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
> + reg = <0 0x14006000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
> + <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
> + };
> +
..snip..
> +
> + dma-controller@1400c000 {
> + compatible = "mediatek,mt8183-mdp3-wrot";
same here
> + reg = <0 0x1400c000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
> + <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>;
> + clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
> + iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
> + #dma-cells = <1>;
> + };
> +
> mutex@1400f000 {
> compatible = "mediatek,mt8195-vpp-mutex";
> reg = <0 0x1400f000 0 0x1000>;
> @@ -2107,6 +2215,286 @@
> power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> };
>
..snip..
> +
> + display@14f14000 {
> + compatible = "mediatek,mt8183-mdp3-rsz";
and here
> + reg = <0 0x14f14000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>;
> + };
> +
> + display@14f15000 {
> + compatible = "mediatek,mt8183-mdp3-rsz";
...and here
> + reg = <0 0x14f15000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
> + };
> +
> + display@14f16000 {
> + compatible = "mediatek,mt8183-mdp3-rsz";
......and here.
> + reg = <0 0x14f16000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
> + };
> +
..snip..
> +
> + dma-controller@14f23000 {
> + compatible = "mediatek,mt8183-mdp3-wrot";
...again... and for the other two occurrences of wrot as well.
Apart from that, looks good.
Regards,
Angelo
> + reg = <0 0x14f23000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>;
> + iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + #dma-cells = <1>;
> + };
> +
> + dma-controller@14f24000 {
> + compatible = "mediatek,mt8183-mdp3-wrot";
> + reg = <0 0x14f24000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
> + iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + #dma-cells = <1>;
> + };
> +
> + dma-controller@14f25000 {
> + compatible = "mediatek,mt8183-mdp3-wrot";
> + reg = <0 0x14f25000 0 0x1000>;
> + mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
> + <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
> + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
> + iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
> + #dma-cells = <1>;
> + };
> +
> imgsys: clock-controller@15000000 {
> compatible = "mediatek,mt8195-imgsys";
> reg = <0 0x15000000 0 0x1000>;
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v6 1/2] arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes
2023-09-22 6:50 ` [PATCH v6 1/2] arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes Moudy Ho
@ 2023-09-22 8:29 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 6+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-09-22 8:29 UTC (permalink / raw)
To: Moudy Ho, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Matthias Brugger
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mediatek
Il 22/09/23 08:50, Moudy Ho ha scritto:
> In order to generalize the node names, the DMA-related nodes
> corresponding to MT8183 MDP3 need to be corrected.
>
> Fixes: 60a2fb8d202a ("arm64: dts: mt8183: add MediaTek MDP3 nodes")
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v6 2/2] arm64: dts: mediatek: mt8195: add MDP3 nodes
2023-09-22 8:29 ` AngeloGioacchino Del Regno
@ 2023-09-27 9:02 ` Moudy Ho (何宗原)
0 siblings, 0 replies; 6+ messages in thread
From: Moudy Ho (何宗原) @ 2023-09-27 9:02 UTC (permalink / raw)
To: matthias.bgg, angelogioacchino.delregno, robh+dt,
krzysztof.kozlowski+dt, conor+dt
Cc: linux-arm-kernel, linux-kernel, linux-mediatek, devicetree
On Fri, 2023-09-22 at 10:29 +0200, AngeloGioacchino Del Regno wrote:
> Il 22/09/23 08:50, Moudy Ho ha scritto:
> > Add device nodes for Media Data Path 3 (MDP3) modules.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 388
> > +++++++++++++++++++++++
> > 1 file changed, 388 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index 4dbbf8fdab75..cf61ba7b8956 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -1960,6 +1960,114 @@
> > #clock-cells = <1>;
> > };
> >
>
> ..snip..
>
> > +
> > + display@14006000 {
> > + compatible = "mediatek,mt8183-mdp3-rsz";
>
> Please always add a SoC-specific compatible (both here and in
> bindings).
>
> compatible = "medaitek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
>
> > + reg = <0 0x14006000 0 0x1000>;
> > + mediatek,gce-client-reg = <&gce1
> > SUBSYS_1400XXXX 0x6000 0x1000>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
> > + <CMDQ_EVENT_VPP0_MDP_RSZ_
> > FRAME_DONE>;
> > + clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
> > + };
> > +
>
> ..snip..
>
> > +
> > + dma-controller@1400c000 {
> > + compatible = "mediatek,mt8183-mdp3-wrot";
>
> same here
>
> > + reg = <0 0x1400c000 0 0x1000>;
> > + mediatek,gce-client-reg = <&gce1
> > SUBSYS_1400XXXX 0xc000 0x1000>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
> > + <CMDQ_EVENT_VPP0_MDP_WROT
> > _VIDO_WDONE>;
> > + clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
> > + iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
> > + power-domains = <&spm
> > MT8195_POWER_DOMAIN_VPPSYS0>;
> > + #dma-cells = <1>;
> > + };
> > +
> > mutex@1400f000 {
> > compatible = "mediatek,mt8195-vpp-mutex";
> > reg = <0 0x1400f000 0 0x1000>;
> > @@ -2107,6 +2215,286 @@
> > power-domains = <&spm
> > MT8195_POWER_DOMAIN_VPPSYS1>;
> > };
> >
>
> ..snip..
>
> > +
> > + display@14f14000 {
> > + compatible = "mediatek,mt8183-mdp3-rsz";
>
> and here
>
> > + reg = <0 0x14f14000 0 0x1000>;
> > + mediatek,gce-client-reg = <&gce1
> > SUBSYS_14f1XXXX 0x4000 0x1000>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>,
> > + <CMDQ_EVENT_VPP1_SVPP1_MD
> > P_RSZ_FRAME_DONE>;
> > + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>;
> > + };
> > +
> > + display@14f15000 {
> > + compatible = "mediatek,mt8183-mdp3-rsz";
>
> ...and here
>
> > + reg = <0 0x14f15000 0 0x1000>;
> > + mediatek,gce-client-reg = <&gce1
> > SUBSYS_14f1XXXX 0x5000 0x1000>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>,
> > + <CMDQ_EVENT_VPP1_SVPP2_MD
> > P_RSZ_FRAME_DONE>;
> > + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>;
> > + };
> > +
> > + display@14f16000 {
> > + compatible = "mediatek,mt8183-mdp3-rsz";
>
> ......and here.
>
> > + reg = <0 0x14f16000 0 0x1000>;
> > + mediatek,gce-client-reg = <&gce1
> > SUBSYS_14f1XXXX 0x6000 0x1000>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>,
> > + <CMDQ_EVENT_VPP1_SVPP3_MD
> > P_RSZ_FRAME_DONE>;
> > + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>;
> > + };
> > +
>
> ..snip..
>
> > +
> > + dma-controller@14f23000 {
> > + compatible = "mediatek,mt8183-mdp3-wrot";
>
> ...again... and for the other two occurrences of wrot as well.
>
> Apart from that, looks good.
>
> Regards,
> Angelo
>
Hi Angelo,
Thank you for the advice, I will include the appropriate compatible
names to the specified locations.
Sincerely,
Moudy
> > + reg = <0 0x14f23000 0 0x1000>;
> > + mediatek,gce-client-reg = <&gce1
> > SUBSYS_14f2XXXX 0x3000 0x1000>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
> > + <CMDQ_EVENT_VPP1_SVPP1_MD
> > P_WROT_FRAME_DONE>;
> > + clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>;
> > + iommus = <&iommu_vdo
> > M4U_PORT_L5_SVPP1_MDP_WROT>;
> > + power-domains = <&spm
> > MT8195_POWER_DOMAIN_VPPSYS1>;
> > + #dma-cells = <1>;
> > + };
> > +
> > + dma-controller@14f24000 {
> > + compatible = "mediatek,mt8183-mdp3-wrot";
> > + reg = <0 0x14f24000 0 0x1000>;
> > + mediatek,gce-client-reg = <&gce1
> > SUBSYS_14f2XXXX 0x4000 0x1000>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
> > + <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT
> > _FRAME_DONE>;
> > + clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
> > + iommus = <&iommu_vdo
> > M4U_PORT_L5_SVPP2_MDP_WROT>;
> > + power-domains = <&spm
> > MT8195_POWER_DOMAIN_VPPSYS1>;
> > + #dma-cells = <1>;
> > + };
> > +
> > + dma-controller@14f25000 {
> > + compatible = "mediatek,mt8183-mdp3-wrot";
> > + reg = <0 0x14f25000 0 0x1000>;
> > + mediatek,gce-client-reg = <&gce1
> > SUBSYS_14f2XXXX 0x5000 0x1000>;
> > + mediatek,gce-events =
> > <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
> > + <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT
> > _FRAME_DONE>;
> > + clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
> > + iommus = <&iommu_vpp
> > M4U_PORT_L6_SVPP3_MDP_WROT>;
> > + power-domains = <&spm
> > MT8195_POWER_DOMAIN_VPPSYS1>;
> > + #dma-cells = <1>;
> > + };
> > +
> > imgsys: clock-controller@15000000 {
> > compatible = "mediatek,mt8195-imgsys";
> > reg = <0 0x15000000 0 0x1000>;
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-09-27 9:23 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-09-22 6:50 [PATCH v6 0/2] Add support for MT8195 MDP3 Moudy Ho
2023-09-22 6:50 ` [PATCH v6 1/2] arm64: dts: mediatek: mt8183: correct MDP3 DMA-related nodes Moudy Ho
2023-09-22 8:29 ` AngeloGioacchino Del Regno
2023-09-22 6:50 ` [PATCH v6 2/2] arm64: dts: mediatek: mt8195: add MDP3 nodes Moudy Ho
2023-09-22 8:29 ` AngeloGioacchino Del Regno
2023-09-27 9:02 ` Moudy Ho (何宗原)
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