Re: [PATCH v3 1/4] clk: mediatek: Export PLL operations symbols

["Johnson Wang (王聖鑫)" <Johnson.Wang@mediatek.com>]

On Thu, 2022-09-29 at 15:07 +0200, AngeloGioacchino Del Regno wrote:
> Il 29/09/22 13:46, Johnson Wang ha scritto:
> > Export PLL operations and register functions for different type
> > of clock driver used.
> > 
> > Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
> > Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com>
> > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > ---
> >   drivers/clk/mediatek/clk-pll.c | 84 ++++++++++++++---------------
> > -----
> >   drivers/clk/mediatek/clk-pll.h | 56 +++++++++++++++++++++++
> >   2 files changed, 90 insertions(+), 50 deletions(-)
> > 
> > diff --git a/drivers/clk/mediatek/clk-pll.c
> > b/drivers/clk/mediatek/clk-pll.c
> > index 54e6cfd29dfc..a4eca5fd539c 100644
> > --- a/drivers/clk/mediatek/clk-pll.c
> > +++ b/drivers/clk/mediatek/clk-pll.c
> > @@ -27,37 +27,10 @@
> >   
> >   #define AUDPLL_TUNER_EN		BIT(31)
> >   
> > -#define POSTDIV_MASK		0x7
> > -
> >   /* default 7 bits integer, can be overridden with pcwibits. */
> >   #define INTEGER_BITS		7
> >   
> > -/*
> > - * MediaTek PLLs are configured through their pcw value. The pcw
> > value describes
> > - * a divider in the PLL feedback loop which consists of 7 bits for
> > the integer
> > - * part and the remaining bits (if present) for the fractional
> > part. Also they
> > - * have a 3 bit power-of-two post divider.
> > - */
> > -
> > -struct mtk_clk_pll {
> > -	struct clk_hw	hw;
> > -	void __iomem	*base_addr;
> > -	void __iomem	*pd_addr;
> > -	void __iomem	*pwr_addr;
> > -	void __iomem	*tuner_addr;
> > -	void __iomem	*tuner_en_addr;
> > -	void __iomem	*pcw_addr;
> > -	void __iomem	*pcw_chg_addr;
> > -	void __iomem	*en_addr;
> > -	const struct mtk_pll_data *data;
> > -};
> > -
> > -static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw
> > *hw)
> > -{
> > -	return container_of(hw, struct mtk_clk_pll, hw);
> > -}
> > -
> > -static int mtk_pll_is_prepared(struct clk_hw *hw)
> > +int mtk_pll_is_prepared(struct clk_hw *hw)
> >   {
> >   	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
> >   
> > @@ -161,8 +134,8 @@ static void mtk_pll_set_rate_regs(struct
> > mtk_clk_pll *pll, u32 pcw,
> >    * @fin:	The input frequency
> >    *
> >    */
> > -static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw,
> > u32 *postdiv,
> > -		u32 freq, u32 fin)
> > +void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32
> > *postdiv,
> > +			 u32 freq, u32 fin)
> >   {
> >   	unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000
> > * MHZ);
> >   	const struct mtk_pll_div_table *div_table = pll->data-
> > >div_table;
> > @@ -198,8 +171,8 @@ static void mtk_pll_calc_values(struct
> > mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
> >   	*pcw = (u32)_pcw;
> >   }
> >   
> > -static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> > -		unsigned long parent_rate)
> > +int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> > +		     unsigned long parent_rate)
> >   {
> >   	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
> >   	u32 pcw = 0;
> > @@ -211,8 +184,7 @@ static int mtk_pll_set_rate(struct clk_hw *hw,
> > unsigned long rate,
> >   	return 0;
> >   }
> >   
> > -static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
> > -		unsigned long parent_rate)
> > +unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long
> > parent_rate)
> >   {
> >   	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
> >   	u32 postdiv;
> > @@ -227,8 +199,8 @@ static unsigned long mtk_pll_recalc_rate(struct
> > clk_hw *hw,
> >   	return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
> >   }
> >   
> > -static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long
> > rate,
> > -		unsigned long *prate)
> > +long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> > +			unsigned long *prate)
> >   {
> >   	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
> >   	u32 pcw = 0;
> > @@ -239,7 +211,7 @@ static long mtk_pll_round_rate(struct clk_hw
> > *hw, unsigned long rate,
> >   	return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
> >   }
> >   
> > -static int mtk_pll_prepare(struct clk_hw *hw)
> > +int mtk_pll_prepare(struct clk_hw *hw)
> >   {
> >   	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
> >   	u32 r;
> > @@ -273,7 +245,7 @@ static int mtk_pll_prepare(struct clk_hw *hw)
> >   	return 0;
> >   }
> >   
> > -static void mtk_pll_unprepare(struct clk_hw *hw)
> > +void mtk_pll_unprepare(struct clk_hw *hw)
> >   {
> >   	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
> >   	u32 r;
> > @@ -301,7 +273,7 @@ static void mtk_pll_unprepare(struct clk_hw
> > *hw)
> >   	writel(r, pll->pwr_addr);
> >   }
> >   
> > -static const struct clk_ops mtk_pll_ops = {
> > +const struct clk_ops mtk_pll_ops = {
> >   	.is_prepared	= mtk_pll_is_prepared,
> >   	.prepare	= mtk_pll_prepare,
> >   	.unprepare	= mtk_pll_unprepare,
> > @@ -310,18 +282,15 @@ static const struct clk_ops mtk_pll_ops = {
> >   	.set_rate	= mtk_pll_set_rate,
> >   };
> >   
> > -static struct clk_hw *mtk_clk_register_pll(const struct
> > mtk_pll_data *data,
> > -		void __iomem *base)
> > +struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
> > +					const struct mtk_pll_data
> > *data,
> > +					void __iomem *base,
> > +					const struct clk_ops *pll_ops)
> >   {
> > -	struct mtk_clk_pll *pll;
> >   	struct clk_init_data init = {};
> >   	int ret;
> >   	const char *parent_name = "clk26m";
> >   
> > -	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> > -	if (!pll)
> > -		return ERR_PTR(-ENOMEM);
> > -
> >   	pll->base_addr = base + data->reg;
> >   	pll->pwr_addr = base + data->pwr_reg;
> >   	pll->pd_addr = base + data->pd_reg;
> > @@ -343,7 +312,7 @@ static struct clk_hw
> > *mtk_clk_register_pll(const struct mtk_pll_data *data,
> >   
> >   	init.name = data->name;
> >   	init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
> > -	init.ops = &mtk_pll_ops;
> > +	init.ops = pll_ops;
> >   	if (data->parent_name)
> >   		init.parent_names = &data->parent_name;
> >   	else
> > @@ -360,7 +329,22 @@ static struct clk_hw
> > *mtk_clk_register_pll(const struct mtk_pll_data *data,
> >   	return &pll->hw;
> >   }
> >   
> > -static void mtk_clk_unregister_pll(struct clk_hw *hw)
> > +struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data
> > *data,
> > +				    void __iomem *base)
> > +{
> > +	struct mtk_clk_pll *pll;
> > +	struct clk_hw *hw;
> > +
> > +	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> > +	if (!pll)
> > +		return ERR_PTR(-ENOMEM);
> > +
> > +	hw = mtk_clk_register_pll_ops(pll, data, base, &mtk_pll_ops);
> > +
> > +	return hw;
> > +}
> > +
> > +void mtk_clk_unregister_pll(struct clk_hw *hw)
> >   {
> >   	struct mtk_clk_pll *pll;
> >   
> > @@ -423,8 +407,8 @@ int mtk_clk_register_plls(struct device_node
> > *node,
> >   }
> >   EXPORT_SYMBOL_GPL(mtk_clk_register_plls);
> >   
> > -static __iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
> > -					  const struct mtk_pll_data
> > *data)
> > +__iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
> > +				   const struct mtk_pll_data *data)
> >   {
> >   	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
> >   
> > diff --git a/drivers/clk/mediatek/clk-pll.h
> > b/drivers/clk/mediatek/clk-pll.h
> > index fe3199715688..e87ab08eea9b 100644
> > --- a/drivers/clk/mediatek/clk-pll.h
> > +++ b/drivers/clk/mediatek/clk-pll.h
> > @@ -7,6 +7,7 @@
> >   #ifndef __DRV_CLK_MTK_PLL_H
> >   #define __DRV_CLK_MTK_PLL_H
> >   
> > +#include <linux/clk-provider.h>
> >   #include <linux/types.h>
> >   
> >   struct clk_ops;
> > @@ -20,6 +21,7 @@ struct mtk_pll_div_table {
> >   
> >   #define HAVE_RST_BAR	BIT(0)
> >   #define PLL_AO		BIT(1)
> > +#define POSTDIV_MASK	0x7
> 
> While moving this, can you please also fixup declaring this mask as
> GENMASK()?
> 
> #define POSTDIV_MASK	GENMASK(2, 0)
> 
> >   
> >   struct mtk_pll_data {
> >   	int id;
> > @@ -48,10 +50,64 @@ struct mtk_pll_data {
> >   	u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
> >   };
> >   
> > +/*
> > + * MediaTek PLLs are configured through their pcw value. The pcw
> > value describes
> > + * a divider in the PLL feedback loop which consists of 7 bits for
> > the integer
> > + * part and the remaining bits (if present) for the fractional
> > part. Also they
> > + * have a 3 bit power-of-two post divider.
> > + */
> > +
> > +struct mtk_clk_pll {
> > +	struct clk_hw	hw;
> > +	void __iomem	*base_addr;
> > +	void __iomem	*pd_addr;
> > +	void __iomem	*pwr_addr;
> > +	void __iomem	*tuner_addr;
> > +	void __iomem	*tuner_en_addr;
> > +	void __iomem	*pcw_addr;
> > +	void __iomem	*pcw_chg_addr;
> > +	void __iomem	*en_addr;
> > +	const struct mtk_pll_data *data;
> > +};
> > +
> > +
> 
> Please drop this extra newline.
> 
> Thanks,
> Angelo

Hi Angelo,

Thanks for your suggestion.
I will improve this in the next version.

BRs,
Johnson Wang