From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
To: "Nancy.Lin" <nancy.lin@mediatek.com>
Cc: CK Hu <ck.hu@mediatek.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
"jason-jh . lin" <jason-jh.lin@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
DRI Development <dri-devel@lists.freedesktop.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
DTML <devicetree@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
singo.chang@mediatek.com,
srv_heupstream <srv_heupstream@mediatek.com>
Subject: Re: [PATCH v5 08/16] soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1
Date: Wed, 8 Sep 2021 00:29:55 +0800 [thread overview]
Message-ID: <CAAOTY_8aQkx55C=mqK-4bULpG_biHkq4brBF2SDdtbpnhP3Rvw@mail.gmail.com> (raw)
In-Reply-To: <20210906071539.12953-9-nancy.lin@mediatek.com>
Hi, Nancy:
Nancy.Lin <nancy.lin@mediatek.com> 於 2021年9月6日 週一 下午3:15寫道:
>
> Add cmdq support for mtk-mmsys config API.
> The mmsys config register settings need to take effect with the other
> HW settings(like OVL_ADAPTOR...) at the same vblanking time.
>
> If we use CPU to write the mmsys reg, we can't guarantee all the
> settings can be written in the same vblanking time.
> Cmdq is used for this purpose. We prepare all the related HW settings
> in one cmdq packet. The first command in the packet is "wait stream done",
> and then following with all the HW settings. After the cmdq packet is
> flush to GCE HW. The GCE waits for the "stream done event" to coming
> and then starts flushing all the HW settings. This can guarantee all
> the settings flush in the same vblanking.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-mmsys.c | 28 +++++++++++++++++++++-----
> include/linux/soc/mediatek/mtk-mmsys.h | 6 +++++-
> 2 files changed, 28 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 3a38b8269c71..060065501b8a 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -81,6 +81,7 @@ struct mtk_mmsys {
> const struct mtk_mmsys_driver_data *data;
> spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> struct reset_controller_dev rcdev;
> + struct cmdq_client_reg cmdq_base;
> };
>
> void mtk_mmsys_ddp_connect(struct device *dev,
> @@ -174,7 +175,7 @@ static const struct reset_control_ops mtk_mmsys_reset_ops = {
> };
>
> void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
> - u32 id, u32 val)
> + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt)
> {
> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> const struct mtk_mmsys_config *mmsys_config = mmsys->data->config;
> @@ -197,10 +198,20 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
> mask = mmsys_config[i].mask;
> reg_val = val << mmsys_config[i].shift;
>
> - u32 tmp = readl(mmsys->regs + offset);
> -
> - tmp = (tmp & ~mask) | reg_val;
> - writel(tmp, mmsys->regs + offset);
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + if (cmdq_pkt && mmsys->cmdq_base.size) {
> + cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
> + mmsys->cmdq_base.offset + offset, reg_val,
> + mask);
> + } else {
> +#endif
> + u32 tmp = readl(mmsys->regs + offset);
> +
> + tmp = (tmp & ~mask) | reg_val;
> + writel(tmp, mmsys->regs + offset);
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + }
> +#endif
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
>
> @@ -236,6 +247,13 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> }
>
> mmsys->data = of_device_get_match_data(&pdev->dev);
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
Define mediatek,gce-client-reg in binding document first.
Regards,
Chun-Kuang.
> + if (ret)
> + dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> +#endif
> +
> platform_set_drvdata(pdev, mmsys);
>
> clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index ef2a6d9a834b..9705d242849a 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -6,6 +6,10 @@
> #ifndef __MTK_MMSYS_H
> #define __MTK_MMSYS_H
>
> +#include <linux/mailbox_controller.h>
> +#include <linux/mailbox/mtk-cmdq-mailbox.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> enum mtk_ddp_comp_id;
> struct device;
>
> @@ -75,6 +79,6 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> enum mtk_ddp_comp_id next);
>
> void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config,
> - u32 id, u32 val);
> + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
>
> #endif /* __MTK_MMSYS_H */
> --
> 2.18.0
>
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next prev parent reply other threads:[~2021-09-07 16:30 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-06 7:15 [PATCH v5 00/16] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 01/16] dt-bindings: mediatek: add vdosys1 RDMA definition " Nancy.Lin
2021-09-06 23:42 ` Chun-Kuang Hu
2021-09-16 2:56 ` Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 02/16] dt-bindings: mediatek: add vdosys1 MERGE property " Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 03/16] dt-bindings: mediatek: add ethdr definition " Nancy.Lin
2021-09-07 15:58 ` Chun-Kuang Hu
2021-09-06 7:15 ` [PATCH v5 04/16] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
2021-09-07 16:06 ` Chun-Kuang Hu
2021-09-16 3:05 ` Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 05/16] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 06/16] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 07/16] soc: mediatek: add mtk-mmsys config API " Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 08/16] soc: mediatek: add cmdq support of " Nancy.Lin
2021-09-07 16:29 ` Chun-Kuang Hu [this message]
2021-09-16 3:07 ` Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1 Nancy.Lin
2021-09-06 7:29 ` Philipp Zabel
2021-09-16 2:51 ` Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 10/16] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 11/16] drm/mediatek: add display MDP RDMA support for MT8195 Nancy.Lin
2021-09-08 23:54 ` Chun-Kuang Hu
2021-09-16 3:18 ` Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 12/16] drm/mediatek: add display merge api " Nancy.Lin
2021-09-09 23:29 ` Chun-Kuang Hu
2021-09-06 7:15 ` [PATCH v5 13/16] drm/mediatek: add ETHDR " Nancy.Lin
2021-09-22 0:09 ` Chun-Kuang Hu
2021-09-24 4:59 ` Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 14/16] drm/mediatek: add ovl_adaptor " Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 15/16] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support Nancy.Lin
2021-09-29 0:03 ` Chun-Kuang Hu
2021-10-04 5:49 ` Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 16/16] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195 Nancy.Lin
2021-09-18 8:34 ` [PATCH v5 00/16] Add MediaTek SoC DRM (vdosys1) support for mt8195 Markus Schneider-Pargmann
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