From: Philipp Zabel <p.zabel@pengutronix.de>
To: "Nancy.Lin" <nancy.lin@mediatek.com>, CK Hu <ck.hu@mediatek.com>
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
"jason-jh . lin" <jason-jh.lin@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
dri-devel@lists.freedesktop.org,
linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, singo.chang@mediatek.com,
srv_heupstream@mediatek.com
Subject: Re: [PATCH v5 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1
Date: Mon, 06 Sep 2021 09:29:14 +0200 [thread overview]
Message-ID: <d93c6866fb8a6e9bebf3b3ed6959e2c3abaf647d.camel@pengutronix.de> (raw)
In-Reply-To: <20210906071539.12953-10-nancy.lin@mediatek.com>
Hi Nancy,
On Mon, 2021-09-06 at 15:15 +0800, Nancy.Lin wrote:
> MT8195 vdosys1 has more than 32 reset bits and a different reset base
> than other chips. Modify mmsys for support 64 bit and different reset
> base.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 1 +
> drivers/soc/mediatek/mtk-mmsys.c | 15 ++++++++++++---
> drivers/soc/mediatek/mtk-mmsys.h | 1 +
> 3 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index 648baaec112b..f67801c42fd9 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -123,6 +123,7 @@
> #define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
> #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
>
> +#define MT8195_VDO1_SW0_RST_B 0x1d0
> #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> #define MT8195_VDO1_MERGE1_ASYNC_CFG_WD 0xe40
> #define MT8195_VDO1_MERGE2_ASYNC_CFG_WD 0xe50
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 060065501b8a..97cb26339ef6 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -18,6 +18,8 @@
> #include "mt8365-mmsys.h"
> #include "mt8195-mmsys.h"
>
> +#define MMSYS_SW_RESET_PER_REG 32
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .clk_driver = "clk-mt2701-mm",
> .routes = mmsys_default_routing_table,
> @@ -48,12 +50,14 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .clk_driver = "clk-mt8173-mm",
> .routes = mmsys_default_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_default_routing_table),
> + .sw_reset_start = MMSYS_SW0_RST_B,
> };
>
> static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .clk_driver = "clk-mt8183-mm",
> .routes = mmsys_mt8183_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> + .sw_reset_start = MMSYS_SW0_RST_B,
> };
>
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
> @@ -74,6 +78,7 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
> .config = mmsys_mt8195_config_table,
> .num_configs = ARRAY_SIZE(mmsys_mt8195_config_table),
> + .sw_reset_start = MT8195_VDO1_SW0_RST_B,
> };
>
> struct mtk_mmsys {
> @@ -126,19 +131,23 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l
> {
> struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev);
> unsigned long flags;
> + u32 offset;
> u32 reg;
> int i;
>
> + offset = (id / MMSYS_SW_RESET_PER_REG) * sizeof(u32);
> + id = id % MMSYS_SW_RESET_PER_REG;
> +
> spin_lock_irqsave(&mmsys->lock, flags);
>
> - reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B);
> + reg = readl_relaxed(mmsys->regs + mmsys->data->sw_reset_start + offset);
>
> if (assert)
> reg &= ~BIT(id);
> else
> reg |= BIT(id);
>
> - writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B);
> + writel_relaxed(reg, mmsys->regs + mmsys->data->sw_reset_start + offset);
>
> spin_unlock_irqrestore(&mmsys->lock, flags);
>
> @@ -237,7 +246,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> spin_lock_init(&mmsys->lock);
>
> mmsys->rcdev.owner = THIS_MODULE;
> - mmsys->rcdev.nr_resets = 32;
> + mmsys->rcdev.nr_resets = 64;
If only MT8195 vdosys1 has more than 32 reset bits, this should be kept
at 32 for the others.
regards
Philipp
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next prev parent reply other threads:[~2021-09-06 7:32 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-06 7:15 [PATCH v5 00/16] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 01/16] dt-bindings: mediatek: add vdosys1 RDMA definition " Nancy.Lin
2021-09-06 23:42 ` Chun-Kuang Hu
2021-09-16 2:56 ` Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 02/16] dt-bindings: mediatek: add vdosys1 MERGE property " Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 03/16] dt-bindings: mediatek: add ethdr definition " Nancy.Lin
2021-09-07 15:58 ` Chun-Kuang Hu
2021-09-06 7:15 ` [PATCH v5 04/16] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
2021-09-07 16:06 ` Chun-Kuang Hu
2021-09-16 3:05 ` Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 05/16] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 06/16] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 07/16] soc: mediatek: add mtk-mmsys config API " Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 08/16] soc: mediatek: add cmdq support of " Nancy.Lin
2021-09-07 16:29 ` Chun-Kuang Hu
2021-09-16 3:07 ` Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1 Nancy.Lin
2021-09-06 7:29 ` Philipp Zabel [this message]
2021-09-16 2:51 ` Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 10/16] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 11/16] drm/mediatek: add display MDP RDMA support for MT8195 Nancy.Lin
2021-09-08 23:54 ` Chun-Kuang Hu
2021-09-16 3:18 ` Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 12/16] drm/mediatek: add display merge api " Nancy.Lin
2021-09-09 23:29 ` Chun-Kuang Hu
2021-09-06 7:15 ` [PATCH v5 13/16] drm/mediatek: add ETHDR " Nancy.Lin
2021-09-22 0:09 ` Chun-Kuang Hu
2021-09-24 4:59 ` Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 14/16] drm/mediatek: add ovl_adaptor " Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 15/16] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support Nancy.Lin
2021-09-29 0:03 ` Chun-Kuang Hu
2021-10-04 5:49 ` Nancy.Lin
2021-09-06 7:15 ` [PATCH v5 16/16] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195 Nancy.Lin
2021-09-18 8:34 ` [PATCH v5 00/16] Add MediaTek SoC DRM (vdosys1) support for mt8195 Markus Schneider-Pargmann
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