From: Chen-Yu Tsai <wenst@chromium.org>
To: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>,
Rob Herring <robh+dt@kernel.org>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
LKML <linux-kernel@vger.kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
linux-clk@vger.kernel.org,
Devicetree List <devicetree@vger.kernel.org>,
srv_heupstream <srv_heupstream@mediatek.com>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: Re: [v2 02/24] clk: mediatek: Add dt-bindings of MT8195 clocks
Date: Wed, 25 Aug 2021 19:39:54 +0800 [thread overview]
Message-ID: <CAGXv+5Eb4ZiXZXURvoApSEk_myhNpEugOhr2DrzvkxGfDKJneg@mail.gmail.com> (raw)
In-Reply-To: <20210820111504.350-3-chun-jie.chen@mediatek.com>
On Fri, Aug 20, 2021 at 7:17 PM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 clock dt-bindings, include topckgen, apmixedsys,
> infracfg_ao, pericfg_ao and subsystem clocks.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> include/dt-bindings/clock/mt8195-clk.h | 864 +++++++++++++++++++++++++
> 1 file changed, 864 insertions(+)
> create mode 100644 include/dt-bindings/clock/mt8195-clk.h
>
> diff --git a/include/dt-bindings/clock/mt8195-clk.h b/include/dt-bindings/clock/mt8195-clk.h
> new file mode 100644
> index 000000000000..95cf812a0b37
> --- /dev/null
> +++ b/include/dt-bindings/clock/mt8195-clk.h
> @@ -0,0 +1,864 @@
[...]
> +/* WPESYS_VPP0 */
> +
> +#define CLK_WPE_VPP0_VECI 0
> +#define CLK_WPE_VPP0_VEC2I 1
> +#define CLK_WPE_VPP0_VEC3I 2
> +#define CLK_WPE_VPP0_WPEO 3
> +#define CLK_WPE_VPP0_MSKO 4
> +#define CLK_WPE_VPP0_VGEN 5
> +#define CLK_WPE_VPP0_EXT 6
> +#define CLK_WPE_VPP0_VFC 7
> +#define CLK_WPE_VPP0_CACH0_TOP 8
> +#define CLK_WPE_VPP0_CACH0_DMA 9
> +#define CLK_WPE_VPP0_CACH1_TOP 10
> +#define CLK_WPE_VPP0_CACH1_DMA 11
> +#define CLK_WPE_VPP0_CACH2_TOP 12
> +#define CLK_WPE_VPP0_CACH2_DMA 13
> +#define CLK_WPE_VPP0_CACH3_TOP 14
> +#define CLK_WPE_VPP0_CACH3_DMA 15
> +#define CLK_WPE_VPP0_PSP 16
> +#define CLK_WPE_VPP0_PSP2 17
> +#define CLK_WPE_VPP0_SYNC 18
> +#define CLK_WPE_VPP0_C24 19
> +#define CLK_WPE_VPP0_MDP_CROP 20
> +#define CLK_WPE_VPP0_ISP_CROP 21
> +#define CLK_WPE_VPP0_TOP 22
> +#define CLK_WPE_VPP0_NR_CLK 23
> +
> +/* WPESYS_VPP1 */
> +
> +#define CLK_WPE_VPP1_VECI 0
> +#define CLK_WPE_VPP1_VEC2I 1
> +#define CLK_WPE_VPP1_VEC3I 2
> +#define CLK_WPE_VPP1_WPEO 3
> +#define CLK_WPE_VPP1_MSKO 4
> +#define CLK_WPE_VPP1_VGEN 5
> +#define CLK_WPE_VPP1_EXT 6
> +#define CLK_WPE_VPP1_VFC 7
> +#define CLK_WPE_VPP1_CACH0_TOP 8
> +#define CLK_WPE_VPP1_CACH0_DMA 9
> +#define CLK_WPE_VPP1_CACH1_TOP 10
> +#define CLK_WPE_VPP1_CACH1_DMA 11
> +#define CLK_WPE_VPP1_CACH2_TOP 12
> +#define CLK_WPE_VPP1_CACH2_DMA 13
> +#define CLK_WPE_VPP1_CACH3_TOP 14
> +#define CLK_WPE_VPP1_CACH3_DMA 15
> +#define CLK_WPE_VPP1_PSP 16
> +#define CLK_WPE_VPP1_PSP2 17
> +#define CLK_WPE_VPP1_SYNC 18
> +#define CLK_WPE_VPP1_C24 19
> +#define CLK_WPE_VPP1_MDP_CROP 20
> +#define CLK_WPE_VPP1_ISP_CROP 21
> +#define CLK_WPE_VPP1_TOP 22
> +#define CLK_WPE_VPP1_NR_CLK 23
If WPE_VPP0 and WPE_VPP1 end up being identical hardware, then there's
no need to have two separate lists.
[...]
> +/* VENCSYS */
> +
> +#define CLK_VENC_LARB 0
> +#define CLK_VENC_VENC 1
> +#define CLK_VENC_JPGENC 2
> +#define CLK_VENC_JPGDEC 3
> +#define CLK_VENC_JPGDEC_C1 4
> +#define CLK_VENC_GALS 5
> +#define CLK_VENC_NR_CLK 6
> +
> +/* VENCSYS_CORE1 */
> +
> +#define CLK_VENC_CORE1_LARB 0
> +#define CLK_VENC_CORE1_VENC 1
> +#define CLK_VENC_CORE1_JPGENC 2
> +#define CLK_VENC_CORE1_JPGDEC 3
> +#define CLK_VENC_CORE1_JPGDEC_C1 4
> +#define CLK_VENC_CORE1_GALS 5
> +#define CLK_VENC_CORE1_NR_CLK 6
Same for VENC and VENC_CORE1.
ChenYu
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next prev parent reply other threads:[~2021-08-25 11:40 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-20 11:14 [v2 00/24] Mediatek MT8195 clock support Chun-Jie Chen
2021-08-20 11:14 ` [v2 01/24] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock Chun-Jie Chen
2021-08-23 6:53 ` Chen-Yu Tsai
2021-08-24 14:44 ` Rob Herring
2021-08-20 11:14 ` [v2 02/24] clk: mediatek: Add dt-bindings of MT8195 clocks Chun-Jie Chen
2021-08-24 15:17 ` Rob Herring
2021-08-25 11:39 ` Chen-Yu Tsai [this message]
2021-08-20 11:14 ` [v2 03/24] clk: mediatek: Fix corner case of tuner_en_reg Chun-Jie Chen
2021-08-20 11:14 ` [v2 04/24] clk: mediatek: Add API for clock resource recycle Chun-Jie Chen
2021-08-23 6:40 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 05/24] clk: mediatek: Fix resource leak in mtk_clk_simple_probe Chun-Jie Chen
2021-08-23 6:42 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 06/24] clk: mediatek: Add MT8195 apmixedsys clock support Chun-Jie Chen
2021-08-23 9:21 ` Chen-Yu Tsai
2021-08-23 9:56 ` Chen-Yu Tsai
2021-08-29 18:26 ` Stephen Boyd
2021-08-20 11:14 ` [v2 07/24] clk: mediatek: Add MT8195 topckgen " Chun-Jie Chen
2021-08-23 11:16 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 08/24] clk: mediatek: Add MT8195 peripheral " Chun-Jie Chen
2021-08-23 11:22 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 09/24] clk: mediatek: Add MT8195 infrastructure " Chun-Jie Chen
2021-08-23 11:32 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 10/24] clk: mediatek: Add MT8195 camsys " Chun-Jie Chen
2021-08-20 11:14 ` [v2 11/24] clk: mediatek: Add MT8195 ccusys " Chun-Jie Chen
2021-08-23 12:13 ` Chen-Yu Tsai
2021-09-10 10:52 ` Chun-Jie Chen
2021-08-20 11:14 ` [v2 12/24] clk: mediatek: Add MT8195 imgsys " Chun-Jie Chen
2021-08-20 11:14 ` [v2 13/24] clk: mediatek: Add MT8195 ipesys " Chun-Jie Chen
2021-08-23 12:20 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 14/24] clk: mediatek: Add MT8195 mfgcfg " Chun-Jie Chen
2021-08-23 12:02 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 15/24] clk: mediatek: Add MT8195 scp adsp " Chun-Jie Chen
2021-08-23 12:08 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 16/24] clk: mediatek: Add MT8195 vdecsys " Chun-Jie Chen
2021-08-23 12:21 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 17/24] clk: mediatek: Add MT8195 vdosys0 " Chun-Jie Chen
2021-08-25 10:52 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 18/24] clk: mediatek: Add MT8195 vdosys1 " Chun-Jie Chen
2021-08-25 10:55 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 19/24] clk: mediatek: Add MT8195 vencsys " Chun-Jie Chen
2021-08-25 11:03 ` Chen-Yu Tsai
2021-09-10 11:09 ` Chun-Jie Chen
2021-09-14 3:47 ` Chen-Yu Tsai
2021-08-20 11:15 ` [v2 20/24] clk: mediatek: Add MT8195 vppsys0 " Chun-Jie Chen
2021-08-25 10:59 ` Chen-Yu Tsai
2021-08-20 11:15 ` [v2 21/24] clk: mediatek: Add MT8195 vppsys1 " Chun-Jie Chen
2021-08-25 11:00 ` Chen-Yu Tsai
2021-08-20 11:15 ` [v2 22/24] clk: mediatek: Add MT8195 wpesys " Chun-Jie Chen
2021-08-25 11:34 ` Chen-Yu Tsai
2021-09-10 11:04 ` Chun-Jie Chen
2021-08-20 11:15 ` [v2 23/24] clk: mediatek: Add MT8195 imp i2c wrapper " Chun-Jie Chen
2021-08-23 12:50 ` Chen-Yu Tsai
2021-08-20 11:15 ` [v2 24/24] clk: mediatek: Add MT8195 apusys " Chun-Jie Chen
2021-08-23 12:48 ` Chen-Yu Tsai
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