From: Chen-Yu Tsai <wenst@chromium.org>
To: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>,
Rob Herring <robh+dt@kernel.org>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
LKML <linux-kernel@vger.kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
linux-clk@vger.kernel.org,
Devicetree List <devicetree@vger.kernel.org>,
srv_heupstream <srv_heupstream@mediatek.com>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: Re: [v2 14/24] clk: mediatek: Add MT8195 mfgcfg clock support
Date: Mon, 23 Aug 2021 20:02:32 +0800 [thread overview]
Message-ID: <CAGXv+5H-NqZYeGUwsZQnu45DQLn=JX=4zrpuGHZ4ArC7p3Ks=Q@mail.gmail.com> (raw)
In-Reply-To: <20210820111504.350-15-chun-jie.chen@mediatek.com>
On Fri, Aug 20, 2021 at 7:26 PM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 mfg clock controller which provides clock gate
> control for Main Frame Graphic.
I think it would be easier to understand if it just said GPU instead. Or
it could write:
... for Main Frame Graphic, aka integrated GPU.
Try to use more generic terms. The idea is for people with at least some
basic knowledge to be able to understand.
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> drivers/clk/mediatek/Makefile | 2 +-
> drivers/clk/mediatek/clk-mt8195-mfg.c | 47 +++++++++++++++++++++++++++
> 2 files changed, 48 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mt8195-mfg.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 84d315a6b3e4..042db433245a 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -81,6 +81,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_SCP_ADSP) += clk-mt8192-scp_adsp.o
> obj-$(CONFIG_COMMON_CLK_MT8192_VDECSYS) += clk-mt8192-vdec.o
> obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
> obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o clk-mt8195-cam.o \
> - clk-mt8195-ccu.o clk-mt8195-img.o clk-mt8195-ipe.o
> + clk-mt8195-ccu.o clk-mt8195-img.o clk-mt8195-ipe.o clk-mt8195-mfg.o
Wrap line, please.
Regards
ChenYu
> obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
> obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-mfg.c b/drivers/clk/mediatek/clk-mt8195-mfg.c
> new file mode 100644
> index 000000000000..0a81fe1fe50e
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-mfg.c
> @@ -0,0 +1,47 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +static const struct mtk_gate_regs mfg_cg_regs = {
> + .set_ofs = 0x4,
> + .clr_ofs = 0x8,
> + .sta_ofs = 0x0,
> +};
> +
> +#define GATE_MFG(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate mfg_clks[] = {
> + GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "top_mfg_core_tmp", 0),
> +};
> +
> +static const struct mtk_clk_desc mfg_desc = {
> + .clks = mfg_clks,
> + .num_clks = ARRAY_SIZE(mfg_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8195_mfg[] = {
> + {
> + .compatible = "mediatek,mt8195-mfgcfg",
> + .data = &mfg_desc,
> + }, {
> + /* sentinel */
> + }
> +};
> +
> +static struct platform_driver clk_mt8195_mfg_drv = {
> + .probe = mtk_clk_simple_probe,
> + .driver = {
> + .name = "clk-mt8195-mfg",
> + .of_match_table = of_match_clk_mt8195_mfg,
> + },
> +};
> +builtin_platform_driver(clk_mt8195_mfg_drv);
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
next prev parent reply other threads:[~2021-08-23 12:03 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-20 11:14 [v2 00/24] Mediatek MT8195 clock support Chun-Jie Chen
2021-08-20 11:14 ` [v2 01/24] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock Chun-Jie Chen
2021-08-23 6:53 ` Chen-Yu Tsai
2021-08-24 14:44 ` Rob Herring
2021-08-20 11:14 ` [v2 02/24] clk: mediatek: Add dt-bindings of MT8195 clocks Chun-Jie Chen
2021-08-24 15:17 ` Rob Herring
2021-08-25 11:39 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 03/24] clk: mediatek: Fix corner case of tuner_en_reg Chun-Jie Chen
2021-08-20 11:14 ` [v2 04/24] clk: mediatek: Add API for clock resource recycle Chun-Jie Chen
2021-08-23 6:40 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 05/24] clk: mediatek: Fix resource leak in mtk_clk_simple_probe Chun-Jie Chen
2021-08-23 6:42 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 06/24] clk: mediatek: Add MT8195 apmixedsys clock support Chun-Jie Chen
2021-08-23 9:21 ` Chen-Yu Tsai
2021-08-23 9:56 ` Chen-Yu Tsai
2021-08-29 18:26 ` Stephen Boyd
2021-08-20 11:14 ` [v2 07/24] clk: mediatek: Add MT8195 topckgen " Chun-Jie Chen
2021-08-23 11:16 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 08/24] clk: mediatek: Add MT8195 peripheral " Chun-Jie Chen
2021-08-23 11:22 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 09/24] clk: mediatek: Add MT8195 infrastructure " Chun-Jie Chen
2021-08-23 11:32 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 10/24] clk: mediatek: Add MT8195 camsys " Chun-Jie Chen
2021-08-20 11:14 ` [v2 11/24] clk: mediatek: Add MT8195 ccusys " Chun-Jie Chen
2021-08-23 12:13 ` Chen-Yu Tsai
2021-09-10 10:52 ` Chun-Jie Chen
2021-08-20 11:14 ` [v2 12/24] clk: mediatek: Add MT8195 imgsys " Chun-Jie Chen
2021-08-20 11:14 ` [v2 13/24] clk: mediatek: Add MT8195 ipesys " Chun-Jie Chen
2021-08-23 12:20 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 14/24] clk: mediatek: Add MT8195 mfgcfg " Chun-Jie Chen
2021-08-23 12:02 ` Chen-Yu Tsai [this message]
2021-08-20 11:14 ` [v2 15/24] clk: mediatek: Add MT8195 scp adsp " Chun-Jie Chen
2021-08-23 12:08 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 16/24] clk: mediatek: Add MT8195 vdecsys " Chun-Jie Chen
2021-08-23 12:21 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 17/24] clk: mediatek: Add MT8195 vdosys0 " Chun-Jie Chen
2021-08-25 10:52 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 18/24] clk: mediatek: Add MT8195 vdosys1 " Chun-Jie Chen
2021-08-25 10:55 ` Chen-Yu Tsai
2021-08-20 11:14 ` [v2 19/24] clk: mediatek: Add MT8195 vencsys " Chun-Jie Chen
2021-08-25 11:03 ` Chen-Yu Tsai
2021-09-10 11:09 ` Chun-Jie Chen
2021-09-14 3:47 ` Chen-Yu Tsai
2021-08-20 11:15 ` [v2 20/24] clk: mediatek: Add MT8195 vppsys0 " Chun-Jie Chen
2021-08-25 10:59 ` Chen-Yu Tsai
2021-08-20 11:15 ` [v2 21/24] clk: mediatek: Add MT8195 vppsys1 " Chun-Jie Chen
2021-08-25 11:00 ` Chen-Yu Tsai
2021-08-20 11:15 ` [v2 22/24] clk: mediatek: Add MT8195 wpesys " Chun-Jie Chen
2021-08-25 11:34 ` Chen-Yu Tsai
2021-09-10 11:04 ` Chun-Jie Chen
2021-08-20 11:15 ` [v2 23/24] clk: mediatek: Add MT8195 imp i2c wrapper " Chun-Jie Chen
2021-08-23 12:50 ` Chen-Yu Tsai
2021-08-20 11:15 ` [v2 24/24] clk: mediatek: Add MT8195 apusys " Chun-Jie Chen
2021-08-23 12:48 ` Chen-Yu Tsai
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAGXv+5H-NqZYeGUwsZQnu45DQLn=JX=4zrpuGHZ4ArC7p3Ks=Q@mail.gmail.com' \
--to=wenst@chromium.org \
--cc=Project_Global_Chrome_Upstream_Group@mediatek.com \
--cc=chun-jie.chen@mediatek.com \
--cc=devicetree@vger.kernel.org \
--cc=drinkcat@chromium.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=srv_heupstream@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).