* [PATCH v12 1/7] dt-bindings: mediatek: mt8188: Add binding for MM & INFRA IOMMU
2023-06-02 9:02 [PATCH v12 0/7] MT8188 IOMMU SUPPORT Yong Wu
@ 2023-06-02 9:02 ` Yong Wu
2023-08-17 8:21 ` Chen-Yu Tsai
2023-06-02 9:02 ` [PATCH v12 2/7] iommu/mediatek: Fix two IOMMU share pagetable issue Yong Wu
` (6 subsequent siblings)
7 siblings, 1 reply; 25+ messages in thread
From: Yong Wu @ 2023-06-02 9:02 UTC (permalink / raw)
To: Joerg Roedel, Will Deacon, Rob Herring, Matthias Brugger
Cc: Robin Murphy, Krzysztof Kozlowski, Yong Wu,
AngeloGioacchino Del Regno, iommu, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, mingyuan.ma, yf.wang,
jianjiao.zeng, chengci.xu, Krzysztof Kozlowski
From: "Chengci.Xu" <chengci.xu@mediatek.com>
Add descriptions for mt8188 IOMMU which also use ARM Short-Descriptor
translation table format.
In mt8188, there are two smi-common HW and IOMMU, one is for vdo(video
output), the other is for vpp(video processing pipe). They connects
with different smi-larbs, then some setting(larbid_remap) is different.
Differentiate them with the compatible string.
Something like this:
IOMMU(VDO) IOMMU(VPP)
| |
SMI_COMMON_VDO SMI_COMMON_VPP
--------------- ----------------
| | ... | | ...
larb0 larb2 ... larb1 larb3 ...
We also have an IOMMU that is for infra master like PCIe.
And infra master don't have the larb and ports.
Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/iommu/mediatek,iommu.yaml | 12 +-
.../memory/mediatek,mt8188-memory-port.h | 489 ++++++++++++++++++
2 files changed, 500 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/memory/mediatek,mt8188-memory-port.h
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index 5b6395bc10e0..ea6b0f5f24de 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -78,6 +78,9 @@ properties:
- mediatek,mt8173-m4u # generation two
- mediatek,mt8183-m4u # generation two
- mediatek,mt8186-iommu-mm # generation two
+ - mediatek,mt8188-iommu-vdo # generation two
+ - mediatek,mt8188-iommu-vpp # generation two
+ - mediatek,mt8188-iommu-infra # generation two
- mediatek,mt8192-m4u # generation two
- mediatek,mt8195-iommu-vdo # generation two
- mediatek,mt8195-iommu-vpp # generation two
@@ -123,6 +126,7 @@ properties:
description: |
This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as
defined in
+ dt-binding/memory/mediatek,mt8188-memory-port.h for mt8188,
dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623,
dt-binding/memory/mt2712-larb-port.h for mt2712,
dt-binding/memory/mt6779-larb-port.h for mt6779,
@@ -155,6 +159,8 @@ allOf:
- mediatek,mt6795-m4u
- mediatek,mt8173-m4u
- mediatek,mt8186-iommu-mm
+ - mediatek,mt8188-iommu-vdo
+ - mediatek,mt8188-iommu-vpp
- mediatek,mt8192-m4u
- mediatek,mt8195-iommu-vdo
- mediatek,mt8195-iommu-vpp
@@ -168,6 +174,8 @@ allOf:
compatible:
enum:
- mediatek,mt8186-iommu-mm
+ - mediatek,mt8188-iommu-vdo
+ - mediatek,mt8188-iommu-vpp
- mediatek,mt8192-m4u
- mediatek,mt8195-iommu-vdo
- mediatek,mt8195-iommu-vpp
@@ -194,7 +202,9 @@ allOf:
properties:
compatible:
contains:
- const: mediatek,mt8195-iommu-infra
+ enum:
+ - mediatek,mt8188-iommu-infra
+ - mediatek,mt8195-iommu-infra
then:
required:
diff --git a/include/dt-bindings/memory/mediatek,mt8188-memory-port.h b/include/dt-bindings/memory/mediatek,mt8188-memory-port.h
new file mode 100644
index 000000000000..337ab11262af
--- /dev/null
+++ b/include/dt-bindings/memory/mediatek,mt8188-memory-port.h
@@ -0,0 +1,489 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Chengci Xu <chengci.xu@mediatek.com>
+ */
+#ifndef _DT_BINDINGS_MEMORY_MEDIATEK_MT8188_LARB_PORT_H_
+#define _DT_BINDINGS_MEMORY_MEDIATEK_MT8188_LARB_PORT_H_
+
+#include <dt-bindings/memory/mtk-memory-port.h>
+
+/*
+ * MM IOMMU larbs:
+ * From below, for example larb11 has larb11a/larb11b/larb11c,
+ * the index of larb is not in order. So we reindexed these larbs from a
+ * software view.
+ */
+#define SMI_L0_ID 0
+#define SMI_L1_ID 1
+#define SMI_L2_ID 2
+#define SMI_L3_ID 3
+#define SMI_L4_ID 4
+#define SMI_L5_ID 5
+#define SMI_L6_ID 6
+#define SMI_L7_ID 7
+#define SMI_L9_ID 8
+#define SMI_L10_ID 9
+#define SMI_L11A_ID 10
+#define SMI_L11B_ID 11
+#define SMI_L11C_ID 12
+#define SMI_L12_ID 13
+#define SMI_L13_ID 14
+#define SMI_L14_ID 15
+#define SMI_L15_ID 16
+#define SMI_L16A_ID 17
+#define SMI_L16B_ID 18
+#define SMI_L17A_ID 19
+#define SMI_L17B_ID 20
+#define SMI_L19_ID 21
+#define SMI_L21_ID 22
+#define SMI_L23_ID 23
+#define SMI_L27_ID 24
+#define SMI_L28_ID 25
+
+/*
+ * MM IOMMU supports 16GB dma address. We separate it to four ranges:
+ * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
+ * locate in anyone region. BUT:
+ * a) Make sure all the ports inside a larb are in one range.
+ * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
+ *
+ * This is the suggested mapping in this SoC:
+ *
+ * modules dma-address-region larbs-ports
+ * disp 0 ~ 4G larb0/1/2/3
+ * vcodec 4G ~ 8G larb19(21)[1]/21(22)/23
+ * cam/mdp 8G ~ 12G the other larbs.
+ * N/A 12G ~ 16G
+ * CCU0 0x24000_0000 ~ 0x243ff_ffff larb27(24): port 0/1
+ * CCU1 0x24400_0000 ~ 0x247ff_ffff larb27(24): port 2/3
+ *
+ * This SoC have two MM IOMMU HWs, this is the connected information:
+ * iommu-vdo: larb0/2/5/9/10/11A/11C/13/16B/17B/19/21
+ * iommu-vpp: larb1/3/4/6/7/11B/12/14/15/16A/17A/23/27
+ *
+ * [1]: This is larb19, but the index is 21 from the SW view.
+ */
+
+/* MM IOMMU ports */
+/* LARB 0 -- VDO-0 */
+#define M4U_PORT_L0_DISP_RDMA1 MTK_M4U_ID(SMI_L0_ID, 0)
+#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(SMI_L0_ID, 1)
+#define M4U_PORT_L0_DISP_OVL0_RDMA0 MTK_M4U_ID(SMI_L0_ID, 2)
+#define M4U_PORT_L0_DISP_OVL0_RDMA1 MTK_M4U_ID(SMI_L0_ID, 3)
+#define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_ID(SMI_L0_ID, 4)
+#define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(SMI_L0_ID, 5)
+#define M4U_PORT_L0_DISP_FAKE_ENG0 MTK_M4U_ID(SMI_L0_ID, 6)
+
+/* LARB 1 -- VD0-0 */
+#define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_ID(SMI_L1_ID, 0)
+#define M4U_PORT_L1_DISP_WDMA1 MTK_M4U_ID(SMI_L1_ID, 1)
+#define M4U_PORT_L1_DISP_OVL1_RDMA0 MTK_M4U_ID(SMI_L1_ID, 2)
+#define M4U_PORT_L1_DISP_OVL1_RDMA1 MTK_M4U_ID(SMI_L1_ID, 3)
+#define M4U_PORT_L1_DISP_OVL1_HDR MTK_M4U_ID(SMI_L1_ID, 4)
+#define M4U_PORT_L1_DISP_WROT0 MTK_M4U_ID(SMI_L1_ID, 5)
+#define M4U_PORT_L1_DISP_FAKE_ENG1 MTK_M4U_ID(SMI_L1_ID, 6)
+
+/* LARB 2 -- VDO-1 */
+#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(SMI_L2_ID, 0)
+#define M4U_PORT_L2_MDP_RDMA2 MTK_M4U_ID(SMI_L2_ID, 1)
+#define M4U_PORT_L2_MDP_RDMA4 MTK_M4U_ID(SMI_L2_ID, 2)
+#define M4U_PORT_L2_MDP_RDMA6 MTK_M4U_ID(SMI_L2_ID, 3)
+#define M4U_PORT_L2_DISP_FAKE1 MTK_M4U_ID(SMI_L2_ID, 4)
+
+/* LARB 3 -- VDO-1 */
+#define M4U_PORT_L3_MDP_RDMA1 MTK_M4U_ID(SMI_L3_ID, 0)
+#define M4U_PORT_L3_MDP_RDMA3 MTK_M4U_ID(SMI_L3_ID, 1)
+#define M4U_PORT_L3_MDP_RDMA5 MTK_M4U_ID(SMI_L3_ID, 2)
+#define M4U_PORT_L3_MDP_RDMA7 MTK_M4U_ID(SMI_L3_ID, 3)
+#define M4U_PORT_L3_HDR_DS_SMI MTK_M4U_ID(SMI_L3_ID, 4)
+#define M4U_PORT_L3_HDR_ADL_SMI MTK_M4U_ID(SMI_L3_ID, 5)
+#define M4U_PORT_L3_DISP_FAKE1 MTK_M4U_ID(SMI_L3_ID, 6)
+
+/* LARB 4 -- VPP-0 */
+#define M4U_PORT_L4_MDP_RDMA MTK_M4U_ID(SMI_L4_ID, 0)
+#define M4U_PORT_L4_MDP_FG MTK_M4U_ID(SMI_L4_ID, 1)
+#define M4U_PORT_L4_MDP_OVL MTK_M4U_ID(SMI_L4_ID, 2)
+#define M4U_PORT_L4_MDP_WROT MTK_M4U_ID(SMI_L4_ID, 3)
+#define M4U_PORT_L4_FAKE_ENG MTK_M4U_ID(SMI_L4_ID, 4)
+#define M4U_PORT_L4_DISP_RDMA MTK_M4U_ID(SMI_L4_ID, 5)
+#define M4U_PORT_L4_DISP_WDMA MTK_M4U_ID(SMI_L4_ID, 6)
+
+/* LARB 5 -- VPP-1 */
+#define M4U_PORT_L5_SVPP1_MDP_RDMA MTK_M4U_ID(SMI_L5_ID, 0)
+#define M4U_PORT_L5_SVPP1_MDP_FG MTK_M4U_ID(SMI_L5_ID, 1)
+#define M4U_PORT_L5_SVPP1_MDP_OVL MTK_M4U_ID(SMI_L5_ID, 2)
+#define M4U_PORT_L5_SVPP1_MDP_WROT MTK_M4U_ID(SMI_L5_ID, 3)
+#define M4U_PORT_L5_SVPP2_MDP_RDMA MTK_M4U_ID(SMI_L5_ID, 4)
+#define M4U_PORT_L5_SVPP2_MDP_FG MTK_M4U_ID(SMI_L5_ID, 5)
+#define M4U_PORT_L5_SVPP2_MDP_WROT MTK_M4U_ID(SMI_L5_ID, 6)
+#define M4U_PORT_L5_LARB5_FAKE_ENG MTK_M4U_ID(SMI_L5_ID, 7)
+
+/* LARB 6 -- VPP-1 */
+#define M4U_PORT_L6_SVPP3_MDP_RDMA MTK_M4U_ID(SMI_L6_ID, 0)
+#define M4U_PORT_L6_SVPP3_MDP_FG MTK_M4U_ID(SMI_L6_ID, 1)
+#define M4U_PORT_L6_SVPP3_MDP_WROT MTK_M4U_ID(SMI_L6_ID, 2)
+#define M4U_PORT_L6_LARB6_FAKE_ENG MTK_M4U_ID(SMI_L6_ID, 3)
+
+/* LARB 7 -- WPE */
+#define M4U_PORT_L7_WPE_RDMA_0 MTK_M4U_ID(SMI_L7_ID, 0)
+#define M4U_PORT_L7_WPE_RDMA_1 MTK_M4U_ID(SMI_L7_ID, 1)
+#define M4U_PORT_L7_WPE_WDMA_0 MTK_M4U_ID(SMI_L7_ID, 2)
+
+/* LARB 9 -- IMG-M */
+#define M4U_PORT_L9_IMGI_T1_A MTK_M4U_ID(SMI_L9_ID, 0)
+#define M4U_PORT_L9_UFDI_T1_A MTK_M4U_ID(SMI_L9_ID, 1)
+#define M4U_PORT_L9_IMGBI_T1_A MTK_M4U_ID(SMI_L9_ID, 2)
+#define M4U_PORT_L9_IMGCI_T1_A MTK_M4U_ID(SMI_L9_ID, 3)
+#define M4U_PORT_L9_SMTI_T1_A MTK_M4U_ID(SMI_L9_ID, 4)
+#define M4U_PORT_L9_SMTI_T4_A MTK_M4U_ID(SMI_L9_ID, 5)
+#define M4U_PORT_L9_TNCSTI_T1_A MTK_M4U_ID(SMI_L9_ID, 6)
+#define M4U_PORT_L9_TNCSTI_T4_A MTK_M4U_ID(SMI_L9_ID, 7)
+#define M4U_PORT_L9_YUVO_T1_A MTK_M4U_ID(SMI_L9_ID, 8)
+#define M4U_PORT_L9_YUVBO_T1_A MTK_M4U_ID(SMI_L9_ID, 9)
+#define M4U_PORT_L9_YUVCO_T1_A MTK_M4U_ID(SMI_L9_ID, 10)
+#define M4U_PORT_L9_TIMGO_T1_A MTK_M4U_ID(SMI_L9_ID, 11)
+#define M4U_PORT_L9_YUVO_T2_A MTK_M4U_ID(SMI_L9_ID, 12)
+#define M4U_PORT_L9_YUVO_T5_A MTK_M4U_ID(SMI_L9_ID, 13)
+#define M4U_PORT_L9_IMGI_T1_B MTK_M4U_ID(SMI_L9_ID, 14)
+#define M4U_PORT_L9_IMGBI_T1_B MTK_M4U_ID(SMI_L9_ID, 15)
+#define M4U_PORT_L9_IMGCI_T1_B MTK_M4U_ID(SMI_L9_ID, 16)
+#define M4U_PORT_L9_SMTI_T4_B MTK_M4U_ID(SMI_L9_ID, 17)
+#define M4U_PORT_L9_TNCSO_T1_A MTK_M4U_ID(SMI_L9_ID, 18)
+#define M4U_PORT_L9_SMTO_T1_A MTK_M4U_ID(SMI_L9_ID, 19)
+#define M4U_PORT_L9_SMTO_T4_A MTK_M4U_ID(SMI_L9_ID, 20)
+#define M4U_PORT_L9_TNCSTO_T1_A MTK_M4U_ID(SMI_L9_ID, 21)
+#define M4U_PORT_L9_YUVO_T2_B MTK_M4U_ID(SMI_L9_ID, 22)
+#define M4U_PORT_L9_YUVO_T5_B MTK_M4U_ID(SMI_L9_ID, 23)
+#define M4U_PORT_L9_SMTO_T4_B MTK_M4U_ID(SMI_L9_ID, 24)
+
+/* LARB 10 -- IMG-D */
+#define M4U_PORT_L10_IMGI_D1 MTK_M4U_ID(SMI_L10_ID, 0)
+#define M4U_PORT_L10_IMGBI_D1 MTK_M4U_ID(SMI_L10_ID, 1)
+#define M4U_PORT_L10_IMGCI_D1 MTK_M4U_ID(SMI_L10_ID, 2)
+#define M4U_PORT_L10_IMGDI_D1 MTK_M4U_ID(SMI_L10_ID, 3)
+#define M4U_PORT_L10_DEPI_D1 MTK_M4U_ID(SMI_L10_ID, 4)
+#define M4U_PORT_L10_DMGI_D1 MTK_M4U_ID(SMI_L10_ID, 5)
+#define M4U_PORT_L10_SMTI_D1 MTK_M4U_ID(SMI_L10_ID, 6)
+#define M4U_PORT_L10_RECI_D1 MTK_M4U_ID(SMI_L10_ID, 7)
+#define M4U_PORT_L10_RECI_D1_N MTK_M4U_ID(SMI_L10_ID, 8)
+#define M4U_PORT_L10_TNRWI_D1 MTK_M4U_ID(SMI_L10_ID, 9)
+#define M4U_PORT_L10_TNRCI_D1 MTK_M4U_ID(SMI_L10_ID, 10)
+#define M4U_PORT_L10_TNRCI_D1_N MTK_M4U_ID(SMI_L10_ID, 11)
+#define M4U_PORT_L10_IMG4O_D1 MTK_M4U_ID(SMI_L10_ID, 12)
+#define M4U_PORT_L10_IMG4BO_D1 MTK_M4U_ID(SMI_L10_ID, 13)
+#define M4U_PORT_L10_SMTI_D8 MTK_M4U_ID(SMI_L10_ID, 14)
+#define M4U_PORT_L10_SMTO_D1 MTK_M4U_ID(SMI_L10_ID, 15)
+#define M4U_PORT_L10_TNRMO_D1 MTK_M4U_ID(SMI_L10_ID, 16)
+#define M4U_PORT_L10_TNRMO_D1_N MTK_M4U_ID(SMI_L10_ID, 17)
+#define M4U_PORT_L10_SMTO_D8 MTK_M4U_ID(SMI_L10_ID, 18)
+#define M4U_PORT_L10_DBGO_D1 MTK_M4U_ID(SMI_L10_ID, 19)
+
+/* LARB 11A -- IMG-D */
+#define M4U_PORT_L11A_WPE_RDMA_0 MTK_M4U_ID(SMI_L11A_ID, 0)
+#define M4U_PORT_L11A_WPE_RDMA_1 MTK_M4U_ID(SMI_L11A_ID, 1)
+#define M4U_PORT_L11A_WPE_RDMA_4P_0 MTK_M4U_ID(SMI_L11A_ID, 2)
+#define M4U_PORT_L11A_WPE_RDMA_4P_1 MTK_M4U_ID(SMI_L11A_ID, 3)
+#define M4U_PORT_L11A_WPE_CQ0 MTK_M4U_ID(SMI_L11A_ID, 4)
+#define M4U_PORT_L11A_WPE_CQ1 MTK_M4U_ID(SMI_L11A_ID, 5)
+#define M4U_PORT_L11A_PIMGI_P1 MTK_M4U_ID(SMI_L11A_ID, 6)
+#define M4U_PORT_L11A_PIMGBI_P1 MTK_M4U_ID(SMI_L11A_ID, 7)
+#define M4U_PORT_L11A_PIMGCI_P1 MTK_M4U_ID(SMI_L11A_ID, 8)
+#define M4U_PORT_L11A_IMGI_T1_C MTK_M4U_ID(SMI_L11A_ID, 9)
+#define M4U_PORT_L11A_IMGBI_T1_C MTK_M4U_ID(SMI_L11A_ID, 10)
+#define M4U_PORT_L11A_IMGCI_T1_C MTK_M4U_ID(SMI_L11A_ID, 11)
+#define M4U_PORT_L11A_SMTI_T1_C MTK_M4U_ID(SMI_L11A_ID, 12)
+#define M4U_PORT_L11A_SMTI_T4_C MTK_M4U_ID(SMI_L11A_ID, 13)
+#define M4U_PORT_L11A_SMTI_T6_C MTK_M4U_ID(SMI_L11A_ID, 14)
+#define M4U_PORT_L11A_YUVO_T1_C MTK_M4U_ID(SMI_L11A_ID, 15)
+#define M4U_PORT_L11A_YUVBO_T1_C MTK_M4U_ID(SMI_L11A_ID, 16)
+#define M4U_PORT_L11A_YUVCO_T1_C MTK_M4U_ID(SMI_L11A_ID, 17)
+#define M4U_PORT_L11A_WPE_WDMA_0 MTK_M4U_ID(SMI_L11A_ID, 18)
+#define M4U_PORT_L11A_WPE_WDMA_4P_0 MTK_M4U_ID(SMI_L11A_ID, 19)
+#define M4U_PORT_L11A_WROT_P1 MTK_M4U_ID(SMI_L11A_ID, 20)
+#define M4U_PORT_L11A_TCCSO_P1 MTK_M4U_ID(SMI_L11A_ID, 21)
+#define M4U_PORT_L11A_TCCSI_P1 MTK_M4U_ID(SMI_L11A_ID, 22)
+#define M4U_PORT_L11A_TIMGO_T1_C MTK_M4U_ID(SMI_L11A_ID, 23)
+#define M4U_PORT_L11A_YUVO_T2_C MTK_M4U_ID(SMI_L11A_ID, 24)
+#define M4U_PORT_L11A_YUVO_T5_C MTK_M4U_ID(SMI_L11A_ID, 25)
+#define M4U_PORT_L11A_SMTO_T1_C MTK_M4U_ID(SMI_L11A_ID, 26)
+#define M4U_PORT_L11A_SMTO_T4_C MTK_M4U_ID(SMI_L11A_ID, 27)
+#define M4U_PORT_L11A_SMTO_T6_C MTK_M4U_ID(SMI_L11A_ID, 28)
+#define M4U_PORT_L11A_DBGO_T1_C MTK_M4U_ID(SMI_L11A_ID, 29)
+
+/* LARB 11B -- IMG-D */
+#define M4U_PORT_L11B_WPE_RDMA_0 MTK_M4U_ID(SMI_L11B_ID, 0)
+#define M4U_PORT_L11B_WPE_RDMA_1 MTK_M4U_ID(SMI_L11B_ID, 1)
+#define M4U_PORT_L11B_WPE_RDMA_4P_0 MTK_M4U_ID(SMI_L11B_ID, 2)
+#define M4U_PORT_L11B_WPE_RDMA_4P_1 MTK_M4U_ID(SMI_L11B_ID, 3)
+#define M4U_PORT_L11B_WPE_CQ0 MTK_M4U_ID(SMI_L11B_ID, 4)
+#define M4U_PORT_L11B_WPE_CQ1 MTK_M4U_ID(SMI_L11B_ID, 5)
+#define M4U_PORT_L11B_PIMGI_P1 MTK_M4U_ID(SMI_L11B_ID, 6)
+#define M4U_PORT_L11B_PIMGBI_P1 MTK_M4U_ID(SMI_L11B_ID, 7)
+#define M4U_PORT_L11B_PIMGCI_P1 MTK_M4U_ID(SMI_L11B_ID, 8)
+#define M4U_PORT_L11B_IMGI_T1_C MTK_M4U_ID(SMI_L11B_ID, 9)
+#define M4U_PORT_L11B_IMGBI_T1_C MTK_M4U_ID(SMI_L11B_ID, 10)
+#define M4U_PORT_L11B_IMGCI_T1_C MTK_M4U_ID(SMI_L11B_ID, 11)
+#define M4U_PORT_L11B_SMTI_T1_C MTK_M4U_ID(SMI_L11B_ID, 12)
+#define M4U_PORT_L11B_SMTI_T4_C MTK_M4U_ID(SMI_L11B_ID, 13)
+#define M4U_PORT_L11B_SMTI_T6_C MTK_M4U_ID(SMI_L11B_ID, 14)
+#define M4U_PORT_L11B_YUVO_T1_C MTK_M4U_ID(SMI_L11B_ID, 15)
+#define M4U_PORT_L11B_YUVBO_T1_C MTK_M4U_ID(SMI_L11B_ID, 16)
+#define M4U_PORT_L11B_YUVCO_T1_C MTK_M4U_ID(SMI_L11B_ID, 17)
+#define M4U_PORT_L11B_WPE_WDMA_0 MTK_M4U_ID(SMI_L11B_ID, 18)
+#define M4U_PORT_L11B_WPE_WDMA_4P_0 MTK_M4U_ID(SMI_L11B_ID, 19)
+#define M4U_PORT_L11B_WROT_P1 MTK_M4U_ID(SMI_L11B_ID, 20)
+#define M4U_PORT_L11B_TCCSO_P1 MTK_M4U_ID(SMI_L11B_ID, 21)
+#define M4U_PORT_L11B_TCCSI_P1 MTK_M4U_ID(SMI_L11B_ID, 22)
+#define M4U_PORT_L11B_TIMGO_T1_C MTK_M4U_ID(SMI_L11B_ID, 23)
+#define M4U_PORT_L11B_YUVO_T2_C MTK_M4U_ID(SMI_L11B_ID, 24)
+#define M4U_PORT_L11B_YUVO_T5_C MTK_M4U_ID(SMI_L11B_ID, 25)
+#define M4U_PORT_L11B_SMTO_T1_C MTK_M4U_ID(SMI_L11B_ID, 26)
+#define M4U_PORT_L11B_SMTO_T4_C MTK_M4U_ID(SMI_L11B_ID, 27)
+#define M4U_PORT_L11B_SMTO_T6_C MTK_M4U_ID(SMI_L11B_ID, 28)
+#define M4U_PORT_L11B_DBGO_T1_C MTK_M4U_ID(SMI_L11B_ID, 29)
+
+/* LARB 11C -- IMG-D */
+#define M4U_PORT_L11C_WPE_RDMA_0 MTK_M4U_ID(SMI_L11C_ID, 0)
+#define M4U_PORT_L11C_WPE_RDMA_1 MTK_M4U_ID(SMI_L11C_ID, 1)
+#define M4U_PORT_L11C_WPE_RDMA_4P_0 MTK_M4U_ID(SMI_L11C_ID, 2)
+#define M4U_PORT_L11C_WPE_RDMA_4P_1 MTK_M4U_ID(SMI_L11C_ID, 3)
+#define M4U_PORT_L11C_WPE_CQ0 MTK_M4U_ID(SMI_L11C_ID, 4)
+#define M4U_PORT_L11C_WPE_CQ1 MTK_M4U_ID(SMI_L11C_ID, 5)
+#define M4U_PORT_L11C_PIMGI_P1 MTK_M4U_ID(SMI_L11C_ID, 6)
+#define M4U_PORT_L11C_PIMGBI_P1 MTK_M4U_ID(SMI_L11C_ID, 7)
+#define M4U_PORT_L11C_PIMGCI_P1 MTK_M4U_ID(SMI_L11C_ID, 8)
+#define M4U_PORT_L11C_IMGI_T1_C MTK_M4U_ID(SMI_L11C_ID, 9)
+#define M4U_PORT_L11C_IMGBI_T1_C MTK_M4U_ID(SMI_L11C_ID, 10)
+#define M4U_PORT_L11C_IMGCI_T1_C MTK_M4U_ID(SMI_L11C_ID, 11)
+#define M4U_PORT_L11C_SMTI_T1_C MTK_M4U_ID(SMI_L11C_ID, 12)
+#define M4U_PORT_L11C_SMTI_T4_C MTK_M4U_ID(SMI_L11C_ID, 13)
+#define M4U_PORT_L11C_SMTI_T6_C MTK_M4U_ID(SMI_L11C_ID, 14)
+#define M4U_PORT_L11C_YUVO_T1_C MTK_M4U_ID(SMI_L11C_ID, 15)
+#define M4U_PORT_L11C_YUVBO_T1_C MTK_M4U_ID(SMI_L11C_ID, 16)
+#define M4U_PORT_L11C_YUVCO_T1_C MTK_M4U_ID(SMI_L11C_ID, 17)
+#define M4U_PORT_L11C_WPE_WDMA_0 MTK_M4U_ID(SMI_L11C_ID, 18)
+#define M4U_PORT_L11C_WPE_WDMA_4P_0 MTK_M4U_ID(SMI_L11C_ID, 19)
+#define M4U_PORT_L11C_WROT_P1 MTK_M4U_ID(SMI_L11C_ID, 20)
+#define M4U_PORT_L11C_TCCSO_P1 MTK_M4U_ID(SMI_L11C_ID, 21)
+#define M4U_PORT_L11C_TCCSI_P1 MTK_M4U_ID(SMI_L11C_ID, 22)
+#define M4U_PORT_L11C_TIMGO_T1_C MTK_M4U_ID(SMI_L11C_ID, 23)
+#define M4U_PORT_L11C_YUVO_T2_C MTK_M4U_ID(SMI_L11C_ID, 24)
+#define M4U_PORT_L11C_YUVO_T5_C MTK_M4U_ID(SMI_L11C_ID, 25)
+#define M4U_PORT_L11C_SMTO_T1_C MTK_M4U_ID(SMI_L11C_ID, 26)
+#define M4U_PORT_L11C_SMTO_T4_C MTK_M4U_ID(SMI_L11C_ID, 27)
+#define M4U_PORT_L11C_SMTO_T6_C MTK_M4U_ID(SMI_L11C_ID, 28)
+#define M4U_PORT_L11C_DBGO_T1_C MTK_M4U_ID(SMI_L11C_ID, 29)
+
+/* LARB 12 -- IPE */
+#define M4U_PORT_L12_FDVT_RDA_0 MTK_M4U_ID(SMI_L12_ID, 0)
+#define M4U_PORT_L12_FDVT_RDB_0 MTK_M4U_ID(SMI_L12_ID, 1)
+#define M4U_PORT_L12_FDVT_WRA_0 MTK_M4U_ID(SMI_L12_ID, 2)
+#define M4U_PORT_L12_FDVT_WRB_0 MTK_M4U_ID(SMI_L12_ID, 3)
+#define M4U_PORT_L12_ME_RDMA MTK_M4U_ID(SMI_L12_ID, 4)
+#define M4U_PORT_L12_ME_WDMA MTK_M4U_ID(SMI_L12_ID, 5)
+#define M4U_PORT_L12_DVS_RDMA MTK_M4U_ID(SMI_L12_ID, 6)
+#define M4U_PORT_L12_DVS_WDMA MTK_M4U_ID(SMI_L12_ID, 7)
+#define M4U_PORT_L12_DVP_RDMA MTK_M4U_ID(SMI_L12_ID, 8)
+#define M4U_PORT_L12_DVP_WDMA MTK_M4U_ID(SMI_L12_ID, 9)
+#define M4U_PORT_L12_FDVT_2ND_RDA_0 MTK_M4U_ID(SMI_L12_ID, 10)
+#define M4U_PORT_L12_FDVT_2ND_RDB_0 MTK_M4U_ID(SMI_L12_ID, 11)
+#define M4U_PORT_L12_FDVT_2ND_WRA_0 MTK_M4U_ID(SMI_L12_ID, 12)
+#define M4U_PORT_L12_FDVT_2ND_WRB_0 MTK_M4U_ID(SMI_L12_ID, 13)
+#define M4U_PORT_L12_DHZEI_E1 MTK_M4U_ID(SMI_L12_ID, 14)
+#define M4U_PORT_L12_DHZEO_E1 MTK_M4U_ID(SMI_L12_ID, 15)
+
+/* LARB 13 -- CAM-1 */
+#define M4U_PORT_L13_CAMSV_CQI_E1 MTK_M4U_ID(SMI_L13_ID, 0)
+#define M4U_PORT_L13_CAMSV_CQI_E2 MTK_M4U_ID(SMI_L13_ID, 1)
+#define M4U_PORT_L13_GCAMSV_A_IMGO_1 MTK_M4U_ID(SMI_L13_ID, 2)
+#define M4U_PORT_L13_GCAMSV_C_IMGO_1 MTK_M4U_ID(SMI_L13_ID, 3)
+#define M4U_PORT_L13_GCAMSV_A_IMGO_2 MTK_M4U_ID(SMI_L13_ID, 4)
+#define M4U_PORT_L13_GCAMSV_C_IMGO_2 MTK_M4U_ID(SMI_L13_ID, 5)
+#define M4U_PORT_L13_PDAI_A_0 MTK_M4U_ID(SMI_L13_ID, 6)
+#define M4U_PORT_L13_PDAI_A_1 MTK_M4U_ID(SMI_L13_ID, 7)
+#define M4U_PORT_L13_CAMSV_CQI_B_E1 MTK_M4U_ID(SMI_L13_ID, 8)
+#define M4U_PORT_L13_CAMSV_CQI_B_E2 MTK_M4U_ID(SMI_L13_ID, 9)
+#define M4U_PORT_L13_CAMSV_CQI_C_E1 MTK_M4U_ID(SMI_L13_ID, 10)
+#define M4U_PORT_L13_CAMSV_CQI_C_E2 MTK_M4U_ID(SMI_L13_ID, 11)
+#define M4U_PORT_L13_GCAMSV_E_IMGO_1 MTK_M4U_ID(SMI_L13_ID, 12)
+#define M4U_PORT_L13_GCAMSV_E_IMGO_2 MTK_M4U_ID(SMI_L13_ID, 13)
+#define M4U_PORT_L13_GCAMSV_A_UFEO_1 MTK_M4U_ID(SMI_L13_ID, 14)
+#define M4U_PORT_L13_GCAMSV_C_UFEO_1 MTK_M4U_ID(SMI_L13_ID, 15)
+#define M4U_PORT_L13_GCAMSV_A_UFEO_2 MTK_M4U_ID(SMI_L13_ID, 16)
+#define M4U_PORT_L13_GCAMSV_C_UFEO_2 MTK_M4U_ID(SMI_L13_ID, 17)
+#define M4U_PORT_L13_GCAMSV_E_UFEO_1 MTK_M4U_ID(SMI_L13_ID, 18)
+#define M4U_PORT_L13_GCAMSV_E_UFEO_2 MTK_M4U_ID(SMI_L13_ID, 19)
+#define M4U_PORT_L13_GCAMSV_G_IMGO_1 MTK_M4U_ID(SMI_L13_ID, 20)
+#define M4U_PORT_L13_GCAMSV_G_IMGO_2 MTK_M4U_ID(SMI_L13_ID, 21)
+#define M4U_PORT_L13_PDAO_A MTK_M4U_ID(SMI_L13_ID, 22)
+#define M4U_PORT_L13_PDAO_C MTK_M4U_ID(SMI_L13_ID, 23)
+
+/* LARB 14 -- CAM-1 */
+#define M4U_PORT_L14_GCAMSV_B_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 0)
+#define M4U_PORT_L14_GCAMSV_B_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 1)
+#define M4U_PORT_L14_SCAMSV_A_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 2)
+#define M4U_PORT_L14_SCAMSV_A_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 3)
+#define M4U_PORT_L14_SCAMSV_B_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 4)
+#define M4U_PORT_L14_SCAMSV_B_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 5)
+#define M4U_PORT_L14_PDAI_B_0 MTK_M4U_ID(SMI_L14_ID, 6)
+#define M4U_PORT_L14_PDAI_B_1 MTK_M4U_ID(SMI_L14_ID, 7)
+#define M4U_PORT_L14_GCAMSV_D_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 8)
+#define M4U_PORT_L14_GCAMSV_D_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 9)
+#define M4U_PORT_L14_GCAMSV_F_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 10)
+#define M4U_PORT_L14_GCAMSV_F_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 11)
+#define M4U_PORT_L14_GCAMSV_H_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 12)
+#define M4U_PORT_L14_GCAMSV_H_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 13)
+#define M4U_PORT_L14_GCAMSV_B_UFEO_1 MTK_M4U_ID(SMI_L14_ID, 14)
+#define M4U_PORT_L14_GCAMSV_B_UFEO_2 MTK_M4U_ID(SMI_L14_ID, 15)
+#define M4U_PORT_L14_GCAMSV_D_UFEO_1 MTK_M4U_ID(SMI_L14_ID, 16)
+#define M4U_PORT_L14_GCAMSV_D_UFEO_2 MTK_M4U_ID(SMI_L14_ID, 17)
+#define M4U_PORT_L14_PDAO_B MTK_M4U_ID(SMI_L14_ID, 18)
+#define M4U_PORT_L14_IPUI MTK_M4U_ID(SMI_L14_ID, 19)
+#define M4U_PORT_L14_IPUO MTK_M4U_ID(SMI_L14_ID, 20)
+#define M4U_PORT_L14_IPU3O MTK_M4U_ID(SMI_L14_ID, 21)
+#define M4U_PORT_L14_FAKE MTK_M4U_ID(SMI_L14_ID, 22)
+
+/* LARB 15 -- IMG-D */
+#define M4U_PORT_L15_VIPI_D1 MTK_M4U_ID(SMI_L15_ID, 0)
+#define M4U_PORT_L15_VIPBI_D1 MTK_M4U_ID(SMI_L15_ID, 1)
+#define M4U_PORT_L15_SMTI_D6 MTK_M4U_ID(SMI_L15_ID, 2)
+#define M4U_PORT_L15_TNCSTI_D1 MTK_M4U_ID(SMI_L15_ID, 3)
+#define M4U_PORT_L15_TNCSTI_D4 MTK_M4U_ID(SMI_L15_ID, 4)
+#define M4U_PORT_L15_SMTI_D4 MTK_M4U_ID(SMI_L15_ID, 5)
+#define M4U_PORT_L15_IMG3O_D1 MTK_M4U_ID(SMI_L15_ID, 6)
+#define M4U_PORT_L15_IMG3BO_D1 MTK_M4U_ID(SMI_L15_ID, 7)
+#define M4U_PORT_L15_IMG3CO_D1 MTK_M4U_ID(SMI_L15_ID, 8)
+#define M4U_PORT_L15_IMG2O_D1 MTK_M4U_ID(SMI_L15_ID, 9)
+#define M4U_PORT_L15_SMTI_D9 MTK_M4U_ID(SMI_L15_ID, 10)
+#define M4U_PORT_L15_SMTO_D4 MTK_M4U_ID(SMI_L15_ID, 11)
+#define M4U_PORT_L15_FEO_D1 MTK_M4U_ID(SMI_L15_ID, 12)
+#define M4U_PORT_L15_TNCSO_D1 MTK_M4U_ID(SMI_L15_ID, 13)
+#define M4U_PORT_L15_TNCSTO_D1 MTK_M4U_ID(SMI_L15_ID, 14)
+#define M4U_PORT_L15_SMTO_D6 MTK_M4U_ID(SMI_L15_ID, 15)
+#define M4U_PORT_L15_SMTO_D9 MTK_M4U_ID(SMI_L15_ID, 16)
+#define M4U_PORT_L15_TNCO_D1 MTK_M4U_ID(SMI_L15_ID, 17)
+#define M4U_PORT_L15_TNCO_D1_N MTK_M4U_ID(SMI_L15_ID, 18)
+
+/* LARB 16A -- CAM */
+#define M4U_PORT_L16A_IMGO_R1 MTK_M4U_ID(SMI_L16A_ID, 0)
+#define M4U_PORT_L16A_CQI_R1 MTK_M4U_ID(SMI_L16A_ID, 1)
+#define M4U_PORT_L16A_CQI_R2 MTK_M4U_ID(SMI_L16A_ID, 2)
+#define M4U_PORT_L16A_BPCI_R1 MTK_M4U_ID(SMI_L16A_ID, 3)
+#define M4U_PORT_L16A_LSCI_R1 MTK_M4U_ID(SMI_L16A_ID, 4)
+#define M4U_PORT_L16A_RAWI_R2 MTK_M4U_ID(SMI_L16A_ID, 5)
+#define M4U_PORT_L16A_RAWI_R3 MTK_M4U_ID(SMI_L16A_ID, 6)
+#define M4U_PORT_L16A_UFDI_R2 MTK_M4U_ID(SMI_L16A_ID, 7)
+#define M4U_PORT_L16A_UFDI_R3 MTK_M4U_ID(SMI_L16A_ID, 8)
+#define M4U_PORT_L16A_RAWI_R4 MTK_M4U_ID(SMI_L16A_ID, 9)
+#define M4U_PORT_L16A_RAWI_R5 MTK_M4U_ID(SMI_L16A_ID, 10)
+#define M4U_PORT_L16A_AAI_R1 MTK_M4U_ID(SMI_L16A_ID, 11)
+#define M4U_PORT_L16A_UFDI_R5 MTK_M4U_ID(SMI_L16A_ID, 12)
+#define M4U_PORT_L16A_FHO_R1 MTK_M4U_ID(SMI_L16A_ID, 13)
+#define M4U_PORT_L16A_AAO_R1 MTK_M4U_ID(SMI_L16A_ID, 14)
+#define M4U_PORT_L16A_TSFSO_R1 MTK_M4U_ID(SMI_L16A_ID, 15)
+#define M4U_PORT_L16A_FLKO_R1 MTK_M4U_ID(SMI_L16A_ID, 16)
+
+/* LARB 16B -- CAM */
+#define M4U_PORT_L16B_IMGO_R1 MTK_M4U_ID(SMI_L16B_ID, 0)
+#define M4U_PORT_L16B_CQI_R1 MTK_M4U_ID(SMI_L16B_ID, 1)
+#define M4U_PORT_L16B_CQI_R2 MTK_M4U_ID(SMI_L16B_ID, 2)
+#define M4U_PORT_L16B_BPCI_R1 MTK_M4U_ID(SMI_L16B_ID, 3)
+#define M4U_PORT_L16B_LSCI_R1 MTK_M4U_ID(SMI_L16B_ID, 4)
+#define M4U_PORT_L16B_RAWI_R2 MTK_M4U_ID(SMI_L16B_ID, 5)
+#define M4U_PORT_L16B_RAWI_R3 MTK_M4U_ID(SMI_L16B_ID, 6)
+#define M4U_PORT_L16B_UFDI_R2 MTK_M4U_ID(SMI_L16B_ID, 7)
+#define M4U_PORT_L16B_UFDI_R3 MTK_M4U_ID(SMI_L16B_ID, 8)
+#define M4U_PORT_L16B_RAWI_R4 MTK_M4U_ID(SMI_L16B_ID, 9)
+#define M4U_PORT_L16B_RAWI_R5 MTK_M4U_ID(SMI_L16B_ID, 10)
+#define M4U_PORT_L16B_AAI_R1 MTK_M4U_ID(SMI_L16B_ID, 11)
+#define M4U_PORT_L16B_UFDI_R5 MTK_M4U_ID(SMI_L16B_ID, 12)
+#define M4U_PORT_L16B_FHO_R1 MTK_M4U_ID(SMI_L16B_ID, 13)
+#define M4U_PORT_L16B_AAO_R1 MTK_M4U_ID(SMI_L16B_ID, 14)
+#define M4U_PORT_L16B_TSFSO_R1 MTK_M4U_ID(SMI_L16B_ID, 15)
+#define M4U_PORT_L16B_FLKO_R1 MTK_M4U_ID(SMI_L16B_ID, 16)
+
+/* LARB 17A -- CAM */
+#define M4U_PORT_L17A_YUVO_R1 MTK_M4U_ID(SMI_L17A_ID, 0)
+#define M4U_PORT_L17A_YUVO_R3 MTK_M4U_ID(SMI_L17A_ID, 1)
+#define M4U_PORT_L17A_YUVCO_R1 MTK_M4U_ID(SMI_L17A_ID, 2)
+#define M4U_PORT_L17A_YUVO_R2 MTK_M4U_ID(SMI_L17A_ID, 3)
+#define M4U_PORT_L17A_RZH1N2TO_R1 MTK_M4U_ID(SMI_L17A_ID, 4)
+#define M4U_PORT_L17A_DRZS4NO_R1 MTK_M4U_ID(SMI_L17A_ID, 5)
+#define M4U_PORT_L17A_TNCSO_R1 MTK_M4U_ID(SMI_L17A_ID, 6)
+
+/* LARB 17B -- CAM */
+#define M4U_PORT_L17B_YUVO_R1 MTK_M4U_ID(SMI_L17B_ID, 0)
+#define M4U_PORT_L17B_YUVO_R3 MTK_M4U_ID(SMI_L17B_ID, 1)
+#define M4U_PORT_L17B_YUVCO_R1 MTK_M4U_ID(SMI_L17B_ID, 2)
+#define M4U_PORT_L17B_YUVO_R2 MTK_M4U_ID(SMI_L17B_ID, 3)
+#define M4U_PORT_L17B_RZH1N2TO_R1 MTK_M4U_ID(SMI_L17B_ID, 4)
+#define M4U_PORT_L17B_DRZS4NO_R1 MTK_M4U_ID(SMI_L17B_ID, 5)
+#define M4U_PORT_L17B_TNCSO_R1 MTK_M4U_ID(SMI_L17B_ID, 6)
+
+/* LARB 19 -- VENC */
+#define M4U_PORT_L19_VENC_RCPU MTK_M4U_ID(SMI_L19_ID, 0)
+#define M4U_PORT_L19_VENC_REC MTK_M4U_ID(SMI_L19_ID, 1)
+#define M4U_PORT_L19_VENC_BSDMA MTK_M4U_ID(SMI_L19_ID, 2)
+#define M4U_PORT_L19_VENC_SV_COMV MTK_M4U_ID(SMI_L19_ID, 3)
+#define M4U_PORT_L19_VENC_RD_COMV MTK_M4U_ID(SMI_L19_ID, 4)
+#define M4U_PORT_L19_VENC_NBM_RDMA MTK_M4U_ID(SMI_L19_ID, 5)
+#define M4U_PORT_L19_VENC_NBM_RDMA_LITE MTK_M4U_ID(SMI_L19_ID, 6)
+#define M4U_PORT_L19_JPGENC_Y_RDMA MTK_M4U_ID(SMI_L19_ID, 7)
+#define M4U_PORT_L19_JPGENC_C_RDMA MTK_M4U_ID(SMI_L19_ID, 8)
+#define M4U_PORT_L19_JPGENC_Q_TABLE MTK_M4U_ID(SMI_L19_ID, 9)
+#define M4U_PORT_L19_VENC_SUB_W_LUMA MTK_M4U_ID(SMI_L19_ID, 10)
+#define M4U_PORT_L19_VENC_FCS_NBM_RDMA MTK_M4U_ID(SMI_L19_ID, 11)
+#define M4U_PORT_L19_JPGENC_BSDMA MTK_M4U_ID(SMI_L19_ID, 12)
+#define M4U_PORT_L19_JPGDEC_WDMA_0 MTK_M4U_ID(SMI_L19_ID, 13)
+#define M4U_PORT_L19_JPGDEC_BSDMA_0 MTK_M4U_ID(SMI_L19_ID, 14)
+#define M4U_PORT_L19_VENC_NBM_WDMA MTK_M4U_ID(SMI_L19_ID, 15)
+#define M4U_PORT_L19_VENC_NBM_WDMA_LITE MTK_M4U_ID(SMI_L19_ID, 16)
+#define M4U_PORT_L19_VENC_FCS_NBM_WDMA MTK_M4U_ID(SMI_L19_ID, 17)
+#define M4U_PORT_L19_JPGDEC_WDMA_1 MTK_M4U_ID(SMI_L19_ID, 18)
+#define M4U_PORT_L19_JPGDEC_BSDMA_1 MTK_M4U_ID(SMI_L19_ID, 19)
+#define M4U_PORT_L19_JPGDEC_HUFF_OFFSET_1 MTK_M4U_ID(SMI_L19_ID, 20)
+#define M4U_PORT_L19_JPGDEC_HUFF_OFFSET_0 MTK_M4U_ID(SMI_L19_ID, 21)
+#define M4U_PORT_L19_VENC_CUR_LUMA MTK_M4U_ID(SMI_L19_ID, 22)
+#define M4U_PORT_L19_VENC_CUR_CHROMA MTK_M4U_ID(SMI_L19_ID, 23)
+#define M4U_PORT_L19_VENC_REF_LUMA MTK_M4U_ID(SMI_L19_ID, 24)
+#define M4U_PORT_L19_VENC_REF_CHROMA MTK_M4U_ID(SMI_L19_ID, 25)
+#define M4U_PORT_L19_VENC_SUB_R_LUMA MTK_M4U_ID(SMI_L19_ID, 26)
+
+/* LARB 21 -- VDEC-CORE0 */
+#define M4U_PORT_L21_HW_VDEC_MC_EXT MTK_M4U_ID(SMI_L21_ID, 0)
+#define M4U_PORT_L21_HW_VDEC_UFO_EXT MTK_M4U_ID(SMI_L21_ID, 1)
+#define M4U_PORT_L21_HW_VDEC_PP_EXT MTK_M4U_ID(SMI_L21_ID, 2)
+#define M4U_PORT_L21_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(SMI_L21_ID, 3)
+#define M4U_PORT_L21_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(SMI_L21_ID, 4)
+#define M4U_PORT_L21_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(SMI_L21_ID, 5)
+#define M4U_PORT_L21_HW_VDEC_TILE_EXT MTK_M4U_ID(SMI_L21_ID, 6)
+#define M4U_PORT_L21_HW_VDEC_VLD_EXT MTK_M4U_ID(SMI_L21_ID, 7)
+#define M4U_PORT_L21_HW_VDEC_VLD2_EXT MTK_M4U_ID(SMI_L21_ID, 8)
+#define M4U_PORT_L21_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(SMI_L21_ID, 9)
+#define M4U_PORT_L21_HW_VDEC_UFO_EXT_C MTK_M4U_ID(SMI_L21_ID, 10)
+
+/* LARB 23 -- VDEC-SOC */
+#define M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT MTK_M4U_ID(SMI_L23_ID, 0)
+#define M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(SMI_L23_ID, 1)
+#define M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT MTK_M4U_ID(SMI_L23_ID, 2)
+#define M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(SMI_L23_ID, 3)
+#define M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT MTK_M4U_ID(SMI_L23_ID, 4)
+#define M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(SMI_L23_ID, 5)
+#define M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(SMI_L23_ID, 6)
+#define M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C MTK_M4U_ID(SMI_L23_ID, 7)
+#define M4U_PORT_L23_HW_VDEC_MC_EXT_C MTK_M4U_ID(SMI_L23_ID, 8)
+
+/* LARB 27 -- CCU */
+#define M4U_PORT_L27_CCUI MTK_M4U_ID(SMI_L27_ID, 0)
+#define M4U_PORT_L27_CCUO MTK_M4U_ID(SMI_L27_ID, 1)
+#define M4U_PORT_L27_CCUI2 MTK_M4U_ID(SMI_L27_ID, 2)
+#define M4U_PORT_L27_CCUO2 MTK_M4U_ID(SMI_L27_ID, 3)
+
+/* LARB 28 -- AXI-CCU */
+#define M4U_PORT_L28_CCU_AXI_0 MTK_M4U_ID(SMI_L28_ID, 0)
+
+/* infra/peri */
+#define IFR_IOMMU_PORT_PCIE_0 MTK_IFAIOMMU_PERI_ID(0)
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH v12 1/7] dt-bindings: mediatek: mt8188: Add binding for MM & INFRA IOMMU
2023-06-02 9:02 ` [PATCH v12 1/7] dt-bindings: mediatek: mt8188: Add binding for MM & INFRA IOMMU Yong Wu
@ 2023-08-17 8:21 ` Chen-Yu Tsai
0 siblings, 0 replies; 25+ messages in thread
From: Chen-Yu Tsai @ 2023-08-17 8:21 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Yong Wu, Joerg Roedel, Will Deacon, Matthias Brugger,
Robin Murphy, Krzysztof Kozlowski, AngeloGioacchino Del Regno,
iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, mingyuan.ma, yf.wang, jianjiao.zeng,
chengci.xu
On Fri, Jun 2, 2023 at 5:03 PM Yong Wu <yong.wu@mediatek.com> wrote:
>
> From: "Chengci.Xu" <chengci.xu@mediatek.com>
>
> Add descriptions for mt8188 IOMMU which also use ARM Short-Descriptor
> translation table format.
>
> In mt8188, there are two smi-common HW and IOMMU, one is for vdo(video
> output), the other is for vpp(video processing pipe). They connects
> with different smi-larbs, then some setting(larbid_remap) is different.
> Differentiate them with the compatible string.
>
> Something like this:
>
> IOMMU(VDO) IOMMU(VPP)
> | |
> SMI_COMMON_VDO SMI_COMMON_VPP
> --------------- ----------------
> | | ... | | ...
> larb0 larb2 ... larb1 larb3 ...
>
> We also have an IOMMU that is for infra master like PCIe.
> And infra master don't have the larb and ports.
>
> Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Question for DT maintainers:
On this new platform, the IOMMU is locked down to secure world in ATF by
setting some registers. Since this is dependent on the firmware, I think
this should be indicated by a new property.
Any ideas? How do other platforms indicate a particular hardware block
is locked down or not accessible by the kernel?
ChenYu
> .../bindings/iommu/mediatek,iommu.yaml | 12 +-
> .../memory/mediatek,mt8188-memory-port.h | 489 ++++++++++++++++++
> 2 files changed, 500 insertions(+), 1 deletion(-)
> create mode 100644 include/dt-bindings/memory/mediatek,mt8188-memory-port.h
>
> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> index 5b6395bc10e0..ea6b0f5f24de 100644
> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> @@ -78,6 +78,9 @@ properties:
> - mediatek,mt8173-m4u # generation two
> - mediatek,mt8183-m4u # generation two
> - mediatek,mt8186-iommu-mm # generation two
> + - mediatek,mt8188-iommu-vdo # generation two
> + - mediatek,mt8188-iommu-vpp # generation two
> + - mediatek,mt8188-iommu-infra # generation two
> - mediatek,mt8192-m4u # generation two
> - mediatek,mt8195-iommu-vdo # generation two
> - mediatek,mt8195-iommu-vpp # generation two
> @@ -123,6 +126,7 @@ properties:
> description: |
> This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as
> defined in
> + dt-binding/memory/mediatek,mt8188-memory-port.h for mt8188,
> dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623,
> dt-binding/memory/mt2712-larb-port.h for mt2712,
> dt-binding/memory/mt6779-larb-port.h for mt6779,
> @@ -155,6 +159,8 @@ allOf:
> - mediatek,mt6795-m4u
> - mediatek,mt8173-m4u
> - mediatek,mt8186-iommu-mm
> + - mediatek,mt8188-iommu-vdo
> + - mediatek,mt8188-iommu-vpp
> - mediatek,mt8192-m4u
> - mediatek,mt8195-iommu-vdo
> - mediatek,mt8195-iommu-vpp
> @@ -168,6 +174,8 @@ allOf:
> compatible:
> enum:
> - mediatek,mt8186-iommu-mm
> + - mediatek,mt8188-iommu-vdo
> + - mediatek,mt8188-iommu-vpp
> - mediatek,mt8192-m4u
> - mediatek,mt8195-iommu-vdo
> - mediatek,mt8195-iommu-vpp
> @@ -194,7 +202,9 @@ allOf:
> properties:
> compatible:
> contains:
> - const: mediatek,mt8195-iommu-infra
> + enum:
> + - mediatek,mt8188-iommu-infra
> + - mediatek,mt8195-iommu-infra
>
> then:
> required:
> diff --git a/include/dt-bindings/memory/mediatek,mt8188-memory-port.h b/include/dt-bindings/memory/mediatek,mt8188-memory-port.h
> new file mode 100644
> index 000000000000..337ab11262af
> --- /dev/null
> +++ b/include/dt-bindings/memory/mediatek,mt8188-memory-port.h
> @@ -0,0 +1,489 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2022 MediaTek Inc.
> + * Author: Chengci Xu <chengci.xu@mediatek.com>
> + */
> +#ifndef _DT_BINDINGS_MEMORY_MEDIATEK_MT8188_LARB_PORT_H_
> +#define _DT_BINDINGS_MEMORY_MEDIATEK_MT8188_LARB_PORT_H_
> +
> +#include <dt-bindings/memory/mtk-memory-port.h>
> +
> +/*
> + * MM IOMMU larbs:
> + * From below, for example larb11 has larb11a/larb11b/larb11c,
> + * the index of larb is not in order. So we reindexed these larbs from a
> + * software view.
> + */
> +#define SMI_L0_ID 0
> +#define SMI_L1_ID 1
> +#define SMI_L2_ID 2
> +#define SMI_L3_ID 3
> +#define SMI_L4_ID 4
> +#define SMI_L5_ID 5
> +#define SMI_L6_ID 6
> +#define SMI_L7_ID 7
> +#define SMI_L9_ID 8
> +#define SMI_L10_ID 9
> +#define SMI_L11A_ID 10
> +#define SMI_L11B_ID 11
> +#define SMI_L11C_ID 12
> +#define SMI_L12_ID 13
> +#define SMI_L13_ID 14
> +#define SMI_L14_ID 15
> +#define SMI_L15_ID 16
> +#define SMI_L16A_ID 17
> +#define SMI_L16B_ID 18
> +#define SMI_L17A_ID 19
> +#define SMI_L17B_ID 20
> +#define SMI_L19_ID 21
> +#define SMI_L21_ID 22
> +#define SMI_L23_ID 23
> +#define SMI_L27_ID 24
> +#define SMI_L28_ID 25
> +
> +/*
> + * MM IOMMU supports 16GB dma address. We separate it to four ranges:
> + * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
> + * locate in anyone region. BUT:
> + * a) Make sure all the ports inside a larb are in one range.
> + * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
> + *
> + * This is the suggested mapping in this SoC:
> + *
> + * modules dma-address-region larbs-ports
> + * disp 0 ~ 4G larb0/1/2/3
> + * vcodec 4G ~ 8G larb19(21)[1]/21(22)/23
> + * cam/mdp 8G ~ 12G the other larbs.
> + * N/A 12G ~ 16G
> + * CCU0 0x24000_0000 ~ 0x243ff_ffff larb27(24): port 0/1
> + * CCU1 0x24400_0000 ~ 0x247ff_ffff larb27(24): port 2/3
> + *
> + * This SoC have two MM IOMMU HWs, this is the connected information:
> + * iommu-vdo: larb0/2/5/9/10/11A/11C/13/16B/17B/19/21
> + * iommu-vpp: larb1/3/4/6/7/11B/12/14/15/16A/17A/23/27
> + *
> + * [1]: This is larb19, but the index is 21 from the SW view.
> + */
> +
> +/* MM IOMMU ports */
> +/* LARB 0 -- VDO-0 */
> +#define M4U_PORT_L0_DISP_RDMA1 MTK_M4U_ID(SMI_L0_ID, 0)
> +#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(SMI_L0_ID, 1)
> +#define M4U_PORT_L0_DISP_OVL0_RDMA0 MTK_M4U_ID(SMI_L0_ID, 2)
> +#define M4U_PORT_L0_DISP_OVL0_RDMA1 MTK_M4U_ID(SMI_L0_ID, 3)
> +#define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_ID(SMI_L0_ID, 4)
> +#define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(SMI_L0_ID, 5)
> +#define M4U_PORT_L0_DISP_FAKE_ENG0 MTK_M4U_ID(SMI_L0_ID, 6)
> +
> +/* LARB 1 -- VD0-0 */
> +#define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_ID(SMI_L1_ID, 0)
> +#define M4U_PORT_L1_DISP_WDMA1 MTK_M4U_ID(SMI_L1_ID, 1)
> +#define M4U_PORT_L1_DISP_OVL1_RDMA0 MTK_M4U_ID(SMI_L1_ID, 2)
> +#define M4U_PORT_L1_DISP_OVL1_RDMA1 MTK_M4U_ID(SMI_L1_ID, 3)
> +#define M4U_PORT_L1_DISP_OVL1_HDR MTK_M4U_ID(SMI_L1_ID, 4)
> +#define M4U_PORT_L1_DISP_WROT0 MTK_M4U_ID(SMI_L1_ID, 5)
> +#define M4U_PORT_L1_DISP_FAKE_ENG1 MTK_M4U_ID(SMI_L1_ID, 6)
> +
> +/* LARB 2 -- VDO-1 */
> +#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(SMI_L2_ID, 0)
> +#define M4U_PORT_L2_MDP_RDMA2 MTK_M4U_ID(SMI_L2_ID, 1)
> +#define M4U_PORT_L2_MDP_RDMA4 MTK_M4U_ID(SMI_L2_ID, 2)
> +#define M4U_PORT_L2_MDP_RDMA6 MTK_M4U_ID(SMI_L2_ID, 3)
> +#define M4U_PORT_L2_DISP_FAKE1 MTK_M4U_ID(SMI_L2_ID, 4)
> +
> +/* LARB 3 -- VDO-1 */
> +#define M4U_PORT_L3_MDP_RDMA1 MTK_M4U_ID(SMI_L3_ID, 0)
> +#define M4U_PORT_L3_MDP_RDMA3 MTK_M4U_ID(SMI_L3_ID, 1)
> +#define M4U_PORT_L3_MDP_RDMA5 MTK_M4U_ID(SMI_L3_ID, 2)
> +#define M4U_PORT_L3_MDP_RDMA7 MTK_M4U_ID(SMI_L3_ID, 3)
> +#define M4U_PORT_L3_HDR_DS_SMI MTK_M4U_ID(SMI_L3_ID, 4)
> +#define M4U_PORT_L3_HDR_ADL_SMI MTK_M4U_ID(SMI_L3_ID, 5)
> +#define M4U_PORT_L3_DISP_FAKE1 MTK_M4U_ID(SMI_L3_ID, 6)
> +
> +/* LARB 4 -- VPP-0 */
> +#define M4U_PORT_L4_MDP_RDMA MTK_M4U_ID(SMI_L4_ID, 0)
> +#define M4U_PORT_L4_MDP_FG MTK_M4U_ID(SMI_L4_ID, 1)
> +#define M4U_PORT_L4_MDP_OVL MTK_M4U_ID(SMI_L4_ID, 2)
> +#define M4U_PORT_L4_MDP_WROT MTK_M4U_ID(SMI_L4_ID, 3)
> +#define M4U_PORT_L4_FAKE_ENG MTK_M4U_ID(SMI_L4_ID, 4)
> +#define M4U_PORT_L4_DISP_RDMA MTK_M4U_ID(SMI_L4_ID, 5)
> +#define M4U_PORT_L4_DISP_WDMA MTK_M4U_ID(SMI_L4_ID, 6)
> +
> +/* LARB 5 -- VPP-1 */
> +#define M4U_PORT_L5_SVPP1_MDP_RDMA MTK_M4U_ID(SMI_L5_ID, 0)
> +#define M4U_PORT_L5_SVPP1_MDP_FG MTK_M4U_ID(SMI_L5_ID, 1)
> +#define M4U_PORT_L5_SVPP1_MDP_OVL MTK_M4U_ID(SMI_L5_ID, 2)
> +#define M4U_PORT_L5_SVPP1_MDP_WROT MTK_M4U_ID(SMI_L5_ID, 3)
> +#define M4U_PORT_L5_SVPP2_MDP_RDMA MTK_M4U_ID(SMI_L5_ID, 4)
> +#define M4U_PORT_L5_SVPP2_MDP_FG MTK_M4U_ID(SMI_L5_ID, 5)
> +#define M4U_PORT_L5_SVPP2_MDP_WROT MTK_M4U_ID(SMI_L5_ID, 6)
> +#define M4U_PORT_L5_LARB5_FAKE_ENG MTK_M4U_ID(SMI_L5_ID, 7)
> +
> +/* LARB 6 -- VPP-1 */
> +#define M4U_PORT_L6_SVPP3_MDP_RDMA MTK_M4U_ID(SMI_L6_ID, 0)
> +#define M4U_PORT_L6_SVPP3_MDP_FG MTK_M4U_ID(SMI_L6_ID, 1)
> +#define M4U_PORT_L6_SVPP3_MDP_WROT MTK_M4U_ID(SMI_L6_ID, 2)
> +#define M4U_PORT_L6_LARB6_FAKE_ENG MTK_M4U_ID(SMI_L6_ID, 3)
> +
> +/* LARB 7 -- WPE */
> +#define M4U_PORT_L7_WPE_RDMA_0 MTK_M4U_ID(SMI_L7_ID, 0)
> +#define M4U_PORT_L7_WPE_RDMA_1 MTK_M4U_ID(SMI_L7_ID, 1)
> +#define M4U_PORT_L7_WPE_WDMA_0 MTK_M4U_ID(SMI_L7_ID, 2)
> +
> +/* LARB 9 -- IMG-M */
> +#define M4U_PORT_L9_IMGI_T1_A MTK_M4U_ID(SMI_L9_ID, 0)
> +#define M4U_PORT_L9_UFDI_T1_A MTK_M4U_ID(SMI_L9_ID, 1)
> +#define M4U_PORT_L9_IMGBI_T1_A MTK_M4U_ID(SMI_L9_ID, 2)
> +#define M4U_PORT_L9_IMGCI_T1_A MTK_M4U_ID(SMI_L9_ID, 3)
> +#define M4U_PORT_L9_SMTI_T1_A MTK_M4U_ID(SMI_L9_ID, 4)
> +#define M4U_PORT_L9_SMTI_T4_A MTK_M4U_ID(SMI_L9_ID, 5)
> +#define M4U_PORT_L9_TNCSTI_T1_A MTK_M4U_ID(SMI_L9_ID, 6)
> +#define M4U_PORT_L9_TNCSTI_T4_A MTK_M4U_ID(SMI_L9_ID, 7)
> +#define M4U_PORT_L9_YUVO_T1_A MTK_M4U_ID(SMI_L9_ID, 8)
> +#define M4U_PORT_L9_YUVBO_T1_A MTK_M4U_ID(SMI_L9_ID, 9)
> +#define M4U_PORT_L9_YUVCO_T1_A MTK_M4U_ID(SMI_L9_ID, 10)
> +#define M4U_PORT_L9_TIMGO_T1_A MTK_M4U_ID(SMI_L9_ID, 11)
> +#define M4U_PORT_L9_YUVO_T2_A MTK_M4U_ID(SMI_L9_ID, 12)
> +#define M4U_PORT_L9_YUVO_T5_A MTK_M4U_ID(SMI_L9_ID, 13)
> +#define M4U_PORT_L9_IMGI_T1_B MTK_M4U_ID(SMI_L9_ID, 14)
> +#define M4U_PORT_L9_IMGBI_T1_B MTK_M4U_ID(SMI_L9_ID, 15)
> +#define M4U_PORT_L9_IMGCI_T1_B MTK_M4U_ID(SMI_L9_ID, 16)
> +#define M4U_PORT_L9_SMTI_T4_B MTK_M4U_ID(SMI_L9_ID, 17)
> +#define M4U_PORT_L9_TNCSO_T1_A MTK_M4U_ID(SMI_L9_ID, 18)
> +#define M4U_PORT_L9_SMTO_T1_A MTK_M4U_ID(SMI_L9_ID, 19)
> +#define M4U_PORT_L9_SMTO_T4_A MTK_M4U_ID(SMI_L9_ID, 20)
> +#define M4U_PORT_L9_TNCSTO_T1_A MTK_M4U_ID(SMI_L9_ID, 21)
> +#define M4U_PORT_L9_YUVO_T2_B MTK_M4U_ID(SMI_L9_ID, 22)
> +#define M4U_PORT_L9_YUVO_T5_B MTK_M4U_ID(SMI_L9_ID, 23)
> +#define M4U_PORT_L9_SMTO_T4_B MTK_M4U_ID(SMI_L9_ID, 24)
> +
> +/* LARB 10 -- IMG-D */
> +#define M4U_PORT_L10_IMGI_D1 MTK_M4U_ID(SMI_L10_ID, 0)
> +#define M4U_PORT_L10_IMGBI_D1 MTK_M4U_ID(SMI_L10_ID, 1)
> +#define M4U_PORT_L10_IMGCI_D1 MTK_M4U_ID(SMI_L10_ID, 2)
> +#define M4U_PORT_L10_IMGDI_D1 MTK_M4U_ID(SMI_L10_ID, 3)
> +#define M4U_PORT_L10_DEPI_D1 MTK_M4U_ID(SMI_L10_ID, 4)
> +#define M4U_PORT_L10_DMGI_D1 MTK_M4U_ID(SMI_L10_ID, 5)
> +#define M4U_PORT_L10_SMTI_D1 MTK_M4U_ID(SMI_L10_ID, 6)
> +#define M4U_PORT_L10_RECI_D1 MTK_M4U_ID(SMI_L10_ID, 7)
> +#define M4U_PORT_L10_RECI_D1_N MTK_M4U_ID(SMI_L10_ID, 8)
> +#define M4U_PORT_L10_TNRWI_D1 MTK_M4U_ID(SMI_L10_ID, 9)
> +#define M4U_PORT_L10_TNRCI_D1 MTK_M4U_ID(SMI_L10_ID, 10)
> +#define M4U_PORT_L10_TNRCI_D1_N MTK_M4U_ID(SMI_L10_ID, 11)
> +#define M4U_PORT_L10_IMG4O_D1 MTK_M4U_ID(SMI_L10_ID, 12)
> +#define M4U_PORT_L10_IMG4BO_D1 MTK_M4U_ID(SMI_L10_ID, 13)
> +#define M4U_PORT_L10_SMTI_D8 MTK_M4U_ID(SMI_L10_ID, 14)
> +#define M4U_PORT_L10_SMTO_D1 MTK_M4U_ID(SMI_L10_ID, 15)
> +#define M4U_PORT_L10_TNRMO_D1 MTK_M4U_ID(SMI_L10_ID, 16)
> +#define M4U_PORT_L10_TNRMO_D1_N MTK_M4U_ID(SMI_L10_ID, 17)
> +#define M4U_PORT_L10_SMTO_D8 MTK_M4U_ID(SMI_L10_ID, 18)
> +#define M4U_PORT_L10_DBGO_D1 MTK_M4U_ID(SMI_L10_ID, 19)
> +
> +/* LARB 11A -- IMG-D */
> +#define M4U_PORT_L11A_WPE_RDMA_0 MTK_M4U_ID(SMI_L11A_ID, 0)
> +#define M4U_PORT_L11A_WPE_RDMA_1 MTK_M4U_ID(SMI_L11A_ID, 1)
> +#define M4U_PORT_L11A_WPE_RDMA_4P_0 MTK_M4U_ID(SMI_L11A_ID, 2)
> +#define M4U_PORT_L11A_WPE_RDMA_4P_1 MTK_M4U_ID(SMI_L11A_ID, 3)
> +#define M4U_PORT_L11A_WPE_CQ0 MTK_M4U_ID(SMI_L11A_ID, 4)
> +#define M4U_PORT_L11A_WPE_CQ1 MTK_M4U_ID(SMI_L11A_ID, 5)
> +#define M4U_PORT_L11A_PIMGI_P1 MTK_M4U_ID(SMI_L11A_ID, 6)
> +#define M4U_PORT_L11A_PIMGBI_P1 MTK_M4U_ID(SMI_L11A_ID, 7)
> +#define M4U_PORT_L11A_PIMGCI_P1 MTK_M4U_ID(SMI_L11A_ID, 8)
> +#define M4U_PORT_L11A_IMGI_T1_C MTK_M4U_ID(SMI_L11A_ID, 9)
> +#define M4U_PORT_L11A_IMGBI_T1_C MTK_M4U_ID(SMI_L11A_ID, 10)
> +#define M4U_PORT_L11A_IMGCI_T1_C MTK_M4U_ID(SMI_L11A_ID, 11)
> +#define M4U_PORT_L11A_SMTI_T1_C MTK_M4U_ID(SMI_L11A_ID, 12)
> +#define M4U_PORT_L11A_SMTI_T4_C MTK_M4U_ID(SMI_L11A_ID, 13)
> +#define M4U_PORT_L11A_SMTI_T6_C MTK_M4U_ID(SMI_L11A_ID, 14)
> +#define M4U_PORT_L11A_YUVO_T1_C MTK_M4U_ID(SMI_L11A_ID, 15)
> +#define M4U_PORT_L11A_YUVBO_T1_C MTK_M4U_ID(SMI_L11A_ID, 16)
> +#define M4U_PORT_L11A_YUVCO_T1_C MTK_M4U_ID(SMI_L11A_ID, 17)
> +#define M4U_PORT_L11A_WPE_WDMA_0 MTK_M4U_ID(SMI_L11A_ID, 18)
> +#define M4U_PORT_L11A_WPE_WDMA_4P_0 MTK_M4U_ID(SMI_L11A_ID, 19)
> +#define M4U_PORT_L11A_WROT_P1 MTK_M4U_ID(SMI_L11A_ID, 20)
> +#define M4U_PORT_L11A_TCCSO_P1 MTK_M4U_ID(SMI_L11A_ID, 21)
> +#define M4U_PORT_L11A_TCCSI_P1 MTK_M4U_ID(SMI_L11A_ID, 22)
> +#define M4U_PORT_L11A_TIMGO_T1_C MTK_M4U_ID(SMI_L11A_ID, 23)
> +#define M4U_PORT_L11A_YUVO_T2_C MTK_M4U_ID(SMI_L11A_ID, 24)
> +#define M4U_PORT_L11A_YUVO_T5_C MTK_M4U_ID(SMI_L11A_ID, 25)
> +#define M4U_PORT_L11A_SMTO_T1_C MTK_M4U_ID(SMI_L11A_ID, 26)
> +#define M4U_PORT_L11A_SMTO_T4_C MTK_M4U_ID(SMI_L11A_ID, 27)
> +#define M4U_PORT_L11A_SMTO_T6_C MTK_M4U_ID(SMI_L11A_ID, 28)
> +#define M4U_PORT_L11A_DBGO_T1_C MTK_M4U_ID(SMI_L11A_ID, 29)
> +
> +/* LARB 11B -- IMG-D */
> +#define M4U_PORT_L11B_WPE_RDMA_0 MTK_M4U_ID(SMI_L11B_ID, 0)
> +#define M4U_PORT_L11B_WPE_RDMA_1 MTK_M4U_ID(SMI_L11B_ID, 1)
> +#define M4U_PORT_L11B_WPE_RDMA_4P_0 MTK_M4U_ID(SMI_L11B_ID, 2)
> +#define M4U_PORT_L11B_WPE_RDMA_4P_1 MTK_M4U_ID(SMI_L11B_ID, 3)
> +#define M4U_PORT_L11B_WPE_CQ0 MTK_M4U_ID(SMI_L11B_ID, 4)
> +#define M4U_PORT_L11B_WPE_CQ1 MTK_M4U_ID(SMI_L11B_ID, 5)
> +#define M4U_PORT_L11B_PIMGI_P1 MTK_M4U_ID(SMI_L11B_ID, 6)
> +#define M4U_PORT_L11B_PIMGBI_P1 MTK_M4U_ID(SMI_L11B_ID, 7)
> +#define M4U_PORT_L11B_PIMGCI_P1 MTK_M4U_ID(SMI_L11B_ID, 8)
> +#define M4U_PORT_L11B_IMGI_T1_C MTK_M4U_ID(SMI_L11B_ID, 9)
> +#define M4U_PORT_L11B_IMGBI_T1_C MTK_M4U_ID(SMI_L11B_ID, 10)
> +#define M4U_PORT_L11B_IMGCI_T1_C MTK_M4U_ID(SMI_L11B_ID, 11)
> +#define M4U_PORT_L11B_SMTI_T1_C MTK_M4U_ID(SMI_L11B_ID, 12)
> +#define M4U_PORT_L11B_SMTI_T4_C MTK_M4U_ID(SMI_L11B_ID, 13)
> +#define M4U_PORT_L11B_SMTI_T6_C MTK_M4U_ID(SMI_L11B_ID, 14)
> +#define M4U_PORT_L11B_YUVO_T1_C MTK_M4U_ID(SMI_L11B_ID, 15)
> +#define M4U_PORT_L11B_YUVBO_T1_C MTK_M4U_ID(SMI_L11B_ID, 16)
> +#define M4U_PORT_L11B_YUVCO_T1_C MTK_M4U_ID(SMI_L11B_ID, 17)
> +#define M4U_PORT_L11B_WPE_WDMA_0 MTK_M4U_ID(SMI_L11B_ID, 18)
> +#define M4U_PORT_L11B_WPE_WDMA_4P_0 MTK_M4U_ID(SMI_L11B_ID, 19)
> +#define M4U_PORT_L11B_WROT_P1 MTK_M4U_ID(SMI_L11B_ID, 20)
> +#define M4U_PORT_L11B_TCCSO_P1 MTK_M4U_ID(SMI_L11B_ID, 21)
> +#define M4U_PORT_L11B_TCCSI_P1 MTK_M4U_ID(SMI_L11B_ID, 22)
> +#define M4U_PORT_L11B_TIMGO_T1_C MTK_M4U_ID(SMI_L11B_ID, 23)
> +#define M4U_PORT_L11B_YUVO_T2_C MTK_M4U_ID(SMI_L11B_ID, 24)
> +#define M4U_PORT_L11B_YUVO_T5_C MTK_M4U_ID(SMI_L11B_ID, 25)
> +#define M4U_PORT_L11B_SMTO_T1_C MTK_M4U_ID(SMI_L11B_ID, 26)
> +#define M4U_PORT_L11B_SMTO_T4_C MTK_M4U_ID(SMI_L11B_ID, 27)
> +#define M4U_PORT_L11B_SMTO_T6_C MTK_M4U_ID(SMI_L11B_ID, 28)
> +#define M4U_PORT_L11B_DBGO_T1_C MTK_M4U_ID(SMI_L11B_ID, 29)
> +
> +/* LARB 11C -- IMG-D */
> +#define M4U_PORT_L11C_WPE_RDMA_0 MTK_M4U_ID(SMI_L11C_ID, 0)
> +#define M4U_PORT_L11C_WPE_RDMA_1 MTK_M4U_ID(SMI_L11C_ID, 1)
> +#define M4U_PORT_L11C_WPE_RDMA_4P_0 MTK_M4U_ID(SMI_L11C_ID, 2)
> +#define M4U_PORT_L11C_WPE_RDMA_4P_1 MTK_M4U_ID(SMI_L11C_ID, 3)
> +#define M4U_PORT_L11C_WPE_CQ0 MTK_M4U_ID(SMI_L11C_ID, 4)
> +#define M4U_PORT_L11C_WPE_CQ1 MTK_M4U_ID(SMI_L11C_ID, 5)
> +#define M4U_PORT_L11C_PIMGI_P1 MTK_M4U_ID(SMI_L11C_ID, 6)
> +#define M4U_PORT_L11C_PIMGBI_P1 MTK_M4U_ID(SMI_L11C_ID, 7)
> +#define M4U_PORT_L11C_PIMGCI_P1 MTK_M4U_ID(SMI_L11C_ID, 8)
> +#define M4U_PORT_L11C_IMGI_T1_C MTK_M4U_ID(SMI_L11C_ID, 9)
> +#define M4U_PORT_L11C_IMGBI_T1_C MTK_M4U_ID(SMI_L11C_ID, 10)
> +#define M4U_PORT_L11C_IMGCI_T1_C MTK_M4U_ID(SMI_L11C_ID, 11)
> +#define M4U_PORT_L11C_SMTI_T1_C MTK_M4U_ID(SMI_L11C_ID, 12)
> +#define M4U_PORT_L11C_SMTI_T4_C MTK_M4U_ID(SMI_L11C_ID, 13)
> +#define M4U_PORT_L11C_SMTI_T6_C MTK_M4U_ID(SMI_L11C_ID, 14)
> +#define M4U_PORT_L11C_YUVO_T1_C MTK_M4U_ID(SMI_L11C_ID, 15)
> +#define M4U_PORT_L11C_YUVBO_T1_C MTK_M4U_ID(SMI_L11C_ID, 16)
> +#define M4U_PORT_L11C_YUVCO_T1_C MTK_M4U_ID(SMI_L11C_ID, 17)
> +#define M4U_PORT_L11C_WPE_WDMA_0 MTK_M4U_ID(SMI_L11C_ID, 18)
> +#define M4U_PORT_L11C_WPE_WDMA_4P_0 MTK_M4U_ID(SMI_L11C_ID, 19)
> +#define M4U_PORT_L11C_WROT_P1 MTK_M4U_ID(SMI_L11C_ID, 20)
> +#define M4U_PORT_L11C_TCCSO_P1 MTK_M4U_ID(SMI_L11C_ID, 21)
> +#define M4U_PORT_L11C_TCCSI_P1 MTK_M4U_ID(SMI_L11C_ID, 22)
> +#define M4U_PORT_L11C_TIMGO_T1_C MTK_M4U_ID(SMI_L11C_ID, 23)
> +#define M4U_PORT_L11C_YUVO_T2_C MTK_M4U_ID(SMI_L11C_ID, 24)
> +#define M4U_PORT_L11C_YUVO_T5_C MTK_M4U_ID(SMI_L11C_ID, 25)
> +#define M4U_PORT_L11C_SMTO_T1_C MTK_M4U_ID(SMI_L11C_ID, 26)
> +#define M4U_PORT_L11C_SMTO_T4_C MTK_M4U_ID(SMI_L11C_ID, 27)
> +#define M4U_PORT_L11C_SMTO_T6_C MTK_M4U_ID(SMI_L11C_ID, 28)
> +#define M4U_PORT_L11C_DBGO_T1_C MTK_M4U_ID(SMI_L11C_ID, 29)
> +
> +/* LARB 12 -- IPE */
> +#define M4U_PORT_L12_FDVT_RDA_0 MTK_M4U_ID(SMI_L12_ID, 0)
> +#define M4U_PORT_L12_FDVT_RDB_0 MTK_M4U_ID(SMI_L12_ID, 1)
> +#define M4U_PORT_L12_FDVT_WRA_0 MTK_M4U_ID(SMI_L12_ID, 2)
> +#define M4U_PORT_L12_FDVT_WRB_0 MTK_M4U_ID(SMI_L12_ID, 3)
> +#define M4U_PORT_L12_ME_RDMA MTK_M4U_ID(SMI_L12_ID, 4)
> +#define M4U_PORT_L12_ME_WDMA MTK_M4U_ID(SMI_L12_ID, 5)
> +#define M4U_PORT_L12_DVS_RDMA MTK_M4U_ID(SMI_L12_ID, 6)
> +#define M4U_PORT_L12_DVS_WDMA MTK_M4U_ID(SMI_L12_ID, 7)
> +#define M4U_PORT_L12_DVP_RDMA MTK_M4U_ID(SMI_L12_ID, 8)
> +#define M4U_PORT_L12_DVP_WDMA MTK_M4U_ID(SMI_L12_ID, 9)
> +#define M4U_PORT_L12_FDVT_2ND_RDA_0 MTK_M4U_ID(SMI_L12_ID, 10)
> +#define M4U_PORT_L12_FDVT_2ND_RDB_0 MTK_M4U_ID(SMI_L12_ID, 11)
> +#define M4U_PORT_L12_FDVT_2ND_WRA_0 MTK_M4U_ID(SMI_L12_ID, 12)
> +#define M4U_PORT_L12_FDVT_2ND_WRB_0 MTK_M4U_ID(SMI_L12_ID, 13)
> +#define M4U_PORT_L12_DHZEI_E1 MTK_M4U_ID(SMI_L12_ID, 14)
> +#define M4U_PORT_L12_DHZEO_E1 MTK_M4U_ID(SMI_L12_ID, 15)
> +
> +/* LARB 13 -- CAM-1 */
> +#define M4U_PORT_L13_CAMSV_CQI_E1 MTK_M4U_ID(SMI_L13_ID, 0)
> +#define M4U_PORT_L13_CAMSV_CQI_E2 MTK_M4U_ID(SMI_L13_ID, 1)
> +#define M4U_PORT_L13_GCAMSV_A_IMGO_1 MTK_M4U_ID(SMI_L13_ID, 2)
> +#define M4U_PORT_L13_GCAMSV_C_IMGO_1 MTK_M4U_ID(SMI_L13_ID, 3)
> +#define M4U_PORT_L13_GCAMSV_A_IMGO_2 MTK_M4U_ID(SMI_L13_ID, 4)
> +#define M4U_PORT_L13_GCAMSV_C_IMGO_2 MTK_M4U_ID(SMI_L13_ID, 5)
> +#define M4U_PORT_L13_PDAI_A_0 MTK_M4U_ID(SMI_L13_ID, 6)
> +#define M4U_PORT_L13_PDAI_A_1 MTK_M4U_ID(SMI_L13_ID, 7)
> +#define M4U_PORT_L13_CAMSV_CQI_B_E1 MTK_M4U_ID(SMI_L13_ID, 8)
> +#define M4U_PORT_L13_CAMSV_CQI_B_E2 MTK_M4U_ID(SMI_L13_ID, 9)
> +#define M4U_PORT_L13_CAMSV_CQI_C_E1 MTK_M4U_ID(SMI_L13_ID, 10)
> +#define M4U_PORT_L13_CAMSV_CQI_C_E2 MTK_M4U_ID(SMI_L13_ID, 11)
> +#define M4U_PORT_L13_GCAMSV_E_IMGO_1 MTK_M4U_ID(SMI_L13_ID, 12)
> +#define M4U_PORT_L13_GCAMSV_E_IMGO_2 MTK_M4U_ID(SMI_L13_ID, 13)
> +#define M4U_PORT_L13_GCAMSV_A_UFEO_1 MTK_M4U_ID(SMI_L13_ID, 14)
> +#define M4U_PORT_L13_GCAMSV_C_UFEO_1 MTK_M4U_ID(SMI_L13_ID, 15)
> +#define M4U_PORT_L13_GCAMSV_A_UFEO_2 MTK_M4U_ID(SMI_L13_ID, 16)
> +#define M4U_PORT_L13_GCAMSV_C_UFEO_2 MTK_M4U_ID(SMI_L13_ID, 17)
> +#define M4U_PORT_L13_GCAMSV_E_UFEO_1 MTK_M4U_ID(SMI_L13_ID, 18)
> +#define M4U_PORT_L13_GCAMSV_E_UFEO_2 MTK_M4U_ID(SMI_L13_ID, 19)
> +#define M4U_PORT_L13_GCAMSV_G_IMGO_1 MTK_M4U_ID(SMI_L13_ID, 20)
> +#define M4U_PORT_L13_GCAMSV_G_IMGO_2 MTK_M4U_ID(SMI_L13_ID, 21)
> +#define M4U_PORT_L13_PDAO_A MTK_M4U_ID(SMI_L13_ID, 22)
> +#define M4U_PORT_L13_PDAO_C MTK_M4U_ID(SMI_L13_ID, 23)
> +
> +/* LARB 14 -- CAM-1 */
> +#define M4U_PORT_L14_GCAMSV_B_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 0)
> +#define M4U_PORT_L14_GCAMSV_B_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 1)
> +#define M4U_PORT_L14_SCAMSV_A_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 2)
> +#define M4U_PORT_L14_SCAMSV_A_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 3)
> +#define M4U_PORT_L14_SCAMSV_B_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 4)
> +#define M4U_PORT_L14_SCAMSV_B_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 5)
> +#define M4U_PORT_L14_PDAI_B_0 MTK_M4U_ID(SMI_L14_ID, 6)
> +#define M4U_PORT_L14_PDAI_B_1 MTK_M4U_ID(SMI_L14_ID, 7)
> +#define M4U_PORT_L14_GCAMSV_D_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 8)
> +#define M4U_PORT_L14_GCAMSV_D_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 9)
> +#define M4U_PORT_L14_GCAMSV_F_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 10)
> +#define M4U_PORT_L14_GCAMSV_F_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 11)
> +#define M4U_PORT_L14_GCAMSV_H_IMGO_1 MTK_M4U_ID(SMI_L14_ID, 12)
> +#define M4U_PORT_L14_GCAMSV_H_IMGO_2 MTK_M4U_ID(SMI_L14_ID, 13)
> +#define M4U_PORT_L14_GCAMSV_B_UFEO_1 MTK_M4U_ID(SMI_L14_ID, 14)
> +#define M4U_PORT_L14_GCAMSV_B_UFEO_2 MTK_M4U_ID(SMI_L14_ID, 15)
> +#define M4U_PORT_L14_GCAMSV_D_UFEO_1 MTK_M4U_ID(SMI_L14_ID, 16)
> +#define M4U_PORT_L14_GCAMSV_D_UFEO_2 MTK_M4U_ID(SMI_L14_ID, 17)
> +#define M4U_PORT_L14_PDAO_B MTK_M4U_ID(SMI_L14_ID, 18)
> +#define M4U_PORT_L14_IPUI MTK_M4U_ID(SMI_L14_ID, 19)
> +#define M4U_PORT_L14_IPUO MTK_M4U_ID(SMI_L14_ID, 20)
> +#define M4U_PORT_L14_IPU3O MTK_M4U_ID(SMI_L14_ID, 21)
> +#define M4U_PORT_L14_FAKE MTK_M4U_ID(SMI_L14_ID, 22)
> +
> +/* LARB 15 -- IMG-D */
> +#define M4U_PORT_L15_VIPI_D1 MTK_M4U_ID(SMI_L15_ID, 0)
> +#define M4U_PORT_L15_VIPBI_D1 MTK_M4U_ID(SMI_L15_ID, 1)
> +#define M4U_PORT_L15_SMTI_D6 MTK_M4U_ID(SMI_L15_ID, 2)
> +#define M4U_PORT_L15_TNCSTI_D1 MTK_M4U_ID(SMI_L15_ID, 3)
> +#define M4U_PORT_L15_TNCSTI_D4 MTK_M4U_ID(SMI_L15_ID, 4)
> +#define M4U_PORT_L15_SMTI_D4 MTK_M4U_ID(SMI_L15_ID, 5)
> +#define M4U_PORT_L15_IMG3O_D1 MTK_M4U_ID(SMI_L15_ID, 6)
> +#define M4U_PORT_L15_IMG3BO_D1 MTK_M4U_ID(SMI_L15_ID, 7)
> +#define M4U_PORT_L15_IMG3CO_D1 MTK_M4U_ID(SMI_L15_ID, 8)
> +#define M4U_PORT_L15_IMG2O_D1 MTK_M4U_ID(SMI_L15_ID, 9)
> +#define M4U_PORT_L15_SMTI_D9 MTK_M4U_ID(SMI_L15_ID, 10)
> +#define M4U_PORT_L15_SMTO_D4 MTK_M4U_ID(SMI_L15_ID, 11)
> +#define M4U_PORT_L15_FEO_D1 MTK_M4U_ID(SMI_L15_ID, 12)
> +#define M4U_PORT_L15_TNCSO_D1 MTK_M4U_ID(SMI_L15_ID, 13)
> +#define M4U_PORT_L15_TNCSTO_D1 MTK_M4U_ID(SMI_L15_ID, 14)
> +#define M4U_PORT_L15_SMTO_D6 MTK_M4U_ID(SMI_L15_ID, 15)
> +#define M4U_PORT_L15_SMTO_D9 MTK_M4U_ID(SMI_L15_ID, 16)
> +#define M4U_PORT_L15_TNCO_D1 MTK_M4U_ID(SMI_L15_ID, 17)
> +#define M4U_PORT_L15_TNCO_D1_N MTK_M4U_ID(SMI_L15_ID, 18)
> +
> +/* LARB 16A -- CAM */
> +#define M4U_PORT_L16A_IMGO_R1 MTK_M4U_ID(SMI_L16A_ID, 0)
> +#define M4U_PORT_L16A_CQI_R1 MTK_M4U_ID(SMI_L16A_ID, 1)
> +#define M4U_PORT_L16A_CQI_R2 MTK_M4U_ID(SMI_L16A_ID, 2)
> +#define M4U_PORT_L16A_BPCI_R1 MTK_M4U_ID(SMI_L16A_ID, 3)
> +#define M4U_PORT_L16A_LSCI_R1 MTK_M4U_ID(SMI_L16A_ID, 4)
> +#define M4U_PORT_L16A_RAWI_R2 MTK_M4U_ID(SMI_L16A_ID, 5)
> +#define M4U_PORT_L16A_RAWI_R3 MTK_M4U_ID(SMI_L16A_ID, 6)
> +#define M4U_PORT_L16A_UFDI_R2 MTK_M4U_ID(SMI_L16A_ID, 7)
> +#define M4U_PORT_L16A_UFDI_R3 MTK_M4U_ID(SMI_L16A_ID, 8)
> +#define M4U_PORT_L16A_RAWI_R4 MTK_M4U_ID(SMI_L16A_ID, 9)
> +#define M4U_PORT_L16A_RAWI_R5 MTK_M4U_ID(SMI_L16A_ID, 10)
> +#define M4U_PORT_L16A_AAI_R1 MTK_M4U_ID(SMI_L16A_ID, 11)
> +#define M4U_PORT_L16A_UFDI_R5 MTK_M4U_ID(SMI_L16A_ID, 12)
> +#define M4U_PORT_L16A_FHO_R1 MTK_M4U_ID(SMI_L16A_ID, 13)
> +#define M4U_PORT_L16A_AAO_R1 MTK_M4U_ID(SMI_L16A_ID, 14)
> +#define M4U_PORT_L16A_TSFSO_R1 MTK_M4U_ID(SMI_L16A_ID, 15)
> +#define M4U_PORT_L16A_FLKO_R1 MTK_M4U_ID(SMI_L16A_ID, 16)
> +
> +/* LARB 16B -- CAM */
> +#define M4U_PORT_L16B_IMGO_R1 MTK_M4U_ID(SMI_L16B_ID, 0)
> +#define M4U_PORT_L16B_CQI_R1 MTK_M4U_ID(SMI_L16B_ID, 1)
> +#define M4U_PORT_L16B_CQI_R2 MTK_M4U_ID(SMI_L16B_ID, 2)
> +#define M4U_PORT_L16B_BPCI_R1 MTK_M4U_ID(SMI_L16B_ID, 3)
> +#define M4U_PORT_L16B_LSCI_R1 MTK_M4U_ID(SMI_L16B_ID, 4)
> +#define M4U_PORT_L16B_RAWI_R2 MTK_M4U_ID(SMI_L16B_ID, 5)
> +#define M4U_PORT_L16B_RAWI_R3 MTK_M4U_ID(SMI_L16B_ID, 6)
> +#define M4U_PORT_L16B_UFDI_R2 MTK_M4U_ID(SMI_L16B_ID, 7)
> +#define M4U_PORT_L16B_UFDI_R3 MTK_M4U_ID(SMI_L16B_ID, 8)
> +#define M4U_PORT_L16B_RAWI_R4 MTK_M4U_ID(SMI_L16B_ID, 9)
> +#define M4U_PORT_L16B_RAWI_R5 MTK_M4U_ID(SMI_L16B_ID, 10)
> +#define M4U_PORT_L16B_AAI_R1 MTK_M4U_ID(SMI_L16B_ID, 11)
> +#define M4U_PORT_L16B_UFDI_R5 MTK_M4U_ID(SMI_L16B_ID, 12)
> +#define M4U_PORT_L16B_FHO_R1 MTK_M4U_ID(SMI_L16B_ID, 13)
> +#define M4U_PORT_L16B_AAO_R1 MTK_M4U_ID(SMI_L16B_ID, 14)
> +#define M4U_PORT_L16B_TSFSO_R1 MTK_M4U_ID(SMI_L16B_ID, 15)
> +#define M4U_PORT_L16B_FLKO_R1 MTK_M4U_ID(SMI_L16B_ID, 16)
> +
> +/* LARB 17A -- CAM */
> +#define M4U_PORT_L17A_YUVO_R1 MTK_M4U_ID(SMI_L17A_ID, 0)
> +#define M4U_PORT_L17A_YUVO_R3 MTK_M4U_ID(SMI_L17A_ID, 1)
> +#define M4U_PORT_L17A_YUVCO_R1 MTK_M4U_ID(SMI_L17A_ID, 2)
> +#define M4U_PORT_L17A_YUVO_R2 MTK_M4U_ID(SMI_L17A_ID, 3)
> +#define M4U_PORT_L17A_RZH1N2TO_R1 MTK_M4U_ID(SMI_L17A_ID, 4)
> +#define M4U_PORT_L17A_DRZS4NO_R1 MTK_M4U_ID(SMI_L17A_ID, 5)
> +#define M4U_PORT_L17A_TNCSO_R1 MTK_M4U_ID(SMI_L17A_ID, 6)
> +
> +/* LARB 17B -- CAM */
> +#define M4U_PORT_L17B_YUVO_R1 MTK_M4U_ID(SMI_L17B_ID, 0)
> +#define M4U_PORT_L17B_YUVO_R3 MTK_M4U_ID(SMI_L17B_ID, 1)
> +#define M4U_PORT_L17B_YUVCO_R1 MTK_M4U_ID(SMI_L17B_ID, 2)
> +#define M4U_PORT_L17B_YUVO_R2 MTK_M4U_ID(SMI_L17B_ID, 3)
> +#define M4U_PORT_L17B_RZH1N2TO_R1 MTK_M4U_ID(SMI_L17B_ID, 4)
> +#define M4U_PORT_L17B_DRZS4NO_R1 MTK_M4U_ID(SMI_L17B_ID, 5)
> +#define M4U_PORT_L17B_TNCSO_R1 MTK_M4U_ID(SMI_L17B_ID, 6)
> +
> +/* LARB 19 -- VENC */
> +#define M4U_PORT_L19_VENC_RCPU MTK_M4U_ID(SMI_L19_ID, 0)
> +#define M4U_PORT_L19_VENC_REC MTK_M4U_ID(SMI_L19_ID, 1)
> +#define M4U_PORT_L19_VENC_BSDMA MTK_M4U_ID(SMI_L19_ID, 2)
> +#define M4U_PORT_L19_VENC_SV_COMV MTK_M4U_ID(SMI_L19_ID, 3)
> +#define M4U_PORT_L19_VENC_RD_COMV MTK_M4U_ID(SMI_L19_ID, 4)
> +#define M4U_PORT_L19_VENC_NBM_RDMA MTK_M4U_ID(SMI_L19_ID, 5)
> +#define M4U_PORT_L19_VENC_NBM_RDMA_LITE MTK_M4U_ID(SMI_L19_ID, 6)
> +#define M4U_PORT_L19_JPGENC_Y_RDMA MTK_M4U_ID(SMI_L19_ID, 7)
> +#define M4U_PORT_L19_JPGENC_C_RDMA MTK_M4U_ID(SMI_L19_ID, 8)
> +#define M4U_PORT_L19_JPGENC_Q_TABLE MTK_M4U_ID(SMI_L19_ID, 9)
> +#define M4U_PORT_L19_VENC_SUB_W_LUMA MTK_M4U_ID(SMI_L19_ID, 10)
> +#define M4U_PORT_L19_VENC_FCS_NBM_RDMA MTK_M4U_ID(SMI_L19_ID, 11)
> +#define M4U_PORT_L19_JPGENC_BSDMA MTK_M4U_ID(SMI_L19_ID, 12)
> +#define M4U_PORT_L19_JPGDEC_WDMA_0 MTK_M4U_ID(SMI_L19_ID, 13)
> +#define M4U_PORT_L19_JPGDEC_BSDMA_0 MTK_M4U_ID(SMI_L19_ID, 14)
> +#define M4U_PORT_L19_VENC_NBM_WDMA MTK_M4U_ID(SMI_L19_ID, 15)
> +#define M4U_PORT_L19_VENC_NBM_WDMA_LITE MTK_M4U_ID(SMI_L19_ID, 16)
> +#define M4U_PORT_L19_VENC_FCS_NBM_WDMA MTK_M4U_ID(SMI_L19_ID, 17)
> +#define M4U_PORT_L19_JPGDEC_WDMA_1 MTK_M4U_ID(SMI_L19_ID, 18)
> +#define M4U_PORT_L19_JPGDEC_BSDMA_1 MTK_M4U_ID(SMI_L19_ID, 19)
> +#define M4U_PORT_L19_JPGDEC_HUFF_OFFSET_1 MTK_M4U_ID(SMI_L19_ID, 20)
> +#define M4U_PORT_L19_JPGDEC_HUFF_OFFSET_0 MTK_M4U_ID(SMI_L19_ID, 21)
> +#define M4U_PORT_L19_VENC_CUR_LUMA MTK_M4U_ID(SMI_L19_ID, 22)
> +#define M4U_PORT_L19_VENC_CUR_CHROMA MTK_M4U_ID(SMI_L19_ID, 23)
> +#define M4U_PORT_L19_VENC_REF_LUMA MTK_M4U_ID(SMI_L19_ID, 24)
> +#define M4U_PORT_L19_VENC_REF_CHROMA MTK_M4U_ID(SMI_L19_ID, 25)
> +#define M4U_PORT_L19_VENC_SUB_R_LUMA MTK_M4U_ID(SMI_L19_ID, 26)
> +
> +/* LARB 21 -- VDEC-CORE0 */
> +#define M4U_PORT_L21_HW_VDEC_MC_EXT MTK_M4U_ID(SMI_L21_ID, 0)
> +#define M4U_PORT_L21_HW_VDEC_UFO_EXT MTK_M4U_ID(SMI_L21_ID, 1)
> +#define M4U_PORT_L21_HW_VDEC_PP_EXT MTK_M4U_ID(SMI_L21_ID, 2)
> +#define M4U_PORT_L21_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(SMI_L21_ID, 3)
> +#define M4U_PORT_L21_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(SMI_L21_ID, 4)
> +#define M4U_PORT_L21_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(SMI_L21_ID, 5)
> +#define M4U_PORT_L21_HW_VDEC_TILE_EXT MTK_M4U_ID(SMI_L21_ID, 6)
> +#define M4U_PORT_L21_HW_VDEC_VLD_EXT MTK_M4U_ID(SMI_L21_ID, 7)
> +#define M4U_PORT_L21_HW_VDEC_VLD2_EXT MTK_M4U_ID(SMI_L21_ID, 8)
> +#define M4U_PORT_L21_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(SMI_L21_ID, 9)
> +#define M4U_PORT_L21_HW_VDEC_UFO_EXT_C MTK_M4U_ID(SMI_L21_ID, 10)
> +
> +/* LARB 23 -- VDEC-SOC */
> +#define M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT MTK_M4U_ID(SMI_L23_ID, 0)
> +#define M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(SMI_L23_ID, 1)
> +#define M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT MTK_M4U_ID(SMI_L23_ID, 2)
> +#define M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(SMI_L23_ID, 3)
> +#define M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT MTK_M4U_ID(SMI_L23_ID, 4)
> +#define M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(SMI_L23_ID, 5)
> +#define M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(SMI_L23_ID, 6)
> +#define M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C MTK_M4U_ID(SMI_L23_ID, 7)
> +#define M4U_PORT_L23_HW_VDEC_MC_EXT_C MTK_M4U_ID(SMI_L23_ID, 8)
> +
> +/* LARB 27 -- CCU */
> +#define M4U_PORT_L27_CCUI MTK_M4U_ID(SMI_L27_ID, 0)
> +#define M4U_PORT_L27_CCUO MTK_M4U_ID(SMI_L27_ID, 1)
> +#define M4U_PORT_L27_CCUI2 MTK_M4U_ID(SMI_L27_ID, 2)
> +#define M4U_PORT_L27_CCUO2 MTK_M4U_ID(SMI_L27_ID, 3)
> +
> +/* LARB 28 -- AXI-CCU */
> +#define M4U_PORT_L28_CCU_AXI_0 MTK_M4U_ID(SMI_L28_ID, 0)
> +
> +/* infra/peri */
> +#define IFR_IOMMU_PORT_PCIE_0 MTK_IFAIOMMU_PERI_ID(0)
> +
> +#endif
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v12 2/7] iommu/mediatek: Fix two IOMMU share pagetable issue
2023-06-02 9:02 [PATCH v12 0/7] MT8188 IOMMU SUPPORT Yong Wu
2023-06-02 9:02 ` [PATCH v12 1/7] dt-bindings: mediatek: mt8188: Add binding for MM & INFRA IOMMU Yong Wu
@ 2023-06-02 9:02 ` Yong Wu
2023-06-06 13:59 ` Alexandre Mergnat
2023-08-18 15:41 ` Laura Nao
2023-06-02 9:02 ` [PATCH v12 3/7] iommu/mediatek: Adjust mtk_iommu_config flow Yong Wu
` (5 subsequent siblings)
7 siblings, 2 replies; 25+ messages in thread
From: Yong Wu @ 2023-06-02 9:02 UTC (permalink / raw)
To: Joerg Roedel, Will Deacon, Rob Herring, Matthias Brugger
Cc: Robin Murphy, Krzysztof Kozlowski, Yong Wu,
AngeloGioacchino Del Regno, iommu, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, mingyuan.ma, yf.wang,
jianjiao.zeng, chengci.xu
From: "Chengci.Xu" <chengci.xu@mediatek.com>
Prepare for mt8188 to fix a two IOMMU HWs share pagetable issue.
We have two MM IOMMU HWs in mt8188, one is VPP-IOMMU, the other is
VDO-IOMMU. The 2 MM IOMMU HWs share pagetable don't work in this case:
a) VPP-IOMMU probe firstly.
b) VDO-IOMMU probe.
c) The master for VDO-IOMMU probe (means frstdata is vpp-iommu).
d) The master in another domain probe. No matter it is vdo or vpp.
Then it still create a new pagetable in step d). The problem is
"frstdata->bank[0]->m4u_dom" was not initialized. Then when d) enter, it
still create a new one.
In this patch, we create a new variable "share_dom" for this share
pgtable case, it should be helpful for readable. and put all the share
pgtable logic in the mtk_iommu_domain_finalise.
In mt8195, the master of VPP-IOMMU probes before than VDO-IOMMU
from its dtsi node sequence, we don't see this issue in it. Prepare for
mt8188.
Fixes: 645b87c190c9 ("iommu/mediatek: Fix 2 HW sharing pgtable issue")
Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/iommu/mtk_iommu.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index aecc7d154f28..7287be67bd1f 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -258,6 +258,8 @@ struct mtk_iommu_data {
struct device *smicomm_dev;
struct mtk_iommu_bank_data *bank;
+ struct mtk_iommu_domain *share_dom; /* For 2 HWs share pgtable */
+
struct regmap *pericfg;
struct mutex mutex; /* Protect m4u_group/m4u_dom above */
@@ -620,15 +622,14 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
struct mtk_iommu_data *data,
unsigned int region_id)
{
+ struct mtk_iommu_domain *share_dom = data->share_dom;
const struct mtk_iommu_iova_region *region;
- struct mtk_iommu_domain *m4u_dom;
-
- /* Always use bank0 in sharing pgtable case */
- m4u_dom = data->bank[0].m4u_dom;
- if (m4u_dom) {
- dom->iop = m4u_dom->iop;
- dom->cfg = m4u_dom->cfg;
- dom->domain.pgsize_bitmap = m4u_dom->cfg.pgsize_bitmap;
+
+ /* Always use share domain in sharing pgtable case */
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE) && share_dom) {
+ dom->iop = share_dom->iop;
+ dom->cfg = share_dom->cfg;
+ dom->domain.pgsize_bitmap = share_dom->cfg.pgsize_bitmap;
goto update_iova_region;
}
@@ -658,6 +659,9 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
/* Update our support page sizes bitmap */
dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap;
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, SHARE_PGTABLE))
+ data->share_dom = dom;
+
update_iova_region:
/* Update the iova region for this domain */
region = data->plat_data->iova_region + region_id;
@@ -708,7 +712,9 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
/* Data is in the frstdata in sharing pgtable case. */
frstdata = mtk_iommu_get_frst_data(hw_list);
+ mutex_lock(&frstdata->mutex);
ret = mtk_iommu_domain_finalise(dom, frstdata, region_id);
+ mutex_unlock(&frstdata->mutex);
if (ret) {
mutex_unlock(&dom->mutex);
return ret;
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH v12 2/7] iommu/mediatek: Fix two IOMMU share pagetable issue
2023-06-02 9:02 ` [PATCH v12 2/7] iommu/mediatek: Fix two IOMMU share pagetable issue Yong Wu
@ 2023-06-06 13:59 ` Alexandre Mergnat
2023-08-18 15:41 ` Laura Nao
1 sibling, 0 replies; 25+ messages in thread
From: Alexandre Mergnat @ 2023-06-06 13:59 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Rob Herring, Matthias Brugger
Cc: Robin Murphy, Krzysztof Kozlowski, AngeloGioacchino Del Regno,
iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, mingyuan.ma, yf.wang, jianjiao.zeng,
chengci.xu
On 02/06/2023 11:02, Yong Wu wrote:
> Prepare for mt8188 to fix a two IOMMU HWs share pagetable issue.
>
> We have two MM IOMMU HWs in mt8188, one is VPP-IOMMU, the other is
> VDO-IOMMU. The 2 MM IOMMU HWs share pagetable don't work in this case:
> a) VPP-IOMMU probe firstly.
> b) VDO-IOMMU probe.
> c) The master for VDO-IOMMU probe (means frstdata is vpp-iommu).
> d) The master in another domain probe. No matter it is vdo or vpp.
> Then it still create a new pagetable in step d). The problem is
> "frstdata->bank[0]->m4u_dom" was not initialized. Then when d) enter, it
> still create a new one.
>
> In this patch, we create a new variable "share_dom" for this share
> pgtable case, it should be helpful for readable. and put all the share
> pgtable logic in the mtk_iommu_domain_finalise.
>
> In mt8195, the master of VPP-IOMMU probes before than VDO-IOMMU
> from its dtsi node sequence, we don't see this issue in it. Prepare for
> mt8188.
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
--
Regards,
Alexandre
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v12 2/7] iommu/mediatek: Fix two IOMMU share pagetable issue
2023-06-02 9:02 ` [PATCH v12 2/7] iommu/mediatek: Fix two IOMMU share pagetable issue Yong Wu
2023-06-06 13:59 ` Alexandre Mergnat
@ 2023-08-18 15:41 ` Laura Nao
2023-08-19 8:45 ` Yong Wu (吴勇)
1 sibling, 1 reply; 25+ messages in thread
From: Laura Nao @ 2023-08-18 15:41 UTC (permalink / raw)
To: yong.wu
Cc: angelogioacchino.delregno, chengci.xu, devicetree, iommu,
jianjiao.zeng, joro, krzysztof.kozlowski+dt, linux-arm-kernel,
linux-kernel, linux-mediatek, matthias.bgg, mingyuan.ma, robh+dt,
robin.murphy, will, yf.wang, kernel
Hello,
This patch is causing fluster tests to fail on MT8192, IOMMU read and write faults are reported in the log. Here's an extract is from the VP9 tests:
mtk-iommu 1401d000.m4u: fault type=0x280 iova=0x1ff7c0000 pa=0x0 master=0x5000480(larb=5 port=0) layer=0 read
mtk-iommu 1401d000.m4u: fault type=0x280 iova=0x1fe3ee000 pa=0x0 master=0x5000492(larb=5 port=4) layer=0 write
Tests are failing for H264, VP8 and VP9 decoding on next-20230817 with fluster in the same way, complete logs can be found here:
- H264: https://storage.kernelci.org/next/master/next-20230817/arm64/defconfig+arm64-chromebook+videodec/gcc-10/lab-collabora/v4l2-decoder-conformance-h264-mt8192-asurada-spherion-r0.html
- VP8: https://storage.kernelci.org/next/master/next-20230817/arm64/defconfig+arm64-chromebook+videodec/gcc-10/lab-collabora/v4l2-decoder-conformance-vp8-mt8192-asurada-spherion-r0.html
- VP9: https://storage.kernelci.org/next/master/next-20230817/arm64/defconfig+arm64-chromebook+videodec/gcc-10/lab-collabora/v4l2-decoder-conformance-vp9-mt8192-asurada-spherion-r0.html
Reverting this patch fixes the issue.
From my understanding, on MT8192 the 16GB iova space is partitioned between display, vcodec and camera. The iommu domain configuration for vcodec was loaded from frstdata->bank[0]->m4u_dom (vcodec is preassigned to a specific iova range), while after this patch a new pagetable is created instead.
Do you have any insight on how to fix this while keeping compatibility with MT8188 and MT8195?
Best,
Laura
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v12 2/7] iommu/mediatek: Fix two IOMMU share pagetable issue
2023-08-18 15:41 ` Laura Nao
@ 2023-08-19 8:45 ` Yong Wu (吴勇)
0 siblings, 0 replies; 25+ messages in thread
From: Yong Wu (吴勇) @ 2023-08-19 8:45 UTC (permalink / raw)
To: laura.nao
Cc: linux-kernel, linux-mediatek, robh+dt, devicetree,
Jianjiao Zeng (曾健姣),
kernel, robin.murphy, joro, Chengci Xu (许承赐),
YF Wang (王云飞),
linux-arm-kernel, krzysztof.kozlowski+dt, iommu, matthias.bgg,
Mingyuan Ma (马鸣远),
angelogioacchino.delregno, will
Hi Laura,
Thanks very much for your testing.
On Fri, 2023-08-18 at 17:41 +0200, Laura Nao wrote:
> Hello,
>
> This patch is causing fluster tests to fail on MT8192, IOMMU read and
> write faults are reported in the log. Here's an extract is from the
> VP9 tests:
>
> mtk-iommu 1401d000.m4u: fault type=0x280 iova=0x1ff7c0000 pa=0x0
> master=0x5000480(larb=5 port=0) layer=0 read
> mtk-iommu 1401d000.m4u: fault type=0x280 iova=0x1fe3ee000 pa=0x0
> master=0x5000492(larb=5 port=4) layer=0 write
>
> Tests are failing for H264, VP8 and VP9 decoding on next-20230817
> with fluster in the same way, complete logs can be found here:
> - H264:
> https://urldefense.com/v3/__https://storage.kernelci.org/next/master/next-20230817/arm64/defconfig*arm64-chromebook*videodec/gcc-10/lab-collabora/v4l2-decoder-conformance-h264-mt8192-asurada-spherion-r0.html__;Kys!!CTRNKA9wMg0ARbw!g5CkV4Tmx8gZ_Ll6AMpoEosTjSgKbdfG2RNwJJFdnpX4g-MW0IdAmt3bXphiIIfSPmGbbPO1tFM4b8wSlrgogw$
>
> - VP8:
> https://urldefense.com/v3/__https://storage.kernelci.org/next/master/next-20230817/arm64/defconfig*arm64-chromebook*videodec/gcc-10/lab-collabora/v4l2-decoder-conformance-vp8-mt8192-asurada-spherion-r0.html__;Kys!!CTRNKA9wMg0ARbw!g5CkV4Tmx8gZ_Ll6AMpoEosTjSgKbdfG2RNwJJFdnpX4g-MW0IdAmt3bXphiIIfSPmGbbPO1tFM4b8wa_83EZw$
>
> - VP9:
> https://urldefense.com/v3/__https://storage.kernelci.org/next/master/next-20230817/arm64/defconfig*arm64-chromebook*videodec/gcc-10/lab-collabora/v4l2-decoder-conformance-vp9-mt8192-asurada-spherion-r0.html__;Kys!!CTRNKA9wMg0ARbw!g5CkV4Tmx8gZ_Ll6AMpoEosTjSgKbdfG2RNwJJFdnpX4g-MW0IdAmt3bXphiIIfSPmGbbPO1tFM4b8xaOT2SLw$
>
>
> Reverting this patch fixes the issue.
>
> From my understanding, on MT8192 the 16GB iova space is partitioned
> between display, vcodec and camera. The iommu domain configuration
> for vcodec was loaded from frstdata->bank[0]->m4u_dom (vcodec is
> preassigned to a specific iova range), while after this patch a new
> pagetable is created instead.
Exactly Right. It creates a new pagetable for this case. I sent a patch
for this. Could you also help confirm?
Thanks.
https://lore.kernel.org/linux-mediatek/20230819081443.8333-1-yong.wu@mediatek.com/
>
> Do you have any insight on how to fix this while keeping
> compatibility with MT8188 and MT8195?
>
> Best,
>
> Laura
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v12 3/7] iommu/mediatek: Adjust mtk_iommu_config flow
2023-06-02 9:02 [PATCH v12 0/7] MT8188 IOMMU SUPPORT Yong Wu
2023-06-02 9:02 ` [PATCH v12 1/7] dt-bindings: mediatek: mt8188: Add binding for MM & INFRA IOMMU Yong Wu
2023-06-02 9:02 ` [PATCH v12 2/7] iommu/mediatek: Fix two IOMMU share pagetable issue Yong Wu
@ 2023-06-02 9:02 ` Yong Wu
2023-06-06 14:00 ` Alexandre Mergnat
2023-06-02 9:02 ` [PATCH v12 4/7] iommu/mediatek: Add enable IOMMU SMC command for INFRA masters Yong Wu
` (4 subsequent siblings)
7 siblings, 1 reply; 25+ messages in thread
From: Yong Wu @ 2023-06-02 9:02 UTC (permalink / raw)
To: Joerg Roedel, Will Deacon, Rob Herring, Matthias Brugger
Cc: Robin Murphy, Krzysztof Kozlowski, Yong Wu,
AngeloGioacchino Del Regno, iommu, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, mingyuan.ma, yf.wang,
jianjiao.zeng, chengci.xu
From: "Chengci.Xu" <chengci.xu@mediatek.com>
If there are many ports in a infra master, current flow will update
the INFRA register many times. This patch saves all ports to portid_msk
in the front of mtk_iommu_config(), then update only once for the IOMMU
configure. After this, we could avoid send too many SMC calls to ATF in
MT8188.
Prepare for MT8188, also reduce the indention without functional change.
Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/iommu/mtk_iommu.c | 58 +++++++++++++++++++++------------------
1 file changed, 32 insertions(+), 26 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 7287be67bd1f..8cff85615d5e 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -579,41 +579,47 @@ static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
unsigned int larbid, portid;
struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
const struct mtk_iommu_iova_region *region;
- u32 peri_mmuen, peri_mmuen_msk;
+ unsigned long portid_msk = 0;
int i, ret = 0;
for (i = 0; i < fwspec->num_ids; ++i) {
- larbid = MTK_M4U_TO_LARB(fwspec->ids[i]);
portid = MTK_M4U_TO_PORT(fwspec->ids[i]);
+ portid_msk |= BIT(portid);
+ }
- if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
- larb_mmu = &data->larb_imu[larbid];
+ if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) {
+ /* All ports should be in the same larb. just use 0 here */
+ larbid = MTK_M4U_TO_LARB(fwspec->ids[0]);
+ larb_mmu = &data->larb_imu[larbid];
+ region = data->plat_data->iova_region + regionid;
- region = data->plat_data->iova_region + regionid;
+ for_each_set_bit(portid, &portid_msk, 32)
larb_mmu->bank[portid] = upper_32_bits(region->iova_base);
- dev_dbg(dev, "%s iommu for larb(%s) port %d region %d rgn-bank %d.\n",
- enable ? "enable" : "disable", dev_name(larb_mmu->dev),
- portid, regionid, larb_mmu->bank[portid]);
-
- if (enable)
- larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
- else
- larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
- } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
- peri_mmuen_msk = BIT(portid);
- /* PCI dev has only one output id, enable the next writing bit for PCIe */
- if (dev_is_pci(dev))
- peri_mmuen_msk |= BIT(portid + 1);
-
- peri_mmuen = enable ? peri_mmuen_msk : 0;
- ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1,
- peri_mmuen_msk, peri_mmuen);
- if (ret)
- dev_err(dev, "%s iommu(%s) inframaster 0x%x fail(%d).\n",
- enable ? "enable" : "disable",
- dev_name(data->dev), peri_mmuen_msk, ret);
+ dev_dbg(dev, "%s iommu for larb(%s) port 0x%lx region %d rgn-bank %d.\n",
+ enable ? "enable" : "disable", dev_name(larb_mmu->dev),
+ portid_msk, regionid, upper_32_bits(region->iova_base));
+
+ if (enable)
+ larb_mmu->mmu |= portid_msk;
+ else
+ larb_mmu->mmu &= ~portid_msk;
+ } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
+ /* PCI dev has only one output id, enable the next writing bit for PCIe */
+ if (dev_is_pci(dev)) {
+ if (fwspec->num_ids != 1) {
+ dev_err(dev, "PCI dev can only have one port.\n");
+ return -ENODEV;
+ }
+ portid_msk |= BIT(portid + 1);
}
+
+ ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1,
+ (u32)portid_msk, enable ? (u32)portid_msk : 0);
+ if (ret)
+ dev_err(dev, "%s iommu(%s) inframaster 0x%lx fail(%d).\n",
+ enable ? "enable" : "disable",
+ dev_name(data->dev), portid_msk, ret);
}
return ret;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH v12 3/7] iommu/mediatek: Adjust mtk_iommu_config flow
2023-06-02 9:02 ` [PATCH v12 3/7] iommu/mediatek: Adjust mtk_iommu_config flow Yong Wu
@ 2023-06-06 14:00 ` Alexandre Mergnat
0 siblings, 0 replies; 25+ messages in thread
From: Alexandre Mergnat @ 2023-06-06 14:00 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Rob Herring, Matthias Brugger
Cc: Robin Murphy, Krzysztof Kozlowski, AngeloGioacchino Del Regno,
iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, mingyuan.ma, yf.wang, jianjiao.zeng,
chengci.xu
On 02/06/2023 11:02, Yong Wu wrote:
> If there are many ports in a infra master, current flow will update
> the INFRA register many times. This patch saves all ports to portid_msk
> in the front of mtk_iommu_config(), then update only once for the IOMMU
> configure. After this, we could avoid send too many SMC calls to ATF in
> MT8188.
>
> Prepare for MT8188, also reduce the indention without functional change.
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
--
Regards,
Alexandre
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v12 4/7] iommu/mediatek: Add enable IOMMU SMC command for INFRA masters
2023-06-02 9:02 [PATCH v12 0/7] MT8188 IOMMU SUPPORT Yong Wu
` (2 preceding siblings ...)
2023-06-02 9:02 ` [PATCH v12 3/7] iommu/mediatek: Adjust mtk_iommu_config flow Yong Wu
@ 2023-06-02 9:02 ` Yong Wu
2023-06-06 14:04 ` Alexandre Mergnat
2023-06-02 9:02 ` [PATCH v12 5/7] iommu/mediatek: Add MT8188 IOMMU Support Yong Wu
` (3 subsequent siblings)
7 siblings, 1 reply; 25+ messages in thread
From: Yong Wu @ 2023-06-02 9:02 UTC (permalink / raw)
To: Joerg Roedel, Will Deacon, Rob Herring, Matthias Brugger
Cc: Robin Murphy, Krzysztof Kozlowski, Yong Wu,
AngeloGioacchino Del Regno, iommu, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, mingyuan.ma, yf.wang,
jianjiao.zeng, chengci.xu
From: "Chengci.Xu" <chengci.xu@mediatek.com>
Prepare for MT8188. In MT8188, the register which enables IOMMU for
INFRA masters are in the secure world for security concerns, therefore we
add a SMC command for INFRA masters to enable IOMMU in ATF.
Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/iommu/mtk_iommu.c | 32 ++++++++++++++++++++++----------
include/soc/mediatek/smi.h | 1 +
2 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 8cff85615d5e..9c89cf894a4d 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -3,6 +3,7 @@
* Copyright (c) 2015-2016 MediaTek Inc.
* Author: Yong Wu <yong.wu@mediatek.com>
*/
+#include <linux/arm-smccc.h>
#include <linux/bitfield.h>
#include <linux/bug.h>
#include <linux/clk.h>
@@ -27,6 +28,7 @@
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/soc/mediatek/infracfg.h>
+#include <linux/soc/mediatek/mtk_sip_svc.h>
#include <asm/barrier.h>
#include <soc/mediatek/smi.h>
@@ -143,6 +145,7 @@
#define PGTABLE_PA_35_EN BIT(17)
#define TF_PORT_TO_ADDR_MT8173 BIT(18)
#define INT_ID_PORT_WIDTH_6 BIT(19)
+#define CFG_IFA_MASTER_IN_ATF BIT(20)
#define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
((((pdata)->flags) & (mask)) == (_x))
@@ -580,6 +583,7 @@ static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
const struct mtk_iommu_iova_region *region;
unsigned long portid_msk = 0;
+ struct arm_smccc_res res;
int i, ret = 0;
for (i = 0; i < fwspec->num_ids; ++i) {
@@ -605,17 +609,24 @@ static int mtk_iommu_config(struct mtk_iommu_data *data, struct device *dev,
else
larb_mmu->mmu &= ~portid_msk;
} else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
- /* PCI dev has only one output id, enable the next writing bit for PCIe */
- if (dev_is_pci(dev)) {
- if (fwspec->num_ids != 1) {
- dev_err(dev, "PCI dev can only have one port.\n");
- return -ENODEV;
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) {
+ arm_smccc_smc(MTK_SIP_KERNEL_IOMMU_CONTROL,
+ IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU,
+ portid_msk, enable, 0, 0, 0, 0, &res);
+ ret = res.a0;
+ } else {
+ /* PCI dev has only one output id, enable the next writing bit for PCIe */
+ if (dev_is_pci(dev)) {
+ if (fwspec->num_ids != 1) {
+ dev_err(dev, "PCI dev can only have one port.\n");
+ return -ENODEV;
+ }
+ portid_msk |= BIT(portid + 1);
}
- portid_msk |= BIT(portid + 1);
- }
- ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1,
- (u32)portid_msk, enable ? (u32)portid_msk : 0);
+ ret = regmap_update_bits(data->pericfg, PERICFG_IOMMU_1,
+ (u32)portid_msk, enable ? (u32)portid_msk : 0);
+ }
if (ret)
dev_err(dev, "%s iommu(%s) inframaster 0x%lx fail(%d).\n",
enable ? "enable" : "disable",
@@ -1329,7 +1340,8 @@ static int mtk_iommu_probe(struct platform_device *pdev)
dev_err_probe(dev, ret, "mm dts parse fail\n");
goto out_runtime_disable;
}
- } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA)) {
+ } else if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_INFRA) &&
+ !MTK_IOMMU_HAS_FLAG(data->plat_data, CFG_IFA_MASTER_IN_ATF)) {
p = data->plat_data->pericfg_comp_str;
data->pericfg = syscon_regmap_lookup_by_compatible(p);
if (IS_ERR(data->pericfg)) {
diff --git a/include/soc/mediatek/smi.h b/include/soc/mediatek/smi.h
index dfd8efca5e60..000eb1cf68b7 100644
--- a/include/soc/mediatek/smi.h
+++ b/include/soc/mediatek/smi.h
@@ -13,6 +13,7 @@
enum iommu_atf_cmd {
IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to en/disable iommu */
+ IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, /* For infra master to enable iommu */
IOMMU_ATF_CMD_MAX,
};
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH v12 4/7] iommu/mediatek: Add enable IOMMU SMC command for INFRA masters
2023-06-02 9:02 ` [PATCH v12 4/7] iommu/mediatek: Add enable IOMMU SMC command for INFRA masters Yong Wu
@ 2023-06-06 14:04 ` Alexandre Mergnat
0 siblings, 0 replies; 25+ messages in thread
From: Alexandre Mergnat @ 2023-06-06 14:04 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Rob Herring, Matthias Brugger
Cc: Robin Murphy, Krzysztof Kozlowski, AngeloGioacchino Del Regno,
iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, mingyuan.ma, yf.wang, jianjiao.zeng,
chengci.xu
On 02/06/2023 11:02, Yong Wu wrote:
> Prepare for MT8188. In MT8188, the register which enables IOMMU for
> INFRA masters are in the secure world for security concerns, therefore we
> add a SMC command for INFRA masters to enable IOMMU in ATF.
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
--
Regards,
Alexandre
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v12 5/7] iommu/mediatek: Add MT8188 IOMMU Support
2023-06-02 9:02 [PATCH v12 0/7] MT8188 IOMMU SUPPORT Yong Wu
` (3 preceding siblings ...)
2023-06-02 9:02 ` [PATCH v12 4/7] iommu/mediatek: Add enable IOMMU SMC command for INFRA masters Yong Wu
@ 2023-06-02 9:02 ` Yong Wu
2023-06-06 14:16 ` Alexandre Mergnat
2023-08-08 9:53 ` Chen-Yu Tsai
2023-06-02 9:02 ` [PATCH v12 6/7] iommu/mediatek: mt8188: Add iova_region_larb_msk Yong Wu
` (2 subsequent siblings)
7 siblings, 2 replies; 25+ messages in thread
From: Yong Wu @ 2023-06-02 9:02 UTC (permalink / raw)
To: Joerg Roedel, Will Deacon, Rob Herring, Matthias Brugger
Cc: Robin Murphy, Krzysztof Kozlowski, Yong Wu,
AngeloGioacchino Del Regno, iommu, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, mingyuan.ma, yf.wang,
jianjiao.zeng, chengci.xu
From: "Chengci.Xu" <chengci.xu@mediatek.com>
MT8188 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo, the other
is for vpp. and 1 INFRA IOMMU.
Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/iommu/mtk_iommu.c | 49 +++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 9c89cf894a4d..5c66af0c45a8 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -170,6 +170,7 @@ enum mtk_iommu_plat {
M4U_MT8173,
M4U_MT8183,
M4U_MT8186,
+ M4U_MT8188,
M4U_MT8192,
M4U_MT8195,
M4U_MT8365,
@@ -1593,6 +1594,51 @@ static const struct mtk_iommu_plat_data mt8186_data_mm = {
.iova_region_larb_msk = mt8186_larb_region_msk,
};
+static const struct mtk_iommu_plat_data mt8188_data_infra = {
+ .m4u_plat = M4U_MT8188,
+ .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO |
+ MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT |
+ PGTABLE_PA_35_EN | CFG_IFA_MASTER_IN_ATF,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
+ .banks_num = 1,
+ .banks_enable = {true},
+ .iova_region = single_domain,
+ .iova_region_nr = ARRAY_SIZE(single_domain),
+};
+
+static const struct mtk_iommu_plat_data mt8188_data_vdo = {
+ .m4u_plat = M4U_MT8188,
+ .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
+ WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE |
+ PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM,
+ .hw_list = &m4ulist,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
+ .banks_num = 1,
+ .banks_enable = {true},
+ .iova_region = mt8192_multi_dom,
+ .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+ .larbid_remap = {{2}, {0}, {21}, {0}, {19}, {9, 10,
+ 11 /* 11a */, 25 /* 11c */},
+ {13, 0, 29 /* 16b */, 30 /* 17b */, 0}, {5}},
+};
+
+static const struct mtk_iommu_plat_data mt8188_data_vpp = {
+ .m4u_plat = M4U_MT8188,
+ .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
+ WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE |
+ PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM,
+ .hw_list = &m4ulist,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
+ .banks_num = 1,
+ .banks_enable = {true},
+ .iova_region = mt8192_multi_dom,
+ .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+ .larbid_remap = {{1}, {3}, {23}, {7}, {MTK_INVALID_LARBID},
+ {12, 15, 24 /* 11b */}, {14, MTK_INVALID_LARBID,
+ 16 /* 16a */, 17 /* 17a */, MTK_INVALID_LARBID,
+ 27, 28 /* ccu0 */, MTK_INVALID_LARBID}, {4, 6}},
+};
+
static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
[0] = {~0, ~0}, /* Region0: larb0/1 */
[1] = {0, 0, 0, 0, ~0, ~0, 0, ~0}, /* Region1: larb4/5/7 */
@@ -1701,6 +1747,9 @@ static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
{ .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
{ .compatible = "mediatek,mt8186-iommu-mm", .data = &mt8186_data_mm}, /* mm: m4u */
+ { .compatible = "mediatek,mt8188-iommu-infra", .data = &mt8188_data_infra},
+ { .compatible = "mediatek,mt8188-iommu-vdo", .data = &mt8188_data_vdo},
+ { .compatible = "mediatek,mt8188-iommu-vpp", .data = &mt8188_data_vpp},
{ .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
{ .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
{ .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo},
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH v12 5/7] iommu/mediatek: Add MT8188 IOMMU Support
2023-06-02 9:02 ` [PATCH v12 5/7] iommu/mediatek: Add MT8188 IOMMU Support Yong Wu
@ 2023-06-06 14:16 ` Alexandre Mergnat
2023-08-08 9:53 ` Chen-Yu Tsai
1 sibling, 0 replies; 25+ messages in thread
From: Alexandre Mergnat @ 2023-06-06 14:16 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Rob Herring, Matthias Brugger
Cc: Robin Murphy, Krzysztof Kozlowski, AngeloGioacchino Del Regno,
iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, mingyuan.ma, yf.wang, jianjiao.zeng,
chengci.xu
On 02/06/2023 11:02, Yong Wu wrote:
> MT8188 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo, the other
> is for vpp. and 1 INFRA IOMMU.
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
--
Regards,
Alexandre
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v12 5/7] iommu/mediatek: Add MT8188 IOMMU Support
2023-06-02 9:02 ` [PATCH v12 5/7] iommu/mediatek: Add MT8188 IOMMU Support Yong Wu
2023-06-06 14:16 ` Alexandre Mergnat
@ 2023-08-08 9:53 ` Chen-Yu Tsai
2023-08-10 12:22 ` Yong Wu (吴勇)
1 sibling, 1 reply; 25+ messages in thread
From: Chen-Yu Tsai @ 2023-08-08 9:53 UTC (permalink / raw)
To: Yong Wu
Cc: Joerg Roedel, Will Deacon, Rob Herring, Matthias Brugger,
Robin Murphy, Krzysztof Kozlowski, AngeloGioacchino Del Regno,
iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, mingyuan.ma, yf.wang, jianjiao.zeng,
chengci.xu
On Fri, Jun 2, 2023 at 5:04 PM Yong Wu <yong.wu@mediatek.com> wrote:
>
> From: "Chengci.Xu" <chengci.xu@mediatek.com>
>
> MT8188 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo, the other
> is for vpp. and 1 INFRA IOMMU.
>
> Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/iommu/mtk_iommu.c | 49 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 9c89cf894a4d..5c66af0c45a8 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -170,6 +170,7 @@ enum mtk_iommu_plat {
> M4U_MT8173,
> M4U_MT8183,
> M4U_MT8186,
> + M4U_MT8188,
> M4U_MT8192,
> M4U_MT8195,
> M4U_MT8365,
> @@ -1593,6 +1594,51 @@ static const struct mtk_iommu_plat_data mt8186_data_mm = {
> .iova_region_larb_msk = mt8186_larb_region_msk,
> };
>
> +static const struct mtk_iommu_plat_data mt8188_data_infra = {
> + .m4u_plat = M4U_MT8188,
> + .flags = WR_THROT_EN | DCM_DISABLE | STD_AXI_MODE | PM_CLK_AO |
> + MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIE_SUPPORT |
> + PGTABLE_PA_35_EN | CFG_IFA_MASTER_IN_ATF,
FWIW, CFG_IFA_MASTER_IN_ATF should not be tied to the compatible string,
but set via a DT property. The IOMMU controls are secured by firmware.
It is not a property intrinsically tied to the hardware.
If on some other project there is no such security requirement and the
IOMMU is opened up to non-secure world, and ATF not even having support
for the SMC call, this becomes unusable and hard to rectify without
introducing a new compatible string.
ChenYu
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> + .banks_num = 1,
> + .banks_enable = {true},
> + .iova_region = single_domain,
> + .iova_region_nr = ARRAY_SIZE(single_domain),
> +};
> +
> +static const struct mtk_iommu_plat_data mt8188_data_vdo = {
> + .m4u_plat = M4U_MT8188,
> + .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
> + WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE |
> + PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM,
> + .hw_list = &m4ulist,
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> + .banks_num = 1,
> + .banks_enable = {true},
> + .iova_region = mt8192_multi_dom,
> + .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
> + .larbid_remap = {{2}, {0}, {21}, {0}, {19}, {9, 10,
> + 11 /* 11a */, 25 /* 11c */},
> + {13, 0, 29 /* 16b */, 30 /* 17b */, 0}, {5}},
> +};
> +
> +static const struct mtk_iommu_plat_data mt8188_data_vpp = {
> + .m4u_plat = M4U_MT8188,
> + .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
> + WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE |
> + PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM,
> + .hw_list = &m4ulist,
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> + .banks_num = 1,
> + .banks_enable = {true},
> + .iova_region = mt8192_multi_dom,
> + .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
> + .larbid_remap = {{1}, {3}, {23}, {7}, {MTK_INVALID_LARBID},
> + {12, 15, 24 /* 11b */}, {14, MTK_INVALID_LARBID,
> + 16 /* 16a */, 17 /* 17a */, MTK_INVALID_LARBID,
> + 27, 28 /* ccu0 */, MTK_INVALID_LARBID}, {4, 6}},
> +};
> +
> static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
> [0] = {~0, ~0}, /* Region0: larb0/1 */
> [1] = {0, 0, 0, 0, ~0, ~0, 0, ~0}, /* Region1: larb4/5/7 */
> @@ -1701,6 +1747,9 @@ static const struct of_device_id mtk_iommu_of_ids[] = {
> { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
> { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
> { .compatible = "mediatek,mt8186-iommu-mm", .data = &mt8186_data_mm}, /* mm: m4u */
> + { .compatible = "mediatek,mt8188-iommu-infra", .data = &mt8188_data_infra},
> + { .compatible = "mediatek,mt8188-iommu-vdo", .data = &mt8188_data_vdo},
> + { .compatible = "mediatek,mt8188-iommu-vpp", .data = &mt8188_data_vpp},
> { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
> { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
> { .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo},
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v12 5/7] iommu/mediatek: Add MT8188 IOMMU Support
2023-08-08 9:53 ` Chen-Yu Tsai
@ 2023-08-10 12:22 ` Yong Wu (吴勇)
2023-08-11 3:30 ` Chen-Yu Tsai
0 siblings, 1 reply; 25+ messages in thread
From: Yong Wu (吴勇) @ 2023-08-10 12:22 UTC (permalink / raw)
To: wenst
Cc: linux-mediatek, robh+dt, linux-kernel, devicetree,
Jianjiao Zeng (曾健姣),
robin.murphy, joro, Chengci Xu (许承赐),
YF Wang (王云飞),
linux-arm-kernel, iommu, krzysztof.kozlowski+dt, matthias.bgg,
Mingyuan Ma (马鸣远),
angelogioacchino.delregno, will
On Tue, 2023-08-08 at 17:53 +0800, Chen-Yu Tsai wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> On Fri, Jun 2, 2023 at 5:04 PM Yong Wu <yong.wu@mediatek.com> wrote:
> >
> > From: "Chengci.Xu" <chengci.xu@mediatek.com>
> >
> > MT8188 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo, the
> other
> > is for vpp. and 1 INFRA IOMMU.
> >
> > Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
> > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/iommu/mtk_iommu.c | 49
> +++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 49 insertions(+)
> >
> > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > index 9c89cf894a4d..5c66af0c45a8 100644
> > --- a/drivers/iommu/mtk_iommu.c
> > +++ b/drivers/iommu/mtk_iommu.c
> > @@ -170,6 +170,7 @@ enum mtk_iommu_plat {
> > M4U_MT8173,
> > M4U_MT8183,
> > M4U_MT8186,
> > + M4U_MT8188,
> > M4U_MT8192,
> > M4U_MT8195,
> > M4U_MT8365,
> > @@ -1593,6 +1594,51 @@ static const struct mtk_iommu_plat_data
> mt8186_data_mm = {
> > .iova_region_larb_msk = mt8186_larb_region_msk,
> > };
> >
> > +static const struct mtk_iommu_plat_data mt8188_data_infra = {
> > + .m4u_plat = M4U_MT8188,
> > + .flags = WR_THROT_EN | DCM_DISABLE |
> STD_AXI_MODE | PM_CLK_AO |
> > + MTK_IOMMU_TYPE_INFRA |
> IFA_IOMMU_PCIE_SUPPORT |
> > + PGTABLE_PA_35_EN |
> CFG_IFA_MASTER_IN_ATF,
>
> FWIW, CFG_IFA_MASTER_IN_ATF should not be tied to the compatible
> string,
> but set via a DT property. The IOMMU controls are secured by
> firmware.
> It is not a property intrinsically tied to the hardware.
The flag CFG_IFA_MASTER_IN_ATF means the registers which enable/disable
iommu are in the secure world. If the master like pcie want to enable
iommu, we have to enter secure world to configure it. It should be HW
intrinsical, right?
>
> If on some other project there is no such security requirement and
> the
> IOMMU is opened up to non-secure world, and ATF not even having
> support
> for the SMC call, this becomes unusable and hard to rectify without
> introducing a new compatible string.
>
> ChenYu
>
> > + .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> > + .banks_num = 1,
> > + .banks_enable = {true},
> > + .iova_region = single_domain,
> > + .iova_region_nr = ARRAY_SIZE(single_domain),
> > +};
> > +
> > +static const struct mtk_iommu_plat_data mt8188_data_vdo = {
> > + .m4u_plat = M4U_MT8188,
> > + .flags = HAS_BCLK | HAS_SUB_COMM_3BITS |
> OUT_ORDER_WR_EN |
> > + WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE
> |
> > + PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM,
> > + .hw_list = &m4ulist,
> > + .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> > + .banks_num = 1,
> > + .banks_enable = {true},
> > + .iova_region = mt8192_multi_dom,
> > + .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
> > + .larbid_remap = {{2}, {0}, {21}, {0}, {19}, {9, 10,
> > + 11 /* 11a */, 25 /* 11c */},
> > + {13, 0, 29 /* 16b */, 30 /* 17b */, 0},
> {5}},
> > +};
> > +
> > +static const struct mtk_iommu_plat_data mt8188_data_vpp = {
> > + .m4u_plat = M4U_MT8188,
> > + .flags = HAS_BCLK | HAS_SUB_COMM_3BITS |
> OUT_ORDER_WR_EN |
> > + WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE
> |
> > + PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM,
> > + .hw_list = &m4ulist,
> > + .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> > + .banks_num = 1,
> > + .banks_enable = {true},
> > + .iova_region = mt8192_multi_dom,
> > + .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
> > + .larbid_remap = {{1}, {3}, {23}, {7},
> {MTK_INVALID_LARBID},
> > + {12, 15, 24 /* 11b */}, {14,
> MTK_INVALID_LARBID,
> > + 16 /* 16a */, 17 /* 17a */,
> MTK_INVALID_LARBID,
> > + 27, 28 /* ccu0 */, MTK_INVALID_LARBID},
> {4, 6}},
> > +};
> > +
> > static const unsigned int
> mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] =
> {
> > [0] = {~0, ~0}, /* Region0: larb0/1
> */
> > [1] = {0, 0, 0, 0, ~0, ~0, 0, ~0}, /* Region1:
> larb4/5/7 */
> > @@ -1701,6 +1747,9 @@ static const struct of_device_id
> mtk_iommu_of_ids[] = {
> > { .compatible = "mediatek,mt8173-m4u", .data =
> &mt8173_data},
> > { .compatible = "mediatek,mt8183-m4u", .data =
> &mt8183_data},
> > { .compatible = "mediatek,mt8186-iommu-mm", .data =
> &mt8186_data_mm}, /* mm: m4u */
> > + { .compatible = "mediatek,mt8188-iommu-infra", .data =
> &mt8188_data_infra},
> > + { .compatible = "mediatek,mt8188-iommu-vdo", .data =
> &mt8188_data_vdo},
> > + { .compatible = "mediatek,mt8188-iommu-vpp", .data =
> &mt8188_data_vpp},
> > { .compatible = "mediatek,mt8192-m4u", .data =
> &mt8192_data},
> > { .compatible = "mediatek,mt8195-iommu-infra", .data =
> &mt8195_data_infra},
> > { .compatible = "mediatek,mt8195-iommu-vdo", .data =
> &mt8195_data_vdo},
> > --
> > 2.25.1
> >
> >
>
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v12 5/7] iommu/mediatek: Add MT8188 IOMMU Support
2023-08-10 12:22 ` Yong Wu (吴勇)
@ 2023-08-11 3:30 ` Chen-Yu Tsai
2023-08-14 7:14 ` Yong Wu (吴勇)
0 siblings, 1 reply; 25+ messages in thread
From: Chen-Yu Tsai @ 2023-08-11 3:30 UTC (permalink / raw)
To: Yong Wu (吴勇)
Cc: linux-mediatek, robh+dt, linux-kernel, devicetree,
Jianjiao Zeng (曾健姣),
robin.murphy, joro, Chengci Xu (许承赐),
YF Wang (王云飞),
linux-arm-kernel, iommu, krzysztof.kozlowski+dt, matthias.bgg,
Mingyuan Ma (马鸣远),
angelogioacchino.delregno, will
On Thu, Aug 10, 2023 at 8:23 PM Yong Wu (吴勇) <Yong.Wu@mediatek.com> wrote:
>
> On Tue, 2023-08-08 at 17:53 +0800, Chen-Yu Tsai wrote:
> >
> > External email : Please do not click links or open attachments until
> > you have verified the sender or the content.
> > On Fri, Jun 2, 2023 at 5:04 PM Yong Wu <yong.wu@mediatek.com> wrote:
> > >
> > > From: "Chengci.Xu" <chengci.xu@mediatek.com>
> > >
> > > MT8188 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo, the
> > other
> > > is for vpp. and 1 INFRA IOMMU.
> > >
> > > Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
> > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > > ---
> > > drivers/iommu/mtk_iommu.c | 49
> > +++++++++++++++++++++++++++++++++++++++
> > > 1 file changed, 49 insertions(+)
> > >
> > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > > index 9c89cf894a4d..5c66af0c45a8 100644
> > > --- a/drivers/iommu/mtk_iommu.c
> > > +++ b/drivers/iommu/mtk_iommu.c
> > > @@ -170,6 +170,7 @@ enum mtk_iommu_plat {
> > > M4U_MT8173,
> > > M4U_MT8183,
> > > M4U_MT8186,
> > > + M4U_MT8188,
> > > M4U_MT8192,
> > > M4U_MT8195,
> > > M4U_MT8365,
> > > @@ -1593,6 +1594,51 @@ static const struct mtk_iommu_plat_data
> > mt8186_data_mm = {
> > > .iova_region_larb_msk = mt8186_larb_region_msk,
> > > };
> > >
> > > +static const struct mtk_iommu_plat_data mt8188_data_infra = {
> > > + .m4u_plat = M4U_MT8188,
> > > + .flags = WR_THROT_EN | DCM_DISABLE |
> > STD_AXI_MODE | PM_CLK_AO |
> > > + MTK_IOMMU_TYPE_INFRA |
> > IFA_IOMMU_PCIE_SUPPORT |
> > > + PGTABLE_PA_35_EN |
> > CFG_IFA_MASTER_IN_ATF,
> >
> > FWIW, CFG_IFA_MASTER_IN_ATF should not be tied to the compatible
> > string,
> > but set via a DT property. The IOMMU controls are secured by
> > firmware.
> > It is not a property intrinsically tied to the hardware.
>
> The flag CFG_IFA_MASTER_IN_ATF means the registers which enable/disable
> iommu are in the secure world. If the master like pcie want to enable
> iommu, we have to enter secure world to configure it. It should be HW
> intrinsical, right?
If I understand correctly, this is forced by setting some registers.
The registers are set by the firmware at boot time.
So if a different firmware that doesn't set the registers is used,
then the IOMMU is available to non-secure kernel, correct?
That's why I said that it should not be tied to a particular hardware
platform, but set using a boolean device tree property.
> >
> > If on some other project there is no such security requirement and
> > the
> > IOMMU is opened up to non-secure world, and ATF not even having
> > support
> > for the SMC call, this becomes unusable and hard to rectify without
> > introducing a new compatible string.
> >
> > ChenYu
> >
> > > + .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> > > + .banks_num = 1,
> > > + .banks_enable = {true},
> > > + .iova_region = single_domain,
> > > + .iova_region_nr = ARRAY_SIZE(single_domain),
> > > +};
> > > +
> > > +static const struct mtk_iommu_plat_data mt8188_data_vdo = {
> > > + .m4u_plat = M4U_MT8188,
> > > + .flags = HAS_BCLK | HAS_SUB_COMM_3BITS |
> > OUT_ORDER_WR_EN |
> > > + WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE
> > |
> > > + PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM,
> > > + .hw_list = &m4ulist,
> > > + .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> > > + .banks_num = 1,
> > > + .banks_enable = {true},
> > > + .iova_region = mt8192_multi_dom,
> > > + .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
> > > + .larbid_remap = {{2}, {0}, {21}, {0}, {19}, {9, 10,
> > > + 11 /* 11a */, 25 /* 11c */},
> > > + {13, 0, 29 /* 16b */, 30 /* 17b */, 0},
> > {5}},
> > > +};
> > > +
> > > +static const struct mtk_iommu_plat_data mt8188_data_vpp = {
> > > + .m4u_plat = M4U_MT8188,
> > > + .flags = HAS_BCLK | HAS_SUB_COMM_3BITS |
> > OUT_ORDER_WR_EN |
> > > + WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE
> > |
> > > + PGTABLE_PA_35_EN | MTK_IOMMU_TYPE_MM,
> > > + .hw_list = &m4ulist,
> > > + .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> > > + .banks_num = 1,
> > > + .banks_enable = {true},
> > > + .iova_region = mt8192_multi_dom,
> > > + .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
> > > + .larbid_remap = {{1}, {3}, {23}, {7},
> > {MTK_INVALID_LARBID},
> > > + {12, 15, 24 /* 11b */}, {14,
> > MTK_INVALID_LARBID,
> > > + 16 /* 16a */, 17 /* 17a */,
> > MTK_INVALID_LARBID,
> > > + 27, 28 /* ccu0 */, MTK_INVALID_LARBID},
> > {4, 6}},
> > > +};
> > > +
> > > static const unsigned int
> > mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] =
> > {
> > > [0] = {~0, ~0}, /* Region0: larb0/1
> > */
> > > [1] = {0, 0, 0, 0, ~0, ~0, 0, ~0}, /* Region1:
> > larb4/5/7 */
> > > @@ -1701,6 +1747,9 @@ static const struct of_device_id
> > mtk_iommu_of_ids[] = {
> > > { .compatible = "mediatek,mt8173-m4u", .data =
> > &mt8173_data},
> > > { .compatible = "mediatek,mt8183-m4u", .data =
> > &mt8183_data},
> > > { .compatible = "mediatek,mt8186-iommu-mm", .data =
> > &mt8186_data_mm}, /* mm: m4u */
> > > + { .compatible = "mediatek,mt8188-iommu-infra", .data =
> > &mt8188_data_infra},
> > > + { .compatible = "mediatek,mt8188-iommu-vdo", .data =
> > &mt8188_data_vdo},
> > > + { .compatible = "mediatek,mt8188-iommu-vpp", .data =
> > &mt8188_data_vpp},
> > > { .compatible = "mediatek,mt8192-m4u", .data =
> > &mt8192_data},
> > > { .compatible = "mediatek,mt8195-iommu-infra", .data =
> > &mt8195_data_infra},
> > > { .compatible = "mediatek,mt8195-iommu-vdo", .data =
> > &mt8195_data_vdo},
> > > --
> > > 2.25.1
> > >
> > >
> >
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v12 5/7] iommu/mediatek: Add MT8188 IOMMU Support
2023-08-11 3:30 ` Chen-Yu Tsai
@ 2023-08-14 7:14 ` Yong Wu (吴勇)
2023-08-14 8:21 ` Chen-Yu Tsai
0 siblings, 1 reply; 25+ messages in thread
From: Yong Wu (吴勇) @ 2023-08-14 7:14 UTC (permalink / raw)
To: wenst
Cc: linux-kernel, linux-mediatek, robh+dt, devicetree,
Jianjiao Zeng (曾健姣),
robin.murphy, joro, Chengci Xu (许承赐),
YF Wang (王云飞),
linux-arm-kernel, iommu, krzysztof.kozlowski+dt, matthias.bgg,
Mingyuan Ma (马鸣远),
angelogioacchino.delregno, will
On Fri, 2023-08-11 at 11:30 +0800, Chen-Yu Tsai wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> On Thu, Aug 10, 2023 at 8:23 PM Yong Wu (吴勇) <Yong.Wu@mediatek.com>
> wrote:
> >
> > On Tue, 2023-08-08 at 17:53 +0800, Chen-Yu Tsai wrote:
> > >
> > > External email : Please do not click links or open attachments
> until
> > > you have verified the sender or the content.
> > > On Fri, Jun 2, 2023 at 5:04 PM Yong Wu <yong.wu@mediatek.com>
> wrote:
> > > >
> > > > From: "Chengci.Xu" <chengci.xu@mediatek.com>
> > > >
> > > > MT8188 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo, the
> > > other
> > > > is for vpp. and 1 INFRA IOMMU.
> > > >
> > > > Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
> > > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > > ---
> > > > drivers/iommu/mtk_iommu.c | 49
> > > +++++++++++++++++++++++++++++++++++++++
> > > > 1 file changed, 49 insertions(+)
> > > >
> > > > diff --git a/drivers/iommu/mtk_iommu.c
> b/drivers/iommu/mtk_iommu.c
> > > > index 9c89cf894a4d..5c66af0c45a8 100644
> > > > --- a/drivers/iommu/mtk_iommu.c
> > > > +++ b/drivers/iommu/mtk_iommu.c
> > > > @@ -170,6 +170,7 @@ enum mtk_iommu_plat {
> > > > M4U_MT8173,
> > > > M4U_MT8183,
> > > > M4U_MT8186,
> > > > + M4U_MT8188,
> > > > M4U_MT8192,
> > > > M4U_MT8195,
> > > > M4U_MT8365,
> > > > @@ -1593,6 +1594,51 @@ static const struct mtk_iommu_plat_data
> > > mt8186_data_mm = {
> > > > .iova_region_larb_msk = mt8186_larb_region_msk,
> > > > };
> > > >
> > > > +static const struct mtk_iommu_plat_data mt8188_data_infra = {
> > > > + .m4u_plat = M4U_MT8188,
> > > > + .flags = WR_THROT_EN | DCM_DISABLE |
> > > STD_AXI_MODE | PM_CLK_AO |
> > > > + MTK_IOMMU_TYPE_INFRA |
> > > IFA_IOMMU_PCIE_SUPPORT |
> > > > + PGTABLE_PA_35_EN |
> > > CFG_IFA_MASTER_IN_ATF,
> > >
> > > FWIW, CFG_IFA_MASTER_IN_ATF should not be tied to the compatible
> > > string,
> > > but set via a DT property. The IOMMU controls are secured by
> > > firmware.
> > > It is not a property intrinsically tied to the hardware.
> >
> > The flag CFG_IFA_MASTER_IN_ATF means the registers which
> enable/disable
> > iommu are in the secure world. If the master like pcie want to
> enable
> > iommu, we have to enter secure world to configure it. It should be
> HW
> > intrinsical, right?
>
> If I understand correctly, this is forced by setting some registers.
> The registers are set by the firmware at boot time.
The register will be set before the masters that have the "iommus="
property probe. If the master doesn't have "iommus=" property in its
dtsi node, this register won't be set, then its iommu will be disabled
and it has to access continuous buffer.
>
> So if a different firmware that doesn't set the registers is used,
> then the IOMMU is available to non-secure kernel, correct?
No. The meaning of this register is whether to enable iommu. If the
register are not set, the IOMMU for that master is disabled.
>
> That's why I said that it should not be tied to a particular hardware
> platform, but set using a boolean device tree property.
>
> > >
> > > If on some other project there is no such security requirement
> and
> > > the
> > > IOMMU is opened up to non-secure world, and ATF not even having
> > > support
> > > for the SMC call, this becomes unusable and hard to rectify
> without
> > > introducing a new compatible string.
> > >
> > > ChenYu
> > >
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v12 5/7] iommu/mediatek: Add MT8188 IOMMU Support
2023-08-14 7:14 ` Yong Wu (吴勇)
@ 2023-08-14 8:21 ` Chen-Yu Tsai
2023-08-17 8:01 ` Yong Wu (吴勇)
0 siblings, 1 reply; 25+ messages in thread
From: Chen-Yu Tsai @ 2023-08-14 8:21 UTC (permalink / raw)
To: Yong Wu (吴勇)
Cc: linux-kernel, linux-mediatek, robh+dt, devicetree,
Jianjiao Zeng (曾健姣),
robin.murphy, joro, Chengci Xu (许承赐),
YF Wang (王云飞),
linux-arm-kernel, iommu, krzysztof.kozlowski+dt, matthias.bgg,
Mingyuan Ma (马鸣远),
angelogioacchino.delregno, will
On Mon, Aug 14, 2023 at 3:14 PM Yong Wu (吴勇) <Yong.Wu@mediatek.com> wrote:
>
> On Fri, 2023-08-11 at 11:30 +0800, Chen-Yu Tsai wrote:
> >
> > External email : Please do not click links or open attachments until
> > you have verified the sender or the content.
> > On Thu, Aug 10, 2023 at 8:23 PM Yong Wu (吴勇) <Yong.Wu@mediatek.com>
> > wrote:
> > >
> > > On Tue, 2023-08-08 at 17:53 +0800, Chen-Yu Tsai wrote:
> > > >
> > > > External email : Please do not click links or open attachments
> > until
> > > > you have verified the sender or the content.
> > > > On Fri, Jun 2, 2023 at 5:04 PM Yong Wu <yong.wu@mediatek.com>
> > wrote:
> > > > >
> > > > > From: "Chengci.Xu" <chengci.xu@mediatek.com>
> > > > >
> > > > > MT8188 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo, the
> > > > other
> > > > > is for vpp. and 1 INFRA IOMMU.
> > > > >
> > > > > Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
> > > > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > > > > Reviewed-by: AngeloGioacchino Del Regno <
> > > > angelogioacchino.delregno@collabora.com>
> > > > > ---
> > > > > drivers/iommu/mtk_iommu.c | 49
> > > > +++++++++++++++++++++++++++++++++++++++
> > > > > 1 file changed, 49 insertions(+)
> > > > >
> > > > > diff --git a/drivers/iommu/mtk_iommu.c
> > b/drivers/iommu/mtk_iommu.c
> > > > > index 9c89cf894a4d..5c66af0c45a8 100644
> > > > > --- a/drivers/iommu/mtk_iommu.c
> > > > > +++ b/drivers/iommu/mtk_iommu.c
> > > > > @@ -170,6 +170,7 @@ enum mtk_iommu_plat {
> > > > > M4U_MT8173,
> > > > > M4U_MT8183,
> > > > > M4U_MT8186,
> > > > > + M4U_MT8188,
> > > > > M4U_MT8192,
> > > > > M4U_MT8195,
> > > > > M4U_MT8365,
> > > > > @@ -1593,6 +1594,51 @@ static const struct mtk_iommu_plat_data
> > > > mt8186_data_mm = {
> > > > > .iova_region_larb_msk = mt8186_larb_region_msk,
> > > > > };
> > > > >
> > > > > +static const struct mtk_iommu_plat_data mt8188_data_infra = {
> > > > > + .m4u_plat = M4U_MT8188,
> > > > > + .flags = WR_THROT_EN | DCM_DISABLE |
> > > > STD_AXI_MODE | PM_CLK_AO |
> > > > > + MTK_IOMMU_TYPE_INFRA |
> > > > IFA_IOMMU_PCIE_SUPPORT |
> > > > > + PGTABLE_PA_35_EN |
> > > > CFG_IFA_MASTER_IN_ATF,
> > > >
> > > > FWIW, CFG_IFA_MASTER_IN_ATF should not be tied to the compatible
> > > > string,
> > > > but set via a DT property. The IOMMU controls are secured by
> > > > firmware.
> > > > It is not a property intrinsically tied to the hardware.
> > >
> > > The flag CFG_IFA_MASTER_IN_ATF means the registers which
> > enable/disable
> > > iommu are in the secure world. If the master like pcie want to
> > enable
> > > iommu, we have to enter secure world to configure it. It should be
> > HW
> > > intrinsical, right?
> >
> > If I understand correctly, this is forced by setting some registers.
> > The registers are set by the firmware at boot time.
>
> The register will be set before the masters that have the "iommus="
> property probe. If the master doesn't have "iommus=" property in its
> dtsi node, this register won't be set, then its iommu will be disabled
> and it has to access continuous buffer.
>
> >
> > So if a different firmware that doesn't set the registers is used,
> > then the IOMMU is available to non-secure kernel, correct?
>
> No. The meaning of this register is whether to enable iommu. If the
> register are not set, the IOMMU for that master is disabled.
For clarity, I'm referring to PERI_MST_PROT [1], not the registers in the
IOMMU or LARBs. So not any of the registers used in this patch.
If that register doesn't restrict access to IOMMU register space to secure
only, then I assume it is controlled by fuses?
[1] https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/be457248c6b0a7f3c61bd95af58372938d13decd/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.c#93
> >
> > That's why I said that it should not be tied to a particular hardware
> > platform, but set using a boolean device tree property.
> >
> > > >
> > > > If on some other project there is no such security requirement
> > and
> > > > the
> > > > IOMMU is opened up to non-secure world, and ATF not even having
> > > > support
> > > > for the SMC call, this becomes unusable and hard to rectify
> > without
> > > > introducing a new compatible string.
> > > >
> > > > ChenYu
> > > >
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v12 5/7] iommu/mediatek: Add MT8188 IOMMU Support
2023-08-14 8:21 ` Chen-Yu Tsai
@ 2023-08-17 8:01 ` Yong Wu (吴勇)
2023-08-17 8:10 ` Chen-Yu Tsai
0 siblings, 1 reply; 25+ messages in thread
From: Yong Wu (吴勇) @ 2023-08-17 8:01 UTC (permalink / raw)
To: wenst
Cc: linux-kernel, linux-mediatek, robh+dt, devicetree,
Jianjiao Zeng (曾健姣),
robin.murphy, joro, Chengci Xu (许承赐),
YF Wang (王云飞),
linux-arm-kernel, iommu, krzysztof.kozlowski+dt, matthias.bgg,
Mingyuan Ma (马鸣远),
angelogioacchino.delregno, will
On Mon, 2023-08-14 at 16:21 +0800, Chen-Yu Tsai wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> On Mon, Aug 14, 2023 at 3:14 PM Yong Wu (吴勇) <Yong.Wu@mediatek.com>
> wrote:
> >
> > On Fri, 2023-08-11 at 11:30 +0800, Chen-Yu Tsai wrote:
> > >
> > > External email : Please do not click links or open attachments
> until
> > > you have verified the sender or the content.
> > > On Thu, Aug 10, 2023 at 8:23 PM Yong Wu (吴勇) <
> Yong.Wu@mediatek.com>
> > > wrote:
> > > >
> > > > On Tue, 2023-08-08 at 17:53 +0800, Chen-Yu Tsai wrote:
> > > > >
> > > > > External email : Please do not click links or open
> attachments
> > > until
> > > > > you have verified the sender or the content.
> > > > > On Fri, Jun 2, 2023 at 5:04 PM Yong Wu <yong.wu@mediatek.com
> >
> > > wrote:
> > > > > >
> > > > > > From: "Chengci.Xu" <chengci.xu@mediatek.com>
> > > > > >
> > > > > > MT8188 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo,
> the
> > > > > other
> > > > > > is for vpp. and 1 INFRA IOMMU.
> > > > > >
> > > > > > Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
> > > > > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > > > > > Reviewed-by: AngeloGioacchino Del Regno <
> > > > > angelogioacchino.delregno@collabora.com>
> > > > > > ---
> > > > > > drivers/iommu/mtk_iommu.c | 49
> > > > > +++++++++++++++++++++++++++++++++++++++
> > > > > > 1 file changed, 49 insertions(+)
> > > > > >
> > > > > > diff --git a/drivers/iommu/mtk_iommu.c
> > > b/drivers/iommu/mtk_iommu.c
> > > > > > index 9c89cf894a4d..5c66af0c45a8 100644
> > > > > > --- a/drivers/iommu/mtk_iommu.c
> > > > > > +++ b/drivers/iommu/mtk_iommu.c
> > > > > > @@ -170,6 +170,7 @@ enum mtk_iommu_plat {
> > > > > > M4U_MT8173,
> > > > > > M4U_MT8183,
> > > > > > M4U_MT8186,
> > > > > > + M4U_MT8188,
> > > > > > M4U_MT8192,
> > > > > > M4U_MT8195,
> > > > > > M4U_MT8365,
> > > > > > @@ -1593,6 +1594,51 @@ static const struct
> mtk_iommu_plat_data
> > > > > mt8186_data_mm = {
> > > > > > .iova_region_larb_msk = mt8186_larb_region_msk,
> > > > > > };
> > > > > >
> > > > > > +static const struct mtk_iommu_plat_data mt8188_data_infra
> = {
> > > > > > + .m4u_plat = M4U_MT8188,
> > > > > > + .flags = WR_THROT_EN | DCM_DISABLE |
> > > > > STD_AXI_MODE | PM_CLK_AO |
> > > > > > + MTK_IOMMU_TYPE_INFRA |
> > > > > IFA_IOMMU_PCIE_SUPPORT |
> > > > > > + PGTABLE_PA_35_EN |
> > > > > CFG_IFA_MASTER_IN_ATF,
> > > > >
> > > > > FWIW, CFG_IFA_MASTER_IN_ATF should not be tied to the
> compatible
> > > > > string,
> > > > > but set via a DT property. The IOMMU controls are secured by
> > > > > firmware.
> > > > > It is not a property intrinsically tied to the hardware.
> > > >
> > > > The flag CFG_IFA_MASTER_IN_ATF means the registers which
> > > enable/disable
> > > > iommu are in the secure world. If the master like pcie want to
> > > enable
> > > > iommu, we have to enter secure world to configure it. It should
> be
> > > HW
> > > > intrinsical, right?
> > >
> > > If I understand correctly, this is forced by setting some
> registers.
> > > The registers are set by the firmware at boot time.
> >
> > The register will be set before the masters that have the "iommus="
> > property probe. If the master doesn't have "iommus=" property in
> its
> > dtsi node, this register won't be set, then its iommu will be
> disabled
> > and it has to access continuous buffer.
> >
> > >
> > > So if a different firmware that doesn't set the registers is
> used,
> > > then the IOMMU is available to non-secure kernel, correct?
> >
> > No. The meaning of this register is whether to enable iommu. If the
> > register are not set, the IOMMU for that master is disabled.
>
> For clarity, I'm referring to PERI_MST_PROT [1], not the registers in
> the
> IOMMU or LARBs. So not any of the registers used in this patch.
>
> If that register doesn't restrict access to IOMMU register space to
> secure
> only, then I assume it is controlled by fuses?
Thanks for the clarification. Understand this now. If that register
doesn't restrict this, the register for enabling the iommu could be
accessed in normal world.
> [1]
> https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/be457248c6b0a7f3c61bd95af58372938d13decd/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.c#93
>
> > >
> > > That's why I said that it should not be tied to a particular
> hardware
> > > platform, but set using a boolean device tree property.
> > >
> > > > >
> > > > > If on some other project there is no such security
> requirement
> > > and
> > > > > the
> > > > > IOMMU is opened up to non-secure world, and ATF not even
> having
> > > > > support
> > > > > for the SMC call, this becomes unusable and hard to rectify
> > > without
> > > > > introducing a new compatible string.
Then this make sense. Sorry, I don't know if such project exist, I
guess no, right? we could add it when necessary?
Thanks.
> > > > >
> > > > > ChenYu
> > > > >
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH v12 5/7] iommu/mediatek: Add MT8188 IOMMU Support
2023-08-17 8:01 ` Yong Wu (吴勇)
@ 2023-08-17 8:10 ` Chen-Yu Tsai
0 siblings, 0 replies; 25+ messages in thread
From: Chen-Yu Tsai @ 2023-08-17 8:10 UTC (permalink / raw)
To: Yong Wu (吴勇)
Cc: linux-kernel, linux-mediatek, robh+dt, devicetree,
Jianjiao Zeng (曾健姣),
robin.murphy, joro, Chengci Xu (许承赐),
YF Wang (王云飞),
linux-arm-kernel, iommu, krzysztof.kozlowski+dt, matthias.bgg,
Mingyuan Ma (马鸣远),
angelogioacchino.delregno, will
On Thu, Aug 17, 2023 at 4:03 PM Yong Wu (吴勇) <Yong.Wu@mediatek.com> wrote:
>
> On Mon, 2023-08-14 at 16:21 +0800, Chen-Yu Tsai wrote:
> >
> > External email : Please do not click links or open attachments until
> > you have verified the sender or the content.
> > On Mon, Aug 14, 2023 at 3:14 PM Yong Wu (吴勇) <Yong.Wu@mediatek.com>
> > wrote:
> > >
> > > On Fri, 2023-08-11 at 11:30 +0800, Chen-Yu Tsai wrote:
> > > >
> > > > External email : Please do not click links or open attachments
> > until
> > > > you have verified the sender or the content.
> > > > On Thu, Aug 10, 2023 at 8:23 PM Yong Wu (吴勇) <
> > Yong.Wu@mediatek.com>
> > > > wrote:
> > > > >
> > > > > On Tue, 2023-08-08 at 17:53 +0800, Chen-Yu Tsai wrote:
> > > > > >
> > > > > > External email : Please do not click links or open
> > attachments
> > > > until
> > > > > > you have verified the sender or the content.
> > > > > > On Fri, Jun 2, 2023 at 5:04 PM Yong Wu <yong.wu@mediatek.com
> > >
> > > > wrote:
> > > > > > >
> > > > > > > From: "Chengci.Xu" <chengci.xu@mediatek.com>
> > > > > > >
> > > > > > > MT8188 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo,
> > the
> > > > > > other
> > > > > > > is for vpp. and 1 INFRA IOMMU.
> > > > > > >
> > > > > > > Signed-off-by: Chengci.Xu <chengci.xu@mediatek.com>
> > > > > > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > > > > > > Reviewed-by: AngeloGioacchino Del Regno <
> > > > > > angelogioacchino.delregno@collabora.com>
> > > > > > > ---
> > > > > > > drivers/iommu/mtk_iommu.c | 49
> > > > > > +++++++++++++++++++++++++++++++++++++++
> > > > > > > 1 file changed, 49 insertions(+)
> > > > > > >
> > > > > > > diff --git a/drivers/iommu/mtk_iommu.c
> > > > b/drivers/iommu/mtk_iommu.c
> > > > > > > index 9c89cf894a4d..5c66af0c45a8 100644
> > > > > > > --- a/drivers/iommu/mtk_iommu.c
> > > > > > > +++ b/drivers/iommu/mtk_iommu.c
> > > > > > > @@ -170,6 +170,7 @@ enum mtk_iommu_plat {
> > > > > > > M4U_MT8173,
> > > > > > > M4U_MT8183,
> > > > > > > M4U_MT8186,
> > > > > > > + M4U_MT8188,
> > > > > > > M4U_MT8192,
> > > > > > > M4U_MT8195,
> > > > > > > M4U_MT8365,
> > > > > > > @@ -1593,6 +1594,51 @@ static const struct
> > mtk_iommu_plat_data
> > > > > > mt8186_data_mm = {
> > > > > > > .iova_region_larb_msk = mt8186_larb_region_msk,
> > > > > > > };
> > > > > > >
> > > > > > > +static const struct mtk_iommu_plat_data mt8188_data_infra
> > = {
> > > > > > > + .m4u_plat = M4U_MT8188,
> > > > > > > + .flags = WR_THROT_EN | DCM_DISABLE |
> > > > > > STD_AXI_MODE | PM_CLK_AO |
> > > > > > > + MTK_IOMMU_TYPE_INFRA |
> > > > > > IFA_IOMMU_PCIE_SUPPORT |
> > > > > > > + PGTABLE_PA_35_EN |
> > > > > > CFG_IFA_MASTER_IN_ATF,
> > > > > >
> > > > > > FWIW, CFG_IFA_MASTER_IN_ATF should not be tied to the
> > compatible
> > > > > > string,
> > > > > > but set via a DT property. The IOMMU controls are secured by
> > > > > > firmware.
> > > > > > It is not a property intrinsically tied to the hardware.
> > > > >
> > > > > The flag CFG_IFA_MASTER_IN_ATF means the registers which
> > > > enable/disable
> > > > > iommu are in the secure world. If the master like pcie want to
> > > > enable
> > > > > iommu, we have to enter secure world to configure it. It should
> > be
> > > > HW
> > > > > intrinsical, right?
> > > >
> > > > If I understand correctly, this is forced by setting some
> > registers.
> > > > The registers are set by the firmware at boot time.
> > >
> > > The register will be set before the masters that have the "iommus="
> > > property probe. If the master doesn't have "iommus=" property in
> > its
> > > dtsi node, this register won't be set, then its iommu will be
> > disabled
> > > and it has to access continuous buffer.
> > >
> > > >
> > > > So if a different firmware that doesn't set the registers is
> > used,
> > > > then the IOMMU is available to non-secure kernel, correct?
> > >
> > > No. The meaning of this register is whether to enable iommu. If the
> > > register are not set, the IOMMU for that master is disabled.
> >
> > For clarity, I'm referring to PERI_MST_PROT [1], not the registers in
> > the
> > IOMMU or LARBs. So not any of the registers used in this patch.
> >
> > If that register doesn't restrict access to IOMMU register space to
> > secure
> > only, then I assume it is controlled by fuses?
>
> Thanks for the clarification. Understand this now. If that register
> doesn't restrict this, the register for enabling the iommu could be
> accessed in normal world.
>
> > [1]
> > https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/be457248c6b0a7f3c61bd95af58372938d13decd/plat/mediatek/drivers/iommu/mt8188/mtk_iommu_plat.c#93
> >
> > > >
> > > > That's why I said that it should not be tied to a particular
> > hardware
> > > > platform, but set using a boolean device tree property.
> > > >
> > > > > >
> > > > > > If on some other project there is no such security
> > requirement
> > > > and
> > > > > > the
> > > > > > IOMMU is opened up to non-secure world, and ATF not even
> > having
> > > > > > support
> > > > > > for the SMC call, this becomes unusable and hard to rectify
> > > > without
> > > > > > introducing a new compatible string.
>
> Then this make sense. Sorry, I don't know if such project exist, I
> guess no, right? we could add it when necessary?
I guess that works. It would be a negative property, such as
"mediatek,iommu-is-non-secure". However, since this lock down is orthogonal
to the SoC model, it would be better to model it as such from the beginning.
ChenYu
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v12 6/7] iommu/mediatek: mt8188: Add iova_region_larb_msk
2023-06-02 9:02 [PATCH v12 0/7] MT8188 IOMMU SUPPORT Yong Wu
` (4 preceding siblings ...)
2023-06-02 9:02 ` [PATCH v12 5/7] iommu/mediatek: Add MT8188 IOMMU Support Yong Wu
@ 2023-06-02 9:02 ` Yong Wu
2023-06-06 14:19 ` Alexandre Mergnat
2023-06-02 9:02 ` [PATCH v12 7/7] MAINTAINERS: iommu/mediatek: Update the header file name Yong Wu
2023-07-25 7:59 ` [PATCH v12 0/7] MT8188 IOMMU SUPPORT Fei Shao
7 siblings, 1 reply; 25+ messages in thread
From: Yong Wu @ 2023-06-02 9:02 UTC (permalink / raw)
To: Joerg Roedel, Will Deacon, Rob Herring, Matthias Brugger
Cc: Robin Murphy, Krzysztof Kozlowski, Yong Wu,
AngeloGioacchino Del Regno, iommu, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, mingyuan.ma, yf.wang,
jianjiao.zeng, chengci.xu
Add iova_region_larb_msk for mt8188. We separate the 16GB iova regions
by each device's larbid/portid.
Refer to include/dt-bindings/memory/mediatek,mt8188-memory-port.h
As commented in the code, larb19(21) means it's larb19 while its SW index
is 21.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/iommu/mtk_iommu.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 5c66af0c45a8..b17d3e7288a7 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -1606,6 +1606,20 @@ static const struct mtk_iommu_plat_data mt8188_data_infra = {
.iova_region_nr = ARRAY_SIZE(single_domain),
};
+static const u32 mt8188_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
+ [0] = {~0, ~0, ~0, ~0}, /* Region0: all ports for larb0/1/2/3 */
+ [1] = {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, ~0, ~0, ~0}, /* Region1: larb19(21)/21(22)/23 */
+ [2] = {0, 0, 0, 0, ~0, ~0, ~0, ~0, /* Region2: the other larbs. */
+ ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0,
+ ~0, ~0, ~0, ~0, ~0, 0, 0, 0,
+ 0, ~0},
+ [3] = {0},
+ [4] = {[24] = BIT(0) | BIT(1)}, /* Only larb27(24) port0/1 */
+ [5] = {[24] = BIT(2) | BIT(3)}, /* Only larb27(24) port2/3 */
+};
+
static const struct mtk_iommu_plat_data mt8188_data_vdo = {
.m4u_plat = M4U_MT8188,
.flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
@@ -1617,6 +1631,7 @@ static const struct mtk_iommu_plat_data mt8188_data_vdo = {
.banks_enable = {true},
.iova_region = mt8192_multi_dom,
.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+ .iova_region_larb_msk = mt8188_larb_region_msk,
.larbid_remap = {{2}, {0}, {21}, {0}, {19}, {9, 10,
11 /* 11a */, 25 /* 11c */},
{13, 0, 29 /* 16b */, 30 /* 17b */, 0}, {5}},
@@ -1633,6 +1648,7 @@ static const struct mtk_iommu_plat_data mt8188_data_vpp = {
.banks_enable = {true},
.iova_region = mt8192_multi_dom,
.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+ .iova_region_larb_msk = mt8188_larb_region_msk,
.larbid_remap = {{1}, {3}, {23}, {7}, {MTK_INVALID_LARBID},
{12, 15, 24 /* 11b */}, {14, MTK_INVALID_LARBID,
16 /* 16a */, 17 /* 17a */, MTK_INVALID_LARBID,
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH v12 6/7] iommu/mediatek: mt8188: Add iova_region_larb_msk
2023-06-02 9:02 ` [PATCH v12 6/7] iommu/mediatek: mt8188: Add iova_region_larb_msk Yong Wu
@ 2023-06-06 14:19 ` Alexandre Mergnat
0 siblings, 0 replies; 25+ messages in thread
From: Alexandre Mergnat @ 2023-06-06 14:19 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Rob Herring, Matthias Brugger
Cc: Robin Murphy, Krzysztof Kozlowski, AngeloGioacchino Del Regno,
iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, mingyuan.ma, yf.wang, jianjiao.zeng,
chengci.xu
On 02/06/2023 11:02, Yong Wu wrote:
> Add iova_region_larb_msk for mt8188. We separate the 16GB iova regions
> by each device's larbid/portid.
> Refer to include/dt-bindings/memory/mediatek,mt8188-memory-port.h
>
> As commented in the code, larb19(21) means it's larb19 while its SW index
> is 21.
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
--
Regards,
Alexandre
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v12 7/7] MAINTAINERS: iommu/mediatek: Update the header file name
2023-06-02 9:02 [PATCH v12 0/7] MT8188 IOMMU SUPPORT Yong Wu
` (5 preceding siblings ...)
2023-06-02 9:02 ` [PATCH v12 6/7] iommu/mediatek: mt8188: Add iova_region_larb_msk Yong Wu
@ 2023-06-02 9:02 ` Yong Wu
2023-07-25 7:59 ` [PATCH v12 0/7] MT8188 IOMMU SUPPORT Fei Shao
7 siblings, 0 replies; 25+ messages in thread
From: Yong Wu @ 2023-06-02 9:02 UTC (permalink / raw)
To: Joerg Roedel, Will Deacon, Rob Herring, Matthias Brugger
Cc: Robin Murphy, Krzysztof Kozlowski, Yong Wu,
AngeloGioacchino Del Regno, iommu, linux-mediatek, devicetree,
linux-kernel, linux-arm-kernel, mingyuan.ma, yf.wang,
jianjiao.zeng, chengci.xu
We add the prefix "mediatek," for the lastest ports header file name,
For example, include/dt-bindings/memory/mediatek,mt8188-memory-port.h.
Add a new entry for this.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 250518fc70ff..dee99e000177 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13151,6 +13151,7 @@ L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
S: Supported
F: Documentation/devicetree/bindings/iommu/mediatek*
F: drivers/iommu/mtk_iommu*
+F: include/dt-bindings/memory/mediatek,mt*-port.h
F: include/dt-bindings/memory/mt*-port.h
MEDIATEK JPEG DRIVER
--
2.25.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH v12 0/7] MT8188 IOMMU SUPPORT
2023-06-02 9:02 [PATCH v12 0/7] MT8188 IOMMU SUPPORT Yong Wu
` (6 preceding siblings ...)
2023-06-02 9:02 ` [PATCH v12 7/7] MAINTAINERS: iommu/mediatek: Update the header file name Yong Wu
@ 2023-07-25 7:59 ` Fei Shao
[not found] ` <cc910b5c3ec130f092a37049d71bb35c20b278a6.camel@mediatek.com>
7 siblings, 1 reply; 25+ messages in thread
From: Fei Shao @ 2023-07-25 7:59 UTC (permalink / raw)
To: Yong Wu
Cc: Joerg Roedel, Will Deacon, Rob Herring, Matthias Brugger,
Robin Murphy, Krzysztof Kozlowski, AngeloGioacchino Del Regno,
iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, mingyuan.ma, yf.wang, jianjiao.zeng,
chengci.xu
On Fri, Jun 2, 2023 at 5:03 PM Yong Wu <yong.wu@mediatek.com> wrote:
>
> MT8188 have 3 IOMMU HWs. 2 IOMMU HW is for multimedia, and 1 IOMMU HW
> is for infra-master, like PCIe.
>
> About the 2 MM IOMMU HW, the connection could be something like this:
>
> IOMMU(VDO) IOMMU(VPP)
> | |
> SMI_COMMON(VDO) SMI_COMMON(VPP)
> --------------- ----------------
> | | ... | | ...
> larb0 larb2 ... larb1 larb3 ...
>
> INFRA IOMMU does not have SMI, the master connects to IOMMU directly.
>
> Although multiple banks supported in MT8188, we only use one of them,
> which means PCIe is put in bank0 of INFRA IOMMU.
>
> So we have two pgtable for MT8188, specifically, these two MM IOMMU HW
> share a pgtable while INFRA IOMMU HW use a independent pgtable.
>
> Another change is that we add some SMC command for INFRA master to
> enable INFRA IOMMU in ATF considering security concerns.
>
> We also adjust the flow of mtk_iommu_config to reduce indention.
A friendly ping - this series was reviewed, but I'm not sure if it's
still on the radar today.
This can be cleanly applied on top of next-20230725.
To give more confidence, I also tested the basic multimedia and infra
functionalities on my MT8188 with this series, so
Tested-by: Fei Shao <fshao@chromium.org>
to the entire v12 series.
Regards,
Fei
^ permalink raw reply [flat|nested] 25+ messages in thread