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From: "周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>
To: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, robh+dt@kernel.org,
	paul.burton@mips.com, paulburton@kernel.org,
	paul@crapouillou.net, mturquette@baylibre.com, sboyd@kernel.org,
	mark.rutland@arm.com, sernia.zhou@foxmail.com,
	zhenwenjin@gmail.com
Subject: [PATCH v2 2/5] clk: Ingenic: Adjust code to make it compatible with new cgu code.
Date: Fri, 13 Dec 2019 23:21:09 +0800	[thread overview]
Message-ID: <1576250472-124315-4-git-send-email-zhouyanjie@wanyeetech.com> (raw)
In-Reply-To: <1576250472-124315-1-git-send-email-zhouyanjie@wanyeetech.com>

Adjust the code in jz47xx-cgu.c and x1000-cgu.c, make it to be
compatible with the new cgu code.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---

Notes:
    v1->v2:
    1.Use two fields (pll_reg & bypass_reg) instead of the 2-values
      array (reg[2]).
    2.Remove the "pll_info->version" and add a "pll_info->rate_multiplier".
    3.Change my Signed-off-by from "Zhou Yanjie <zhouyanjie@zoho.com>"
      to "周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>" because
      the old mailbox is in an unstable state.

 drivers/clk/ingenic/jz4725b-cgu.c | 4 +++-
 drivers/clk/ingenic/jz4740-cgu.c  | 4 +++-
 drivers/clk/ingenic/jz4770-cgu.c  | 8 ++++++--
 drivers/clk/ingenic/jz4780-cgu.c  | 4 +++-
 drivers/clk/ingenic/x1000-cgu.c   | 8 ++++++--
 5 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c
index a3b4635..0b05167 100644
--- a/drivers/clk/ingenic/jz4725b-cgu.c
+++ b/drivers/clk/ingenic/jz4725b-cgu.c
@@ -53,7 +53,9 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
 		"pll", CGU_CLK_PLL,
 		.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
 		.pll = {
-			.reg = CGU_REG_CPPCR,
+			.pll_reg = CGU_REG_CPPCR,
+			.bypass_reg = CGU_REG_CPPCR,
+			.rate_multiplier = 1,
 			.m_shift = 23,
 			.m_bits = 9,
 			.m_offset = 2,
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index 4f0e92c..78f31df 100644
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -68,7 +68,9 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
 		"pll", CGU_CLK_PLL,
 		.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
 		.pll = {
-			.reg = CGU_REG_CPPCR,
+			.pll_reg = CGU_REG_CPPCR,
+			.bypass_reg = CGU_REG_CPPCR,
+			.rate_multiplier = 1,
 			.m_shift = 23,
 			.m_bits = 9,
 			.m_offset = 2,
diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c
index 956dd65..32e476d 100644
--- a/drivers/clk/ingenic/jz4770-cgu.c
+++ b/drivers/clk/ingenic/jz4770-cgu.c
@@ -101,7 +101,9 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
 		"pll0", CGU_CLK_PLL,
 		.parents = { JZ4770_CLK_EXT },
 		.pll = {
-			.reg = CGU_REG_CPPCR0,
+			.pll_reg = CGU_REG_CPPCR0,
+			.bypass_reg = CGU_REG_CPPCR0,
+			.rate_multiplier = 1,
 			.m_shift = 24,
 			.m_bits = 7,
 			.m_offset = 1,
@@ -123,7 +125,9 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
 		"pll1", CGU_CLK_PLL,
 		.parents = { JZ4770_CLK_EXT },
 		.pll = {
-			.reg = CGU_REG_CPPCR1,
+			.pll_reg = CGU_REG_CPPCR1,
+			.bypass_reg = CGU_REG_CPPCR1,
+			.rate_multiplier = 1,
 			.m_shift = 24,
 			.m_bits = 7,
 			.m_offset = 1,
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index ea905ff..d07fff1 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -220,7 +220,9 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
 	/* PLLs */
 
 #define DEF_PLL(name) { \
-	.reg = CGU_REG_ ## name, \
+	.pll_reg = CGU_REG_ ## name, \
+	.bypass_reg = CGU_REG_ ## name, \
+	.rate_multiplier = 1, \
 	.m_shift = 19, \
 	.m_bits = 13, \
 	.m_offset = 1, \
diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c
index b22d87b..d6fe28f 100644
--- a/drivers/clk/ingenic/x1000-cgu.c
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -57,7 +57,9 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
 		"apll", CGU_CLK_PLL,
 		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
 		.pll = {
-			.reg = CGU_REG_APLL,
+			.pll_reg = CGU_REG_APLL,
+			.bypass_reg = CGU_REG_APLL,
+			.rate_multiplier = 1,
 			.m_shift = 24,
 			.m_bits = 7,
 			.m_offset = 1,
@@ -78,7 +80,9 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
 		"mpll", CGU_CLK_PLL,
 		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
 		.pll = {
-			.reg = CGU_REG_MPLL,
+			.pll_reg = CGU_REG_MPLL,
+			.bypass_reg = CGU_REG_MPLL,
+			.rate_multiplier = 1,
 			.m_shift = 24,
 			.m_bits = 7,
 			.m_offset = 1,
-- 
2.7.4


  parent reply	other threads:[~2019-12-13 20:38 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-13 15:21 clk: Ingenic: Add support for the X1830 v2 周琰杰 (Zhou Yanjie)
2019-12-13 15:21 ` [PATCH v2 0/5] " 周琰杰 (Zhou Yanjie)
2019-12-13 15:21 ` [PATCH v2 1/5] clk: Ingenic: Adjust cgu code to make it compatible with X1830 周琰杰 (Zhou Yanjie)
2019-12-13 21:25   ` Paul Cercueil
2019-12-14 12:16     ` zhouyanjie
2019-12-13 15:21 ` 周琰杰 (Zhou Yanjie) [this message]
2019-12-13 15:21 ` [PATCH v2 3/5] dt-bindings: clock: Add X1830 bindings 周琰杰 (Zhou Yanjie)
2019-12-13 15:21 ` [PATCH v2 4/5] clk: Ingenic: Add CGU driver for X1830 周琰杰 (Zhou Yanjie)
2019-12-13 15:21 ` [PATCH v2 5/5] clk: Ingenic: Remove unnecessary spinlock when reading registers 周琰杰 (Zhou Yanjie)

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