From: "周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>
To: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
robh+dt@kernel.org, paul.burton@mips.com, paulburton@kernel.org,
jhogan@kernel.org, miquel.raynal@bootlin.com,
mark.rutland@arm.com, syq@debian.org, ralf@linux-mips.org,
tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org,
jiaxun.yang@flygoat.com, chenhc@lemote.com,
daniel.lezcano@linaro.org, ebiederm@xmission.com,
keescook@chromium.org, ak@linux.intel.com, krzk@kernel.org,
paul@crapouillou.net, prasannatsmkumar@gmail.com,
sernia.zhou@foxmail.com, zhenwenjin@gmail.com
Subject: [PATCH 3/6] dt-bindings: MIPS: Document Ingenic SoCs binding.
Date: Tue, 14 Jan 2020 00:43:30 +0800 [thread overview]
Message-ID: <1578933813-80122-5-git-send-email-zhouyanjie@wanyeetech.com> (raw)
In-Reply-To: <1578933813-80122-1-git-send-email-zhouyanjie@wanyeetech.com>
Document the available properties for the SoC root node and the
CPU nodes of the devicetree for the Ingenic XBurst SoCs.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
.../bindings/mips/ingenic/ingenic,cpu.txt | 32 ++++++++++++++++++++++
.../bindings/mips/ingenic/ingenic,soc,txt | 18 ++++++++++++
2 files changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt
diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
new file mode 100644
index 00000000..f23e9be
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
@@ -0,0 +1,32 @@
+Bindings for Ingenic XBurst family CPUs.
+
+Required properties:
+- device_type: Must be "cpu".
+- compatible: One of:
+ - "ingenic,xburst".
+ - "ingenic,xburst2".
+- reg: The number of the CPU.
+
+Example:
+cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst";
+ reg = <0>;
+
+ clocks = <&cgu JZ4780_CLK_CPU>;
+ clock-names = "cpu";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst";
+ reg = <1>;
+
+ clocks = <&cgu JZ4780_CLK_CORE1>;
+ clock-names = "cpu";
+ };
+};
diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt
new file mode 100644
index 00000000..c731fa3
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,soc,txt
@@ -0,0 +1,18 @@
+Bindings for Ingenic SoCs with XBurst CPU inside.
+
+Required properties:
+- compatible: One of:
+ - "ingenic,jz4740".
+ - "ingenic,jz4725b".
+ - "ingenic,jz4760".
+ - "ingenic,jz4760b".
+ - "ingenic,jz4770".
+ - "ingenic,jz4780".
+ - "ingenic,x1000".
+ - "ingenic,x1000e".
+ - "ingenic,x1500".
+
+Example:
+#address-cells = <1>;
+#size-cells = <1>;
+compatible = "ingenic,jz4780";
--
2.7.4
next prev parent reply other threads:[~2020-01-13 16:44 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <Introduce SMP support for CI20 (based on JZ4780).>
[not found] ` <1578933813-80122-1-git-send-email-zhouyanjie@wanyeetech.com>
2020-01-13 16:43 ` [PATCH 0/6] Introduce SMP support for JZ4780 周琰杰 (Zhou Yanjie)
2020-01-13 16:43 ` [PATCH 1/6] MIPS: JZ4780: Introduce SMP support 周琰杰 (Zhou Yanjie)
2020-01-14 4:55 ` Jiaxun Yang
2020-01-14 13:46 ` Zhou Yanjie
2020-01-13 16:43 ` [PATCH 2/6] clocksource: Ingenic: Add high resolution timer support for SMP 周琰杰 (Zhou Yanjie)
2020-01-13 16:43 ` 周琰杰 (Zhou Yanjie) [this message]
2020-01-14 4:59 ` [PATCH 3/6] dt-bindings: MIPS: Document Ingenic SoCs binding Jiaxun Yang
2020-01-14 13:48 ` Zhou Yanjie
2020-01-13 16:43 ` [PATCH 4/6] MIPS: Ingenic: Add 'cpus' node for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2020-01-13 16:43 ` [PATCH 5/6] MIPS: CI20: Modify DTS to support high resolution timer for SMP 周琰杰 (Zhou Yanjie)
2020-01-13 16:43 ` [PATCH 6/6] MIPS: CI20: Update defconfig to support SMP 周琰杰 (Zhou Yanjie)
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