* [PATCH V6 1/3] MIPS: context switch: Use save/restore instead of set/clear for Status.CU2
@ 2020-09-07 10:06 Huacai Chen
2020-09-07 10:06 ` [PATCH V6 2/3] MIPS: Loongson-3: Enable COP2 usage in kernel Huacai Chen
2020-09-07 10:06 ` [PATCH V6 3/3] MIPS: Loongson-3: Calculate ra properly when unwinding the stack Huacai Chen
0 siblings, 2 replies; 7+ messages in thread
From: Huacai Chen @ 2020-09-07 10:06 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: linux-mips, Fuxin Zhang, Huacai Chen, Jiaxun Yang, Huacai Chen
Some processors (such as Loongson-3) need to enable CU2 in kernel mode,
current set/clear method will lose Status.CU2 during context switching,
so use save/restore method instead.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/include/asm/switch_to.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
index 0b0a93b..a4374b4 100644
--- a/arch/mips/include/asm/switch_to.h
+++ b/arch/mips/include/asm/switch_to.h
@@ -117,6 +117,8 @@ do { \
__restore_dsp(next); \
} \
if (cop2_present) { \
+ u32 status = read_c0_status(); \
+ \
set_c0_status(ST0_CU2); \
if ((KSTK_STATUS(prev) & ST0_CU2)) { \
if (cop2_lazy_restore) \
@@ -127,7 +129,7 @@ do { \
!cop2_lazy_restore) { \
cop2_restore(next); \
} \
- clear_c0_status(ST0_CU2); \
+ write_c0_status(status); \
} \
__clear_r5_hw_ll_bit(); \
__clear_software_ll_bit(); \
--
2.7.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH V6 2/3] MIPS: Loongson-3: Enable COP2 usage in kernel
2020-09-07 10:06 [PATCH V6 1/3] MIPS: context switch: Use save/restore instead of set/clear for Status.CU2 Huacai Chen
@ 2020-09-07 10:06 ` Huacai Chen
2020-09-14 11:11 ` Thomas Bogendoerfer
2020-09-07 10:06 ` [PATCH V6 3/3] MIPS: Loongson-3: Calculate ra properly when unwinding the stack Huacai Chen
1 sibling, 1 reply; 7+ messages in thread
From: Huacai Chen @ 2020-09-07 10:06 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: linux-mips, Fuxin Zhang, Huacai Chen, Jiaxun Yang, Huacai Chen
Loongson-3's COP2 is Multi-Media coprocessor, it is disabled in kernel
mode by default. However, gslq/gssq (16-bytes load/store instructions)
overrides the instruction format of lwc2/swc2. If we wan't to use gslq/
gssq for optimization in kernel, we should enable COP2 usage in kernel.
Please pay attention that in this patch we only enable COP2 in kernel,
which means it will lose ST0_CU2 when a process go to user space (try
to use COP2 in user space will trigger an exception and then grab COP2,
which is similar to FPU). And as a result, we need to modify the context
switching code because the new scheduled process doesn't contain ST0_CU2
in its THERAD_STATUS probably.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
V3: Stop using ST0_MM and use ST0_CU2 instead (Thank Thomas and Maciej).
V4: Adopt Thomas's suggestion to improve coding style.
V5: Use ST0_KERNEL_CUMASK in all possible places to avoid #ifdefs.
V6: Modify switch_to() and don't touch r4k_switch.S.
arch/mips/boot/compressed/head.S | 5 +++++
arch/mips/include/asm/mipsregs.h | 7 +++++++
arch/mips/include/asm/stackframe.h | 6 +++---
arch/mips/kernel/head.S | 2 +-
arch/mips/kernel/process.c | 4 ++--
arch/mips/kernel/traps.c | 2 +-
6 files changed, 19 insertions(+), 7 deletions(-)
diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
index 409cb48..9fc88ec 100644
--- a/arch/mips/boot/compressed/head.S
+++ b/arch/mips/boot/compressed/head.S
@@ -14,11 +14,16 @@
#include <asm/asm.h>
#include <asm/regdef.h>
+#include <asm/mipsregs.h>
.set noreorder
.cprestore
LEAF(start)
start:
+ mfc0 t0, CP0_STATUS
+ or t0, ST0_KERNEL_CUMASK
+ mtc0 t0, CP0_STATUS
+
/* Save boot rom start args */
move s0, a0
move s1, a1
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 1a03fdc2..36b8433 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -389,6 +389,13 @@
#define ST0_CU3 0x80000000
#define ST0_XX 0x80000000 /* MIPS IV naming */
+/* in-kernel enabled CUs */
+#ifdef CONFIG_CPU_LOONGSON64
+#define ST0_KERNEL_CUMASK (ST0_CU0 | ST0_CU2)
+#else
+#define ST0_KERNEL_CUMASK ST0_CU0
+#endif
+
/*
* Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
*/
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 3e8d2aa..aa430a6 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -450,7 +450,7 @@
*/
.macro CLI
mfc0 t0, CP0_STATUS
- li t1, ST0_CU0 | STATMASK
+ li t1, ST0_KERNEL_CUMASK | STATMASK
or t0, t1
xori t0, STATMASK
mtc0 t0, CP0_STATUS
@@ -463,7 +463,7 @@
*/
.macro STI
mfc0 t0, CP0_STATUS
- li t1, ST0_CU0 | STATMASK
+ li t1, ST0_KERNEL_CUMASK | STATMASK
or t0, t1
xori t0, STATMASK & ~1
mtc0 t0, CP0_STATUS
@@ -477,7 +477,7 @@
*/
.macro KMODE
mfc0 t0, CP0_STATUS
- li t1, ST0_CU0 | (STATMASK & ~1)
+ li t1, ST0_KERNEL_CUMASK | (STATMASK & ~1)
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
andi t2, t0, ST0_IEP
srl t2, 2
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index 7dd234e..61b7358 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -35,7 +35,7 @@
.macro setup_c0_status set clr
.set push
mfc0 t0, CP0_STATUS
- or t0, ST0_CU0|\set|0x1f|\clr
+ or t0, ST0_KERNEL_CUMASK|\set|0x1f|\clr
xor t0, 0x1f|\clr
mtc0 t0, CP0_STATUS
.set noreorder
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index f5dc316..b36297e 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -68,7 +68,7 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
unsigned long status;
/* New thread loses kernel privileges. */
- status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK);
+ status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_CU2|ST0_FR|KU_MASK);
status |= KU_USER;
regs->cp0_status = status;
lose_fpu(0);
@@ -133,7 +133,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
childregs = (struct pt_regs *) childksp - 1;
/* Put the stack after the struct pt_regs. */
childksp = (unsigned long) childregs;
- p->thread.cp0_status = read_c0_status() & ~(ST0_CU2|ST0_CU1);
+ p->thread.cp0_status = (read_c0_status() & ~(ST0_CU2|ST0_CU1)) | ST0_KERNEL_CUMASK;
if (unlikely(p->flags & PF_KTHREAD)) {
/* kernel thread */
unsigned long status = p->thread.cp0_status;
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index cf788591..e035295 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2204,7 +2204,7 @@ static void configure_status(void)
* flag that some firmware may have left set and the TS bit (for
* IP27). Set XX for ISA IV code to work.
*/
- unsigned int status_set = ST0_CU0;
+ unsigned int status_set = ST0_KERNEL_CUMASK;
#ifdef CONFIG_64BIT
status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
#endif
--
2.7.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH V6 3/3] MIPS: Loongson-3: Calculate ra properly when unwinding the stack
2020-09-07 10:06 [PATCH V6 1/3] MIPS: context switch: Use save/restore instead of set/clear for Status.CU2 Huacai Chen
2020-09-07 10:06 ` [PATCH V6 2/3] MIPS: Loongson-3: Enable COP2 usage in kernel Huacai Chen
@ 2020-09-07 10:06 ` Huacai Chen
1 sibling, 0 replies; 7+ messages in thread
From: Huacai Chen @ 2020-09-07 10:06 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: linux-mips, Fuxin Zhang, Huacai Chen, Jiaxun Yang, Huacai Chen
Loongson-3 has 16-bytes load/store instructions: gslq and gssq. This
patch calculate ra properly when unwinding the stack, if ra is saved
by gssq and restored by gslq.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/kernel/process.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index b36297e..37f05c8 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -279,7 +279,21 @@ static inline int is_ra_save_ins(union mips_instruction *ip, int *poff)
*poff = ip->i_format.simmediate / sizeof(ulong);
return 1;
}
-
+#ifdef CONFIG_CPU_LOONGSON64
+ if ((ip->loongson3_lswc2_format.opcode == swc2_op) &&
+ (ip->loongson3_lswc2_format.ls == 1) &&
+ (ip->loongson3_lswc2_format.fr == 0) &&
+ (ip->loongson3_lswc2_format.base == 29)) {
+ if (ip->loongson3_lswc2_format.rt == 31) {
+ *poff = ip->loongson3_lswc2_format.offset << 1;
+ return 1;
+ }
+ if (ip->loongson3_lswc2_format.rq == 31) {
+ *poff = (ip->loongson3_lswc2_format.offset << 1) + 1;
+ return 1;
+ }
+ }
+#endif
return 0;
#endif
}
--
2.7.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH V6 2/3] MIPS: Loongson-3: Enable COP2 usage in kernel
2020-09-07 10:06 ` [PATCH V6 2/3] MIPS: Loongson-3: Enable COP2 usage in kernel Huacai Chen
@ 2020-09-14 11:11 ` Thomas Bogendoerfer
2020-09-15 5:21 ` Jiaxun Yang
0 siblings, 1 reply; 7+ messages in thread
From: Thomas Bogendoerfer @ 2020-09-14 11:11 UTC (permalink / raw)
To: Huacai Chen; +Cc: linux-mips, Fuxin Zhang, Huacai Chen, Jiaxun Yang
On Mon, Sep 07, 2020 at 06:06:08PM +0800, Huacai Chen wrote:
>
> diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
> index 409cb48..9fc88ec 100644
> --- a/arch/mips/boot/compressed/head.S
> +++ b/arch/mips/boot/compressed/head.S
> @@ -14,11 +14,16 @@
>
> #include <asm/asm.h>
> #include <asm/regdef.h>
> +#include <asm/mipsregs.h>
>
> .set noreorder
> .cprestore
> LEAF(start)
> start:
> + mfc0 t0, CP0_STATUS
> + or t0, ST0_KERNEL_CUMASK
> + mtc0 t0, CP0_STATUS
> +
> /* Save boot rom start args */
> move s0, a0
> move s1, a1
please to compiler flags in arch/mips/boot/compressed/Makefile to
disable generation of instruction not supported, if CU2 is disabled
(and don't forget about 2ef).
Rest of the patch LGTM.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH V6 2/3] MIPS: Loongson-3: Enable COP2 usage in kernel
2020-09-14 11:11 ` Thomas Bogendoerfer
@ 2020-09-15 5:21 ` Jiaxun Yang
2020-09-16 6:22 ` Huacai Chen
0 siblings, 1 reply; 7+ messages in thread
From: Jiaxun Yang @ 2020-09-15 5:21 UTC (permalink / raw)
To: Thomas Bogendoerfer, Huacai Chen; +Cc: linux-mips, Fuxin Zhang, Huacai Chen
在 2020/9/14 19:11, Thomas Bogendoerfer 写道:
> On Mon, Sep 07, 2020 at 06:06:08PM +0800, Huacai Chen wrote:
>> diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
>> index 409cb48..9fc88ec 100644
>> --- a/arch/mips/boot/compressed/head.S
>> +++ b/arch/mips/boot/compressed/head.S
>> @@ -14,11 +14,16 @@
>>
>> #include <asm/asm.h>
>> #include <asm/regdef.h>
>> +#include <asm/mipsregs.h>
>>
>> .set noreorder
>> .cprestore
>> LEAF(start)
>> start:
>> + mfc0 t0, CP0_STATUS
>> + or t0, ST0_KERNEL_CUMASK
>> + mtc0 t0, CP0_STATUS
>> +
>> /* Save boot rom start args */
>> move s0, a0
>> move s1, a1
> please to compiler flags in arch/mips/boot/compressed/Makefile to
> disable generation of instruction not supported, if CU2 is disabled
> (and don't forget about 2ef).
I don't think it's worthy to have different CFLAGS between zboot and rest of
the kernel.
On GCC version prior to 9, there is no flag to control the generation of
these instructions, unless drop supplied "-march=loongson3a" option,
that's messy and unreliable for Makefile.
By contrast, enabling CU2 in zboot have no side effect. Some firmware even
did it in early ROM initilization stage.
Thanks.
- Jiaxun
>
> Rest of the patch LGTM.
>
> Thomas.
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH V6 2/3] MIPS: Loongson-3: Enable COP2 usage in kernel
2020-09-15 5:21 ` Jiaxun Yang
@ 2020-09-16 6:22 ` Huacai Chen
2020-09-16 10:18 ` Thomas Bogendoerfer
0 siblings, 1 reply; 7+ messages in thread
From: Huacai Chen @ 2020-09-16 6:22 UTC (permalink / raw)
To: Jiaxun Yang; +Cc: Thomas Bogendoerfer, open list:MIPS, Fuxin Zhang
H, Thomas,
On Tue, Sep 15, 2020 at 1:23 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
>
>
> 在 2020/9/14 19:11, Thomas Bogendoerfer 写道:
> > On Mon, Sep 07, 2020 at 06:06:08PM +0800, Huacai Chen wrote:
> >> diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
> >> index 409cb48..9fc88ec 100644
> >> --- a/arch/mips/boot/compressed/head.S
> >> +++ b/arch/mips/boot/compressed/head.S
> >> @@ -14,11 +14,16 @@
> >>
> >> #include <asm/asm.h>
> >> #include <asm/regdef.h>
> >> +#include <asm/mipsregs.h>
> >>
> >> .set noreorder
> >> .cprestore
> >> LEAF(start)
> >> start:
> >> + mfc0 t0, CP0_STATUS
> >> + or t0, ST0_KERNEL_CUMASK
> >> + mtc0 t0, CP0_STATUS
> >> +
> >> /* Save boot rom start args */
> >> move s0, a0
> >> move s1, a1
> > please to compiler flags in arch/mips/boot/compressed/Makefile to
> > disable generation of instruction not supported, if CU2 is disabled
> > (and don't forget about 2ef).
>
> I don't think it's worthy to have different CFLAGS between zboot and rest of
> the kernel.
>
> On GCC version prior to 9, there is no flag to control the generation of
> these instructions, unless drop supplied "-march=loongson3a" option,
> that's messy and unreliable for Makefile.
>
> By contrast, enabling CU2 in zboot have no side effect. Some firmware even
> did it in early ROM initilization stage.
What do you think about? I agree with Jiaxun, but disable lq/sq in
zboot is also acceptable for me.
Huacai
>
> Thanks.
>
> - Jiaxun
>
> >
> > Rest of the patch LGTM.
> >
> > Thomas.
> >
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH V6 2/3] MIPS: Loongson-3: Enable COP2 usage in kernel
2020-09-16 6:22 ` Huacai Chen
@ 2020-09-16 10:18 ` Thomas Bogendoerfer
0 siblings, 0 replies; 7+ messages in thread
From: Thomas Bogendoerfer @ 2020-09-16 10:18 UTC (permalink / raw)
To: Huacai Chen; +Cc: Jiaxun Yang, open list:MIPS, Fuxin Zhang
On Wed, Sep 16, 2020 at 02:22:40AM -0400, Huacai Chen wrote:
> H, Thomas,
>
> On Tue, Sep 15, 2020 at 1:23 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> >
> >
> >
> > 在 2020/9/14 19:11, Thomas Bogendoerfer 写道:
> > > On Mon, Sep 07, 2020 at 06:06:08PM +0800, Huacai Chen wrote:
> > >> diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
> > >> index 409cb48..9fc88ec 100644
> > >> --- a/arch/mips/boot/compressed/head.S
> > >> +++ b/arch/mips/boot/compressed/head.S
> > >> @@ -14,11 +14,16 @@
> > >>
> > >> #include <asm/asm.h>
> > >> #include <asm/regdef.h>
> > >> +#include <asm/mipsregs.h>
> > >>
> > >> .set noreorder
> > >> .cprestore
> > >> LEAF(start)
> > >> start:
> > >> + mfc0 t0, CP0_STATUS
> > >> + or t0, ST0_KERNEL_CUMASK
> > >> + mtc0 t0, CP0_STATUS
> > >> +
> > >> /* Save boot rom start args */
> > >> move s0, a0
> > >> move s1, a1
> > > please to compiler flags in arch/mips/boot/compressed/Makefile to
> > > disable generation of instruction not supported, if CU2 is disabled
> > > (and don't forget about 2ef).
> >
> > I don't think it's worthy to have different CFLAGS between zboot and rest of
> > the kernel.
> >
> > On GCC version prior to 9, there is no flag to control the generation of
> > these instructions, unless drop supplied "-march=loongson3a" option,
> > that's messy and unreliable for Makefile.
> >
> > By contrast, enabling CU2 in zboot have no side effect. Some firmware even
> > did it in early ROM initilization stage.
> What do you think about? I agree with Jiaxun, but disable lq/sq in
> zboot is also acceptable for me.
I prefer to keep zboot as minimal as possible, so please disable lq/sq.
Thank you.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-09-16 10:26 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2020-09-07 10:06 [PATCH V6 1/3] MIPS: context switch: Use save/restore instead of set/clear for Status.CU2 Huacai Chen
2020-09-07 10:06 ` [PATCH V6 2/3] MIPS: Loongson-3: Enable COP2 usage in kernel Huacai Chen
2020-09-14 11:11 ` Thomas Bogendoerfer
2020-09-15 5:21 ` Jiaxun Yang
2020-09-16 6:22 ` Huacai Chen
2020-09-16 10:18 ` Thomas Bogendoerfer
2020-09-07 10:06 ` [PATCH V6 3/3] MIPS: Loongson-3: Calculate ra properly when unwinding the stack Huacai Chen
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