From: James Hogan <james.hogan@imgtec.com>
To: linux-mips@linux-mips.org
Cc: "James Hogan" <james.hogan@imgtec.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Radim Krčmář" <rkrcmar@redhat.com>,
"Ralf Baechle" <ralf@linux-mips.org>,
kvm@vger.kernel.org
Subject: [PATCH 3/5] KVM: MIPS/T&E: Default to reset vector
Date: Wed, 1 Feb 2017 14:19:25 +0000 [thread overview]
Message-ID: <d403f824532f5ec3872c084277095be6ff957e0d.1485958267.git-series.james.hogan@imgtec.com> (raw)
Message-ID: <20170201141925.vf3BYT2caHVJRUMRgqNvFVgMcbEQY5N6O8ubVNmePRk@z> (raw)
In-Reply-To: <cover.7aeb0f08d03b5d18b5332cdb1b38a8f057d310ac.1485958267.git-series.james.hogan@imgtec.com>
Set the default VCPU state closer to the architectural reset state, with
PC pointing at the reset vector (uncached PA 0x1fc00000, which for KVM
T&E is VA 0x5fc00000), and with CP0_Status.BEV and CP0_Status.ERL to 1.
Although QEMU at least will overwrite this state, it makes sense to do
this now that CP0_EBase is properly implemented to check BEV, and now
that we support a sparse GPA layout potentially with a boot ROM at GPA
0x1fc00000.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
---
arch/mips/kvm/trap_emul.c | 6 ++++++
1 file changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/mips/kvm/trap_emul.c b/arch/mips/kvm/trap_emul.c
index 27082994e07d..86a104947e4d 100644
--- a/arch/mips/kvm/trap_emul.c
+++ b/arch/mips/kvm/trap_emul.c
@@ -614,6 +614,9 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
/* Set Wait IE/IXMT Ignore in Config7, IAR, AR */
kvm_write_c0_guest_config7(cop0, (MIPS_CONF7_WII) | (1 << 10));
+ /* Status */
+ kvm_write_c0_guest_status(cop0, ST0_BEV | ST0_ERL);
+
/*
* Setup IntCtl defaults, compatibility mode for timer interrupts (HW5)
*/
@@ -623,6 +626,9 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
kvm_write_c0_guest_ebase(cop0, KVM_GUEST_KSEG0 |
(vcpu_id & MIPS_EBASE_CPUNUM));
+ /* Put PC at guest reset vector */
+ vcpu->arch.pc = KVM_GUEST_CKSEG1ADDR(0x1fc00000);
+
return 0;
}
--
git-series 0.8.10
next prev parent reply other threads:[~2017-02-01 14:19 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-01 14:19 [PATCH 0/5] KVM: MIPS/T&E: Miscellaneous improvements James Hogan
2017-02-01 14:19 ` James Hogan
2017-02-01 14:19 ` [PATCH 1/5] KVM: MIPS/T&E: Move CP0 register access into T&E James Hogan
2017-02-01 14:19 ` James Hogan
2017-02-01 14:19 ` [PATCH 2/5] KVM: MIPS/T&E: Implement CP0_EBase register James Hogan
2017-02-01 14:19 ` James Hogan
2017-02-01 14:19 ` James Hogan [this message]
2017-02-01 14:19 ` [PATCH 3/5] KVM: MIPS/T&E: Default to reset vector James Hogan
2017-02-01 14:19 ` [PATCH 4/5] KVM: MIPS/T&E: Expose CP0_EntryLo0/1 registers James Hogan
2017-02-01 14:19 ` James Hogan
2017-02-01 14:19 ` [PATCH 5/5] KVM: MIPS/T&E: Expose read-only CP0_IntCtl register James Hogan
2017-02-01 14:19 ` James Hogan
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