* [PATCH net-next 1/3] net: dsa: mt7530: Convert to PHYLINK API
2019-07-24 19:25 [PATCH net-next 0/3] net: dsa: MT7530: Convert to PHYLINK and add support for port 5 René van Dorst
@ 2019-07-24 19:25 ` René van Dorst
2019-07-27 18:48 ` Russell King - ARM Linux admin
2019-07-24 19:25 ` [PATCH net-next 2/3] dt-bindings: net: dsa: mt7530: Add support for port 5 René van Dorst
2019-07-24 19:25 ` [PATCH net-next 3/3] " René van Dorst
2 siblings, 1 reply; 13+ messages in thread
From: René van Dorst @ 2019-07-24 19:25 UTC (permalink / raw)
To: netdev
Cc: frank-w, sean.wang, f.fainelli, linux, davem, matthias.bgg,
andrew, vivien.didelot, john, linux-mediatek, linux-mips,
robh+dt, devicetree, René van Dorst
Convert mt7530 to PHYLINK API
Signed-off-by: René van Dorst <opensource@vdorst.com>
rfc->v1:
* Renamed P5_MODE_* to P5_INTF_SEL_*. fits the function more
* Convert if-statement for speed bits to a switch suggested by
Daniel Santos
* Refactor flow_control pause bits and don't use state->link in
mt7530_phylink_mac_config() suggested by Russell King
* Move MAC tx/rx en/disable to mt7530_phylink_mac_link_up/down()
suggested by Russell King
* Always support PHY_INTERFACE_MODE_NA in mt7530_phylink_validate()
suggested by Russell King
* Added phylink_set_port_modes() in mt7530_phylink_validate() suggested
by Russell King
* Remove dev_err on the end of mt7530_phylink_mac_config() suggested by
Russell King
---
drivers/net/dsa/mt7530.c | 255 +++++++++++++++++++++++++++++----------
drivers/net/dsa/mt7530.h | 32 +++--
2 files changed, 203 insertions(+), 84 deletions(-)
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index 3181e95586d6..73a2204bf81a 100644
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -13,7 +13,7 @@
#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include <linux/of_platform.h>
-#include <linux/phy.h>
+#include <linux/phylink.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
@@ -633,63 +633,6 @@ mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
return ARRAY_SIZE(mt7530_mib);
}
-static void mt7530_adjust_link(struct dsa_switch *ds, int port,
- struct phy_device *phydev)
-{
- struct mt7530_priv *priv = ds->priv;
-
- if (phy_is_pseudo_fixed_link(phydev)) {
- dev_dbg(priv->dev, "phy-mode for master device = %x\n",
- phydev->interface);
-
- /* Setup TX circuit incluing relevant PAD and driving */
- mt7530_pad_clk_setup(ds, phydev->interface);
-
- if (priv->id == ID_MT7530) {
- /* Setup RX circuit, relevant PAD and driving on the
- * host which must be placed after the setup on the
- * device side is all finished.
- */
- mt7623_pad_clk_setup(ds);
- }
- } else {
- u16 lcl_adv = 0, rmt_adv = 0;
- u8 flowctrl;
- u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE;
-
- switch (phydev->speed) {
- case SPEED_1000:
- mcr |= PMCR_FORCE_SPEED_1000;
- break;
- case SPEED_100:
- mcr |= PMCR_FORCE_SPEED_100;
- break;
- }
-
- if (phydev->link)
- mcr |= PMCR_FORCE_LNK;
-
- if (phydev->duplex) {
- mcr |= PMCR_FORCE_FDX;
-
- if (phydev->pause)
- rmt_adv = LPA_PAUSE_CAP;
- if (phydev->asym_pause)
- rmt_adv |= LPA_PAUSE_ASYM;
-
- lcl_adv = linkmode_adv_to_lcl_adv_t(
- phydev->advertising);
- flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
-
- if (flowctrl & FLOW_CTRL_TX)
- mcr |= PMCR_TX_FC_EN;
- if (flowctrl & FLOW_CTRL_RX)
- mcr |= PMCR_RX_FC_EN;
- }
- mt7530_write(priv, MT7530_PMCR_P(port), mcr);
- }
-}
-
static int
mt7530_cpu_port_enable(struct mt7530_priv *priv,
int port)
@@ -698,9 +641,6 @@ mt7530_cpu_port_enable(struct mt7530_priv *priv,
mt7530_write(priv, MT7530_PVC_P(port),
PORT_SPEC_TAG);
- /* Setup the MAC by default for the cpu port */
- mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK);
-
/* Disable auto learning on the cpu port */
mt7530_set(priv, MT7530_PSC_P(port), SA_DIS);
@@ -728,9 +668,6 @@ mt7530_port_enable(struct dsa_switch *ds, int port,
mutex_lock(&priv->reg_mutex);
- /* Setup the MAC for the user port */
- mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK);
-
/* Allow the user port gets connected to the cpu port and also
* restore the port matrix if the port is the member of a certain
* bridge.
@@ -739,7 +676,7 @@ mt7530_port_enable(struct dsa_switch *ds, int port,
priv->ports[port].enable = true;
mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
priv->ports[port].pm);
- mt7530_port_set_status(priv, port, 1);
+ mt7530_port_set_status(priv, port, 0);
mutex_unlock(&priv->reg_mutex);
@@ -1299,6 +1236,8 @@ mt7530_setup(struct dsa_switch *ds)
val |= MHWTRAP_MANUAL;
mt7530_write(priv, MT7530_MHWTRAP, val);
+ priv->p6_interface = PHY_INTERFACE_MODE_NA;
+
/* Enable and reset MIB counters */
mt7530_mib_reset(ds);
@@ -1323,6 +1262,186 @@ mt7530_setup(struct dsa_switch *ds)
return 0;
}
+static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port,
+ unsigned int mode,
+ const struct phylink_link_state *state)
+{
+ struct mt7530_priv *priv = ds->priv;
+ u32 mcr_cur, mcr_new;
+
+ switch (port) {
+ case 0: /* Internal phy */
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ if (state->interface != PHY_INTERFACE_MODE_GMII)
+ return;
+ break;
+ /* case 5: Port 5 is not supported! */
+ case 6: /* 1st cpu port */
+ if (state->interface != PHY_INTERFACE_MODE_RGMII &&
+ state->interface != PHY_INTERFACE_MODE_TRGMII)
+ return;
+
+ if (priv->p6_interface == state->interface)
+ break;
+ /* Setup TX circuit incluing relevant PAD and driving */
+ mt7530_pad_clk_setup(ds, state->interface);
+
+ if (priv->id == ID_MT7530) {
+ /* Setup RX circuit, relevant PAD and driving on the
+ * host which must be placed after the setup on the
+ * device side is all finished.
+ */
+ mt7623_pad_clk_setup(ds);
+ }
+ priv->p6_interface = state->interface;
+ break;
+ default:
+ dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
+ return;
+ }
+
+ mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
+ mcr_new = mcr_cur;
+ mcr_new &= ~(PMCR_FORCE_SPEED_1000 | PMCR_FORCE_SPEED_100 |
+ PMCR_FORCE_FDX | PMCR_TX_FC_EN | PMCR_RX_FC_EN);
+ mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
+ PMCR_BACKPR_EN | PMCR_FORCE_MODE | PMCR_FORCE_LNK;
+
+ switch (state->speed) {
+ case SPEED_1000:
+ mcr_new |= PMCR_FORCE_SPEED_1000;
+ break;
+ case SPEED_100:
+ mcr_new |= PMCR_FORCE_SPEED_100;
+ break;
+ }
+ if (state->duplex == DUPLEX_FULL) {
+ mcr_new |= PMCR_FORCE_FDX;
+ if (state->pause & MLO_PAUSE_TX)
+ mcr_new |= PMCR_TX_FC_EN;
+ if (state->pause & MLO_PAUSE_RX)
+ mcr_new |= PMCR_RX_FC_EN;
+ }
+
+ if (mcr_new != mcr_cur)
+ mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
+}
+
+static void mt7530_phylink_mac_link_down(struct dsa_switch *ds, int port,
+ unsigned int mode,
+ phy_interface_t interface)
+{
+ struct mt7530_priv *priv = ds->priv;
+
+ mt7530_port_set_status(priv, port, 0);
+}
+
+static void mt7530_phylink_mac_link_up(struct dsa_switch *ds, int port,
+ unsigned int mode,
+ phy_interface_t interface,
+ struct phy_device *phydev)
+{
+ struct mt7530_priv *priv = ds->priv;
+
+ mt7530_port_set_status(priv, port, 1);
+}
+
+static void mt7530_phylink_validate(struct dsa_switch *ds, int port,
+ unsigned long *supported,
+ struct phylink_link_state *state)
+{
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+
+ switch (port) {
+ case 0: /* Internal phy */
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ if (state->interface != PHY_INTERFACE_MODE_NA &&
+ state->interface != PHY_INTERFACE_MODE_GMII)
+ goto unsupported;
+ break;
+ /* case 5: Port 5 not supported! */
+ case 6: /* 1st cpu port */
+ if (state->interface != PHY_INTERFACE_MODE_NA &&
+ state->interface != PHY_INTERFACE_MODE_RGMII &&
+ state->interface != PHY_INTERFACE_MODE_TRGMII)
+ goto unsupported;
+ break;
+ default:
+ linkmode_zero(supported);
+ dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
+ return;
+ }
+
+ phylink_set_port_modes(mask);
+ phylink_set(mask, Autoneg);
+
+ if (state->interface != PHY_INTERFACE_MODE_TRGMII) {
+ phylink_set(mask, 10baseT_Half);
+ phylink_set(mask, 10baseT_Full);
+ phylink_set(mask, 100baseT_Half);
+ phylink_set(mask, 100baseT_Full);
+ phylink_set(mask, 1000baseT_Half);
+ }
+
+ phylink_set(mask, 1000baseT_Full);
+
+ phylink_set(mask, Pause);
+ phylink_set(mask, Asym_Pause);
+
+ linkmode_and(supported, supported, mask);
+ linkmode_and(state->advertising, state->advertising, mask);
+ return;
+
+unsupported:
+ linkmode_zero(supported);
+}
+
+static int
+mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
+ struct phylink_link_state *state)
+{
+ struct mt7530_priv *priv = ds->priv;
+ u32 pmsr;
+
+ if (port < 0 || port >= MT7530_NUM_PORTS)
+ return -EINVAL;
+
+ pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
+
+ state->link = (pmsr & PMSR_LINK);
+ state->an_complete = state->link;
+ state->duplex = !!(pmsr & PMSR_DPX);
+
+ switch (pmsr & PMSR_SPEED_MASK) {
+ case PMSR_SPEED_10:
+ state->speed = SPEED_10;
+ break;
+ case PMSR_SPEED_100:
+ state->speed = SPEED_100;
+ break;
+ case PMSR_SPEED_1000:
+ state->speed = SPEED_1000;
+ break;
+ default:
+ state->speed = SPEED_UNKNOWN;
+ break;
+ }
+
+ state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
+ if (pmsr & PMSR_RX_FC)
+ state->pause |= MLO_PAUSE_RX;
+ if (pmsr & PMSR_TX_FC)
+ state->pause |= MLO_PAUSE_TX;
+
+ return 1;
+}
+
static const struct dsa_switch_ops mt7530_switch_ops = {
.get_tag_protocol = mtk_get_tag_protocol,
.setup = mt7530_setup,
@@ -1331,7 +1450,6 @@ static const struct dsa_switch_ops mt7530_switch_ops = {
.phy_write = mt7530_phy_write,
.get_ethtool_stats = mt7530_get_ethtool_stats,
.get_sset_count = mt7530_get_sset_count,
- .adjust_link = mt7530_adjust_link,
.port_enable = mt7530_port_enable,
.port_disable = mt7530_port_disable,
.port_stp_state_set = mt7530_stp_state_set,
@@ -1344,6 +1462,11 @@ static const struct dsa_switch_ops mt7530_switch_ops = {
.port_vlan_prepare = mt7530_port_vlan_prepare,
.port_vlan_add = mt7530_port_vlan_add,
.port_vlan_del = mt7530_port_vlan_del,
+ .phylink_validate = mt7530_phylink_validate,
+ .phylink_mac_link_state = mt7530_phylink_mac_link_state,
+ .phylink_mac_config = mt7530_phylink_mac_config,
+ .phylink_mac_link_down = mt7530_phylink_mac_link_down,
+ .phylink_mac_link_up = mt7530_phylink_mac_link_up,
};
static const struct of_device_id mt7530_of_match[] = {
diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h
index bfac90f48102..107dd04acede 100644
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -198,26 +198,20 @@ enum mt7530_vlan_port_attr {
#define PMCR_FORCE_SPEED_100 BIT(2)
#define PMCR_FORCE_FDX BIT(1)
#define PMCR_FORCE_LNK BIT(0)
-#define PMCR_COMMON_LINK (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
- PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
- PMCR_TX_EN | PMCR_RX_EN | \
- PMCR_TX_FC_EN | PMCR_RX_FC_EN)
-#define PMCR_CPUP_LINK (PMCR_COMMON_LINK | PMCR_FORCE_MODE | \
- PMCR_FORCE_SPEED_1000 | \
- PMCR_FORCE_FDX | \
- PMCR_FORCE_LNK)
-#define PMCR_USERP_LINK PMCR_COMMON_LINK
-#define PMCR_FIXED_LINK (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
- PMCR_FORCE_MODE | PMCR_TX_EN | \
- PMCR_RX_EN | PMCR_BACKPR_EN | \
- PMCR_BACKOFF_EN | \
- PMCR_FORCE_SPEED_1000 | \
- PMCR_FORCE_FDX | \
- PMCR_FORCE_LNK)
-#define PMCR_FIXED_LINK_FC (PMCR_FIXED_LINK | \
- PMCR_TX_FC_EN | PMCR_RX_FC_EN)
+#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
+ PMCR_FORCE_SPEED_1000)
#define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
+#define PMSR_EEE1G BIT(7)
+#define PMSR_EEE100M BIT(6)
+#define PMSR_RX_FC BIT(5)
+#define PMSR_TX_FC BIT(4)
+#define PMSR_SPEED_1000 BIT(3)
+#define PMSR_SPEED_100 BIT(2)
+#define PMSR_SPEED_10 0x00
+#define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000)
+#define PMSR_DPX BIT(1)
+#define PMSR_LINK BIT(0)
/* Register for MIB */
#define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
@@ -423,6 +417,7 @@ struct mt7530_port {
* @ports: Holding the state among ports
* @reg_mutex: The lock for protecting among process accessing
* registers
+ * @p6_interface Holding the current port 6 interface
*/
struct mt7530_priv {
struct device *dev;
@@ -435,6 +430,7 @@ struct mt7530_priv {
struct gpio_desc *reset;
unsigned int id;
bool mcm;
+ phy_interface_t p6_interface;
struct mt7530_port ports[MT7530_NUM_PORTS];
/* protect among processes for registers access*/
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH net-next 1/3] net: dsa: mt7530: Convert to PHYLINK API
2019-07-24 19:25 ` [PATCH net-next 1/3] net: dsa: mt7530: Convert to PHYLINK API René van Dorst
@ 2019-07-27 18:48 ` Russell King - ARM Linux admin
2019-08-01 17:21 ` René van Dorst
0 siblings, 1 reply; 13+ messages in thread
From: Russell King - ARM Linux admin @ 2019-07-27 18:48 UTC (permalink / raw)
To: René van Dorst
Cc: netdev, frank-w, sean.wang, f.fainelli, davem, matthias.bgg,
andrew, vivien.didelot, john, linux-mediatek, linux-mips,
robh+dt, devicetree
Hi,
Just a couple of minor points.
On Wed, Jul 24, 2019 at 09:25:47PM +0200, René van Dorst wrote:
> +static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port,
> + unsigned int mode,
> + const struct phylink_link_state *state)
> +{
> + struct mt7530_priv *priv = ds->priv;
> + u32 mcr_cur, mcr_new;
> +
> + switch (port) {
> + case 0: /* Internal phy */
> + case 1:
> + case 2:
> + case 3:
> + case 4:
> + if (state->interface != PHY_INTERFACE_MODE_GMII)
> + return;
> + break;
> + /* case 5: Port 5 is not supported! */
> + case 6: /* 1st cpu port */
> + if (state->interface != PHY_INTERFACE_MODE_RGMII &&
> + state->interface != PHY_INTERFACE_MODE_TRGMII)
> + return;
> +
> + if (priv->p6_interface == state->interface)
> + break;
> + /* Setup TX circuit incluing relevant PAD and driving */
> + mt7530_pad_clk_setup(ds, state->interface);
> +
> + if (priv->id == ID_MT7530) {
> + /* Setup RX circuit, relevant PAD and driving on the
> + * host which must be placed after the setup on the
> + * device side is all finished.
> + */
> + mt7623_pad_clk_setup(ds);
> + }
> + priv->p6_interface = state->interface;
> + break;
> + default:
> + dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
> + return;
> + }
if (phylink_autoneg_inband(mode)) {
dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
__func__);
return;
}
or similar, since you don't support inband AN in this code path.
> +
> + mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
> + mcr_new = mcr_cur;
> + mcr_new &= ~(PMCR_FORCE_SPEED_1000 | PMCR_FORCE_SPEED_100 |
> + PMCR_FORCE_FDX | PMCR_TX_FC_EN | PMCR_RX_FC_EN);
> + mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
> + PMCR_BACKPR_EN | PMCR_FORCE_MODE | PMCR_FORCE_LNK;
> +
> + switch (state->speed) {
> + case SPEED_1000:
> + mcr_new |= PMCR_FORCE_SPEED_1000;
> + break;
> + case SPEED_100:
> + mcr_new |= PMCR_FORCE_SPEED_100;
> + break;
> + }
> + if (state->duplex == DUPLEX_FULL) {
> + mcr_new |= PMCR_FORCE_FDX;
> + if (state->pause & MLO_PAUSE_TX)
> + mcr_new |= PMCR_TX_FC_EN;
> + if (state->pause & MLO_PAUSE_RX)
> + mcr_new |= PMCR_RX_FC_EN;
> + }
> +
> + if (mcr_new != mcr_cur)
> + mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
> +}
> +
> +static void mt7530_phylink_mac_link_down(struct dsa_switch *ds, int port,
> + unsigned int mode,
> + phy_interface_t interface)
> +{
> + struct mt7530_priv *priv = ds->priv;
> +
> + mt7530_port_set_status(priv, port, 0);
> +}
> +
> +static void mt7530_phylink_mac_link_up(struct dsa_switch *ds, int port,
> + unsigned int mode,
> + phy_interface_t interface,
> + struct phy_device *phydev)
> +{
> + struct mt7530_priv *priv = ds->priv;
> +
> + mt7530_port_set_status(priv, port, 1);
> +}
> +
> +static void mt7530_phylink_validate(struct dsa_switch *ds, int port,
> + unsigned long *supported,
> + struct phylink_link_state *state)
> +{
> + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
> +
> + switch (port) {
> + case 0: /* Internal phy */
> + case 1:
> + case 2:
> + case 3:
> + case 4:
> + if (state->interface != PHY_INTERFACE_MODE_NA &&
> + state->interface != PHY_INTERFACE_MODE_GMII)
> + goto unsupported;
> + break;
> + /* case 5: Port 5 not supported! */
> + case 6: /* 1st cpu port */
> + if (state->interface != PHY_INTERFACE_MODE_NA &&
> + state->interface != PHY_INTERFACE_MODE_RGMII &&
> + state->interface != PHY_INTERFACE_MODE_TRGMII)
> + goto unsupported;
> + break;
> + default:
> + linkmode_zero(supported);
> + dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
You could reorder this as:
default:
dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
unsupported:
linkmode_zero(supported);
and save having the "unsupported" at the end of the function. Not sure
what DaveM would think of it though.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
According to speedtest.net: 11.9Mbps down 500kbps up
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH net-next 1/3] net: dsa: mt7530: Convert to PHYLINK API
2019-07-27 18:48 ` Russell King - ARM Linux admin
@ 2019-08-01 17:21 ` René van Dorst
2019-08-01 17:22 ` David Miller
0 siblings, 1 reply; 13+ messages in thread
From: René van Dorst @ 2019-08-01 17:21 UTC (permalink / raw)
To: davem
Cc: netdev, frank-w, sean.wang, f.fainelli, matthias.bgg, andrew,
vivien.didelot, john, linux-mediatek, linux-mips, robh+dt,
devicetree, Russell King - ARM Linux admin
Quoting Russell King - ARM Linux admin <linux@armlinux.org.uk>:
> Hi,
>
> Just a couple of minor points.
>
> On Wed, Jul 24, 2019 at 09:25:47PM +0200, René van Dorst wrote:
<snip>
>> +
>> +static void mt7530_phylink_validate(struct dsa_switch *ds, int port,
>> + unsigned long *supported,
>> + struct phylink_link_state *state)
>> +{
>> + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
>> +
>> + switch (port) {
>> + case 0: /* Internal phy */
>> + case 1:
>> + case 2:
>> + case 3:
>> + case 4:
>> + if (state->interface != PHY_INTERFACE_MODE_NA &&
>> + state->interface != PHY_INTERFACE_MODE_GMII)
>> + goto unsupported;
>> + break;
>> + /* case 5: Port 5 not supported! */
>> + case 6: /* 1st cpu port */
>> + if (state->interface != PHY_INTERFACE_MODE_NA &&
>> + state->interface != PHY_INTERFACE_MODE_RGMII &&
>> + state->interface != PHY_INTERFACE_MODE_TRGMII)
>> + goto unsupported;
>> + break;
>> + default:
>> + linkmode_zero(supported);
>> + dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
>
> You could reorder this as:
>
> default:
> dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
> unsupported:
> linkmode_zero(supported);
>
Hi David,
> and save having the "unsupported" at the end of the function. Not sure
> what DaveM would think of it though.
Can you give your option about this?
So I know what to do with it and make a new series.
Greats,
René
>
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
> According to speedtest.net: 11.9Mbps down 500kbps up
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH net-next 1/3] net: dsa: mt7530: Convert to PHYLINK API
2019-08-01 17:21 ` René van Dorst
@ 2019-08-01 17:22 ` David Miller
0 siblings, 0 replies; 13+ messages in thread
From: David Miller @ 2019-08-01 17:22 UTC (permalink / raw)
To: opensource
Cc: netdev, frank-w, sean.wang, f.fainelli, matthias.bgg, andrew,
vivien.didelot, john, linux-mediatek, linux-mips, robh+dt,
devicetree, linux
From: René van Dorst <opensource@vdorst.com>
Date: Thu, 01 Aug 2019 17:21:04 +0000
> Quoting Russell King - ARM Linux admin <linux@armlinux.org.uk>:
>
>> Hi,
>>
>> Just a couple of minor points.
>>
>> On Wed, Jul 24, 2019 at 09:25:47PM +0200, René van Dorst wrote:
>
> <snip>
>
>>> +
>>> +static void mt7530_phylink_validate(struct dsa_switch *ds, int port,
>>> + unsigned long *supported,
>>> + struct phylink_link_state *state)
>>> +{
>>> + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
>>> +
>>> + switch (port) {
>>> + case 0: /* Internal phy */
>>> + case 1:
>>> + case 2:
>>> + case 3:
>>> + case 4:
>>> + if (state->interface != PHY_INTERFACE_MODE_NA &&
>>> + state->interface != PHY_INTERFACE_MODE_GMII)
>>> + goto unsupported;
>>> + break;
>>> + /* case 5: Port 5 not supported! */
>>> + case 6: /* 1st cpu port */
>>> + if (state->interface != PHY_INTERFACE_MODE_NA &&
>>> + state->interface != PHY_INTERFACE_MODE_RGMII &&
>>> + state->interface != PHY_INTERFACE_MODE_TRGMII)
>>> + goto unsupported;
>>> + break;
>>> + default:
>>> + linkmode_zero(supported);
>>> + dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
>>
>> You could reorder this as:
>>
>> default:
>> dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
>> unsupported:
>> linkmode_zero(supported);
>>
>
> Hi David,
>
>> and save having the "unsupported" at the end of the function. Not
>> sure
>> what DaveM would think of it though.
>
> Can you give your option about this?
> So I know what to do with it and make a new series.
Russell's suggestion is fine.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH net-next 2/3] dt-bindings: net: dsa: mt7530: Add support for port 5
2019-07-24 19:25 [PATCH net-next 0/3] net: dsa: MT7530: Convert to PHYLINK and add support for port 5 René van Dorst
2019-07-24 19:25 ` [PATCH net-next 1/3] net: dsa: mt7530: Convert to PHYLINK API René van Dorst
@ 2019-07-24 19:25 ` René van Dorst
2019-07-24 19:25 ` [PATCH net-next 3/3] " René van Dorst
2 siblings, 0 replies; 13+ messages in thread
From: René van Dorst @ 2019-07-24 19:25 UTC (permalink / raw)
To: netdev
Cc: frank-w, sean.wang, f.fainelli, linux, davem, matthias.bgg,
andrew, vivien.didelot, john, linux-mediatek, linux-mips,
robh+dt, devicetree, René van Dorst
MT7530 port 5 has many modes/configurations.
Update the documentation how to use port 5.
Signed-off-by: René van Dorst <opensource@vdorst.com>
rfc->v1:
* No change
---
.../devicetree/bindings/net/dsa/mt7530.txt | 215 ++++++++++++++++++
1 file changed, 215 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt b/Documentation/devicetree/bindings/net/dsa/mt7530.txt
index 47aa205ee0bd..f3486780f2c2 100644
--- a/Documentation/devicetree/bindings/net/dsa/mt7530.txt
+++ b/Documentation/devicetree/bindings/net/dsa/mt7530.txt
@@ -35,6 +35,39 @@ Required properties for the child nodes within ports container:
- phy-mode: String, must be either "trgmii" or "rgmii" for port labeled
"cpu".
+Port 5 of the switch is muxed between:
+1. GMAC5: GMAC5 can interface with another external MAC or PHY.
+2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
+ of the SOC. Used in many setups where port 0/4 becomes the WAN port.
+
+Port 5 modes/configurations:
+1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
+ GMAC of the SOC.
+ In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
+ GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC!
+2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
+ It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
+ and RGMII delay.
+3. Port 5 is muxed to GMAC5 and can interface to an external phy.
+ Port 5 becomes an extra switch port.
+ Only works on platform where external phy TX<->RX lines are swapped.
+ Like in the Ubiquiti ER-X-SFP.
+4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
+ Currently a 2nd CPU port is not supported by DSA code.
+
+Depending on how the external PHY is wired:
+1. normal: The PHY can only connect to 2nd GMAC but not to the switch
+2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
+ a ethernet port. But can't interface to the 2nd GMAC.
+
+Based on the DT the port 5 mode is configured.
+
+Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
+When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
+phy-mode must be set, see also example 2 below!
+ * mt7621: phy-mode = "rgmii-txid";
+ * mt7623: phy-mode = "rgmii";
+
See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
required, optional properties and how the integrated switch subnodes must
be specified.
@@ -94,3 +127,185 @@ Example:
};
};
};
+
+Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
+
+ð {
+ status = "okay";
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "rgmii-txid";
+ phy-handle = <&phy4>;
+ };
+
+ mdio: mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Internal phy */
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+
+ mt7530: switch@1f {
+ compatible = "mediatek,mt7621";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1f>;
+ pinctrl-names = "default";
+ mediatek,mcm;
+
+ resets = <&rstctrl 2>;
+ reset-names = "mcm";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan0";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan3";
+ };
+
+/* Commented out. Port 4 is handled by 2nd GMAC.
+ port@4 {
+ reg = <4>;
+ label = "lan4";
+ };
+*/
+
+ cpu_port0: port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+ };
+};
+
+Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.
+
+ð {
+ status = "okay";
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ mdio: mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* External phy */
+ ephy5: ethernet-phy@7 {
+ reg = <7>;
+ };
+
+ mt7530: switch@1f {
+ compatible = "mediatek,mt7621";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1f>;
+ pinctrl-names = "default";
+ mediatek,mcm;
+
+ resets = <&rstctrl 2>;
+ reset-names = "mcm";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan0";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan3";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan4";
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "lan5";
+ phy-mode = "rgmii";
+ phy-handle = <&ephy5>;
+ };
+
+ cpu_port0: port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+ };
+};
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH net-next 3/3] net: dsa: mt7530: Add support for port 5
2019-07-24 19:25 [PATCH net-next 0/3] net: dsa: MT7530: Convert to PHYLINK and add support for port 5 René van Dorst
2019-07-24 19:25 ` [PATCH net-next 1/3] net: dsa: mt7530: Convert to PHYLINK API René van Dorst
2019-07-24 19:25 ` [PATCH net-next 2/3] dt-bindings: net: dsa: mt7530: Add support for port 5 René van Dorst
@ 2019-07-24 19:25 ` René van Dorst
2019-07-26 21:04 ` David Miller
` (2 more replies)
2 siblings, 3 replies; 13+ messages in thread
From: René van Dorst @ 2019-07-24 19:25 UTC (permalink / raw)
To: netdev
Cc: frank-w, sean.wang, f.fainelli, linux, davem, matthias.bgg,
andrew, vivien.didelot, john, linux-mediatek, linux-mips,
robh+dt, devicetree, René van Dorst
Adding support for port 5.
Port 5 can muxed/interface to:
- internal 5th GMAC of the switch; can be used as 2nd CPU port or as
extra port with an external phy for a 6th ethernet port.
- internal PHY of port 0 or 4; Used in most applications so that port 0
or 4 is the WAN port and interfaces with the 2nd GMAC of the SOC.
Signed-off-by: René van Dorst <opensource@vdorst.com>
rfc->v1:
* Removed unnecessary info print suggested by Andrew Lunn
* Added support for MII mode for port 5
---
drivers/net/dsa/mt7530.c | 145 ++++++++++++++++++++++++++++++++++++---
drivers/net/dsa/mt7530.h | 28 ++++++++
2 files changed, 165 insertions(+), 8 deletions(-)
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index 73a2204bf81a..785ce825aeb1 100644
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -633,6 +633,75 @@ mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
return ARRAY_SIZE(mt7530_mib);
}
+static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
+{
+ struct mt7530_priv *priv = ds->priv;
+ u8 tx_delay = 0;
+ int val;
+
+ mutex_lock(&priv->reg_mutex);
+
+ val = mt7530_read(priv, MT7530_MHWTRAP);
+
+ val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
+ val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
+
+ switch (priv->p5_intf_sel) {
+ case P5_INTF_SEL_PHY_P0:
+ /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
+ val |= MHWTRAP_PHY0_SEL;
+ /* fall through */
+ case P5_INTF_SEL_PHY_P4:
+ /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
+ val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
+
+ /* Setup the MAC by default for the cpu port */
+ mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
+ break;
+ case P5_INTF_SEL_GMAC5:
+ /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
+ val &= ~MHWTRAP_P5_DIS;
+ break;
+ case P5_DISABLED:
+ interface = PHY_INTERFACE_MODE_NA;
+ break;
+ default:
+ dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
+ priv->p5_intf_sel);
+ goto unlock_exit;
+ }
+
+ /* Setup RGMII settings */
+ if (phy_interface_mode_is_rgmii(interface)) {
+ val |= MHWTRAP_P5_RGMII_MODE;
+
+ /* P5 RGMII RX Clock Control: delay setting for 1000M */
+ mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
+
+ /* Don't set delay in DSA mode */
+ if (!dsa_is_dsa_port(priv->ds, 5) &&
+ (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
+ interface == PHY_INTERFACE_MODE_RGMII_ID))
+ tx_delay = 4; /* n * 0.5 ns */
+
+ /* P5 RGMII TX Clock Control: delay x */
+ mt7530_write(priv, MT7530_P5RGMIITXCR,
+ CSR_RGMII_TXC_CFG(0x10 + tx_delay));
+
+ /* reduce P5 RGMII Tx driving, 8mA */
+ mt7530_write(priv, MT7530_IO_DRV_CR,
+ P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
+ }
+
+ mt7530_write(priv, MT7530_MHWTRAP, val);
+
+ dev_info(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
+ val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
+
+unlock_exit:
+ mutex_unlock(&priv->reg_mutex);
+}
+
static int
mt7530_cpu_port_enable(struct mt7530_priv *priv,
int port)
@@ -1167,6 +1236,10 @@ mt7530_setup(struct dsa_switch *ds)
u32 id, val;
struct device_node *dn;
struct mt7530_dummy_poll p;
+ phy_interface_t interface;
+ struct device_node *mac_np;
+ struct device_node *phy_node;
+ const __be32 *_id;
/* The parent node of master netdev which holds the common system
* controller also is the container for two GMACs nodes representing
@@ -1254,6 +1327,40 @@ mt7530_setup(struct dsa_switch *ds)
mt7530_port_disable(ds, i);
}
+ /* Setup port 5 */
+ priv->p5_intf_sel = P5_DISABLED;
+ interface = PHY_INTERFACE_MODE_NA;
+
+ if (!dsa_is_unused_port(ds, 5)) {
+ priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+ interface = of_get_phy_mode(ds->ports[5].dn);
+ } else {
+ /* Scan the ethernet nodes. Look for GMAC1, Lookup used phy */
+ for_each_child_of_node(dn, mac_np) {
+ if (!of_device_is_compatible(mac_np,
+ "mediatek,eth-mac"))
+ continue;
+ _id = of_get_property(mac_np, "reg", NULL);
+ if (be32_to_cpup(_id) != 1)
+ continue;
+
+ interface = of_get_phy_mode(mac_np);
+ phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
+
+ if (phy_node->parent == priv->dev->of_node->parent) {
+ _id = of_get_property(phy_node, "reg", NULL);
+ id = be32_to_cpup(_id);
+ if (id == 0)
+ priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
+ if (id == 4)
+ priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
+ }
+ break;
+ }
+ }
+
+ mt7530_setup_port5(ds, interface);
+
/* Flush the FDB table */
ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
if (ret < 0)
@@ -1267,7 +1374,7 @@ static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port,
const struct phylink_link_state *state)
{
struct mt7530_priv *priv = ds->priv;
- u32 mcr_cur, mcr_new;
+ u32 mcr_cur, mcr_new = 0;
switch (port) {
case 0: /* Internal phy */
@@ -1278,7 +1385,19 @@ static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port,
if (state->interface != PHY_INTERFACE_MODE_GMII)
return;
break;
- /* case 5: Port 5 is not supported! */
+ case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
+ if (!phy_interface_mode_is_rgmii(state->interface) &&
+ state->interface != PHY_INTERFACE_MODE_MII &&
+ state->interface != PHY_INTERFACE_MODE_GMII)
+ return;
+ if (priv->p5_intf_sel != P5_INTF_SEL_GMAC5) {
+ priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+ mt7530_setup_port5(ds, state->interface);
+ }
+ /* We are connected to external phy */
+ if (dsa_is_user_port(ds, 5))
+ mcr_new |= PMCR_EXT_PHY;
+ break;
case 6: /* 1st cpu port */
if (state->interface != PHY_INTERFACE_MODE_RGMII &&
state->interface != PHY_INTERFACE_MODE_TRGMII)
@@ -1304,7 +1423,7 @@ static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port,
}
mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
- mcr_new = mcr_cur;
+ mcr_new |= mcr_cur;
mcr_new &= ~(PMCR_FORCE_SPEED_1000 | PMCR_FORCE_SPEED_100 |
PMCR_FORCE_FDX | PMCR_TX_FC_EN | PMCR_RX_FC_EN);
mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
@@ -1365,7 +1484,13 @@ static void mt7530_phylink_validate(struct dsa_switch *ds, int port,
state->interface != PHY_INTERFACE_MODE_GMII)
goto unsupported;
break;
- /* case 5: Port 5 not supported! */
+ case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
+ if (state->interface != PHY_INTERFACE_MODE_NA &&
+ !phy_interface_mode_is_rgmii(state->interface) &&
+ state->interface != PHY_INTERFACE_MODE_MII &&
+ state->interface != PHY_INTERFACE_MODE_GMII)
+ goto unsupported;
+ break;
case 6: /* 1st cpu port */
if (state->interface != PHY_INTERFACE_MODE_NA &&
state->interface != PHY_INTERFACE_MODE_RGMII &&
@@ -1381,15 +1506,19 @@ static void mt7530_phylink_validate(struct dsa_switch *ds, int port,
phylink_set_port_modes(mask);
phylink_set(mask, Autoneg);
- if (state->interface != PHY_INTERFACE_MODE_TRGMII) {
+ if (state->interface == PHY_INTERFACE_MODE_TRGMII) {
+ phylink_set(mask, 1000baseT_Full);
+ } else {
phylink_set(mask, 10baseT_Half);
phylink_set(mask, 10baseT_Full);
phylink_set(mask, 100baseT_Half);
phylink_set(mask, 100baseT_Full);
- phylink_set(mask, 1000baseT_Half);
- }
- phylink_set(mask, 1000baseT_Full);
+ if (state->interface != PHY_INTERFACE_MODE_MII) {
+ phylink_set(mask, 1000baseT_Half);
+ phylink_set(mask, 1000baseT_Full);
+ }
+ }
phylink_set(mask, Pause);
phylink_set(mask, Asym_Pause);
diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h
index 107dd04acede..0f7276a2270a 100644
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -186,6 +186,7 @@ enum mt7530_vlan_port_attr {
/* Register for port MAC control register */
#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
+#define PMCR_EXT_PHY BIT(17)
#define PMCR_MAC_MODE BIT(16)
#define PMCR_FORCE_MODE BIT(15)
#define PMCR_TX_EN BIT(14)
@@ -245,6 +246,7 @@ enum mt7530_vlan_port_attr {
/* Register for hw trap modification */
#define MT7530_MHWTRAP 0x7804
+#define MHWTRAP_PHY0_SEL BIT(20)
#define MHWTRAP_MANUAL BIT(16)
#define MHWTRAP_P5_MAC_SEL BIT(13)
#define MHWTRAP_P6_DIS BIT(8)
@@ -402,6 +404,30 @@ struct mt7530_port {
u16 pvid;
};
+/* Port 5 interface select definitions */
+enum p5_interface_select {
+ P5_DISABLED = 0,
+ P5_INTF_SEL_PHY_P0,
+ P5_INTF_SEL_PHY_P4,
+ P5_INTF_SEL_GMAC5,
+};
+
+static const char *p5_intf_modes(unsigned int p5_interface)
+{
+ switch (p5_interface) {
+ case P5_DISABLED:
+ return "DISABLED";
+ case P5_INTF_SEL_PHY_P0:
+ return "PHY P0";
+ case P5_INTF_SEL_PHY_P4:
+ return "PHY P4";
+ case P5_INTF_SEL_GMAC5:
+ return "GMAC5";
+ default:
+ return "unknown";
+ }
+}
+
/* struct mt7530_priv - This is the main data structure for holding the state
* of the driver
* @dev: The device pointer
@@ -418,6 +444,7 @@ struct mt7530_port {
* @reg_mutex: The lock for protecting among process accessing
* registers
* @p6_interface Holding the current port 6 interface
+ * @p5_intf_sel: Holding the current port 5 interface select
*/
struct mt7530_priv {
struct device *dev;
@@ -431,6 +458,7 @@ struct mt7530_priv {
unsigned int id;
bool mcm;
phy_interface_t p6_interface;
+ unsigned int p5_intf_sel;
struct mt7530_port ports[MT7530_NUM_PORTS];
/* protect among processes for registers access*/
--
2.20.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH net-next 3/3] net: dsa: mt7530: Add support for port 5
2019-07-24 19:25 ` [PATCH net-next 3/3] " René van Dorst
@ 2019-07-26 21:04 ` David Miller
2019-07-27 18:43 ` René van Dorst
2019-07-27 8:42 ` Florian Fainelli
2019-07-27 18:53 ` Russell King - ARM Linux admin
2 siblings, 1 reply; 13+ messages in thread
From: David Miller @ 2019-07-26 21:04 UTC (permalink / raw)
To: opensource
Cc: netdev, frank-w, sean.wang, f.fainelli, linux, matthias.bgg,
andrew, vivien.didelot, john, linux-mediatek, linux-mips,
robh+dt, devicetree
From: René van Dorst <opensource@vdorst.com>
Date: Wed, 24 Jul 2019 21:25:49 +0200
> @@ -1167,6 +1236,10 @@ mt7530_setup(struct dsa_switch *ds)
> u32 id, val;
> struct device_node *dn;
> struct mt7530_dummy_poll p;
> + phy_interface_t interface;
> + struct device_node *mac_np;
> + struct device_node *phy_node;
> + const __be32 *_id;
Reverse christmas tree here please.
Thank you.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH net-next 3/3] net: dsa: mt7530: Add support for port 5
2019-07-26 21:04 ` David Miller
@ 2019-07-27 18:43 ` René van Dorst
0 siblings, 0 replies; 13+ messages in thread
From: René van Dorst @ 2019-07-27 18:43 UTC (permalink / raw)
To: David Miller
Cc: netdev, frank-w, sean.wang, f.fainelli, linux, matthias.bgg,
andrew, vivien.didelot, john, linux-mediatek, linux-mips,
robh+dt, devicetree
Quoting David Miller <davem@davemloft.net>:
> From: René van Dorst <opensource@vdorst.com>
> Date: Wed, 24 Jul 2019 21:25:49 +0200
>
>> @@ -1167,6 +1236,10 @@ mt7530_setup(struct dsa_switch *ds)
>> u32 id, val;
>> struct device_node *dn;
>> struct mt7530_dummy_poll p;
>> + phy_interface_t interface;
>> + struct device_node *mac_np;
>> + struct device_node *phy_node;
>> + const __be32 *_id;
>
Hi David,
> Reverse christmas tree here please.
>
> Thank you.
OK, I shall change that.
I spin a new version.
Greats,
René
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH net-next 3/3] net: dsa: mt7530: Add support for port 5
2019-07-24 19:25 ` [PATCH net-next 3/3] " René van Dorst
2019-07-26 21:04 ` David Miller
@ 2019-07-27 8:42 ` Florian Fainelli
2019-07-27 18:38 ` René van Dorst
2019-07-27 18:53 ` Russell King - ARM Linux admin
2 siblings, 1 reply; 13+ messages in thread
From: Florian Fainelli @ 2019-07-27 8:42 UTC (permalink / raw)
To: René van Dorst, netdev
Cc: frank-w, sean.wang, linux, davem, matthias.bgg, andrew,
vivien.didelot, john, linux-mediatek, linux-mips, robh+dt,
devicetree
On 7/24/2019 9:25 PM, René van Dorst wrote:
> Adding support for port 5.
>
> Port 5 can muxed/interface to:
> - internal 5th GMAC of the switch; can be used as 2nd CPU port or as
> extra port with an external phy for a 6th ethernet port.
> - internal PHY of port 0 or 4; Used in most applications so that port 0
> or 4 is the WAN port and interfaces with the 2nd GMAC of the SOC.
>
> Signed-off-by: René van Dorst <opensource@vdorst.com>
[snip]
> + /* Setup port 5 */
> + priv->p5_intf_sel = P5_DISABLED;
> + interface = PHY_INTERFACE_MODE_NA;
> +
> + if (!dsa_is_unused_port(ds, 5)) {
> + priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
> + interface = of_get_phy_mode(ds->ports[5].dn);
> + } else {
> + /* Scan the ethernet nodes. Look for GMAC1, Lookup used phy */
> + for_each_child_of_node(dn, mac_np) {
> + if (!of_device_is_compatible(mac_np,
> + "mediatek,eth-mac"))
> + continue;
> + _id = of_get_property(mac_np, "reg", NULL);
> + if (be32_to_cpup(_id) != 1)
> + continue;
> +
> + interface = of_get_phy_mode(mac_np);
> + phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
> +
> + if (phy_node->parent == priv->dev->of_node->parent) {
> + _id = of_get_property(phy_node, "reg", NULL);
> + id = be32_to_cpup(_id);
> + if (id == 0)
> + priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
> + if (id == 4)
> + priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
Can you use of_mdio_parse_addr() here?
--
Florian
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH net-next 3/3] net: dsa: mt7530: Add support for port 5
2019-07-27 8:42 ` Florian Fainelli
@ 2019-07-27 18:38 ` René van Dorst
0 siblings, 0 replies; 13+ messages in thread
From: René van Dorst @ 2019-07-27 18:38 UTC (permalink / raw)
To: Florian Fainelli
Cc: netdev, frank-w, sean.wang, linux, davem, matthias.bgg, andrew,
vivien.didelot, john, linux-mediatek, linux-mips, robh+dt,
devicetree
Quoting Florian Fainelli <f.fainelli@gmail.com>:
> On 7/24/2019 9:25 PM, René van Dorst wrote:
>> Adding support for port 5.
>>
>> Port 5 can muxed/interface to:
>> - internal 5th GMAC of the switch; can be used as 2nd CPU port or as
>> extra port with an external phy for a 6th ethernet port.
>> - internal PHY of port 0 or 4; Used in most applications so that port 0
>> or 4 is the WAN port and interfaces with the 2nd GMAC of the SOC.
>>
>> Signed-off-by: René van Dorst <opensource@vdorst.com>
>
> [snip]
>
>> + /* Setup port 5 */
>> + priv->p5_intf_sel = P5_DISABLED;
>> + interface = PHY_INTERFACE_MODE_NA;
>> +
>> + if (!dsa_is_unused_port(ds, 5)) {
>> + priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
>> + interface = of_get_phy_mode(ds->ports[5].dn);
>> + } else {
>> + /* Scan the ethernet nodes. Look for GMAC1, Lookup used phy */
>> + for_each_child_of_node(dn, mac_np) {
>> + if (!of_device_is_compatible(mac_np,
>> + "mediatek,eth-mac"))
>> + continue;
>> + _id = of_get_property(mac_np, "reg", NULL);
>> + if (be32_to_cpup(_id) != 1)
>> + continue;
>> +
>> + interface = of_get_phy_mode(mac_np);
>> + phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
>> +
>> + if (phy_node->parent == priv->dev->of_node->parent) {
>> + _id = of_get_property(phy_node, "reg", NULL);
>> + id = be32_to_cpup(_id);
>> + if (id == 0)
>> + priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
>> + if (id == 4)
>> + priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
>
Hi Florian,
> Can you use of_mdio_parse_addr() here?
Yes that function be used.
Thanks for mention this function.
I see that I can refactor this scan routine a bit more.
Also I missing a of_node_put(phy_node) at the end.
> --
> Florian
Greats,
René
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH net-next 3/3] net: dsa: mt7530: Add support for port 5
2019-07-24 19:25 ` [PATCH net-next 3/3] " René van Dorst
2019-07-26 21:04 ` David Miller
2019-07-27 8:42 ` Florian Fainelli
@ 2019-07-27 18:53 ` Russell King - ARM Linux admin
2019-07-27 21:26 ` René van Dorst
2 siblings, 1 reply; 13+ messages in thread
From: Russell King - ARM Linux admin @ 2019-07-27 18:53 UTC (permalink / raw)
To: René van Dorst
Cc: netdev, frank-w, sean.wang, f.fainelli, davem, matthias.bgg,
andrew, vivien.didelot, john, linux-mediatek, linux-mips,
robh+dt, devicetree
On Wed, Jul 24, 2019 at 09:25:49PM +0200, René van Dorst wrote:
> Adding support for port 5.
>
> Port 5 can muxed/interface to:
> - internal 5th GMAC of the switch; can be used as 2nd CPU port or as
> extra port with an external phy for a 6th ethernet port.
> - internal PHY of port 0 or 4; Used in most applications so that port 0
> or 4 is the WAN port and interfaces with the 2nd GMAC of the SOC.
...
> @@ -1381,15 +1506,19 @@ static void mt7530_phylink_validate(struct dsa_switch *ds, int port,
> phylink_set_port_modes(mask);
> phylink_set(mask, Autoneg);
>
> - if (state->interface != PHY_INTERFACE_MODE_TRGMII) {
> + if (state->interface == PHY_INTERFACE_MODE_TRGMII) {
> + phylink_set(mask, 1000baseT_Full);
> + } else {
> phylink_set(mask, 10baseT_Half);
> phylink_set(mask, 10baseT_Full);
> phylink_set(mask, 100baseT_Half);
> phylink_set(mask, 100baseT_Full);
> - phylink_set(mask, 1000baseT_Half);
> - }
>
> - phylink_set(mask, 1000baseT_Full);
> + if (state->interface != PHY_INTERFACE_MODE_MII) {
> + phylink_set(mask, 1000baseT_Half);
> + phylink_set(mask, 1000baseT_Full);
> + }
> + }
As port 5 could use an external PHY, and it supports gigabit speeds,
consider that the PHY may provide not only copper but also fiber
connectivity, so port 5 should probably also have 1000baseX modes
too, which would allow such a PHY to bridge the switch to fiber.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
According to speedtest.net: 11.9Mbps down 500kbps up
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH net-next 3/3] net: dsa: mt7530: Add support for port 5
2019-07-27 18:53 ` Russell King - ARM Linux admin
@ 2019-07-27 21:26 ` René van Dorst
0 siblings, 0 replies; 13+ messages in thread
From: René van Dorst @ 2019-07-27 21:26 UTC (permalink / raw)
To: Russell King - ARM Linux admin
Cc: netdev, frank-w, sean.wang, f.fainelli, davem, matthias.bgg,
andrew, vivien.didelot, john, linux-mediatek, linux-mips,
robh+dt, devicetree
Quoting Russell King - ARM Linux admin <linux@armlinux.org.uk>:
> On Wed, Jul 24, 2019 at 09:25:49PM +0200, René van Dorst wrote:
>> Adding support for port 5.
>>
>> Port 5 can muxed/interface to:
>> - internal 5th GMAC of the switch; can be used as 2nd CPU port or as
>> extra port with an external phy for a 6th ethernet port.
>> - internal PHY of port 0 or 4; Used in most applications so that port 0
>> or 4 is the WAN port and interfaces with the 2nd GMAC of the SOC.
>
> ...
>
>> @@ -1381,15 +1506,19 @@ static void mt7530_phylink_validate(struct
>> dsa_switch *ds, int port,
>> phylink_set_port_modes(mask);
>> phylink_set(mask, Autoneg);
>>
>> - if (state->interface != PHY_INTERFACE_MODE_TRGMII) {
>> + if (state->interface == PHY_INTERFACE_MODE_TRGMII) {
>> + phylink_set(mask, 1000baseT_Full);
>> + } else {
>> phylink_set(mask, 10baseT_Half);
>> phylink_set(mask, 10baseT_Full);
>> phylink_set(mask, 100baseT_Half);
>> phylink_set(mask, 100baseT_Full);
>> - phylink_set(mask, 1000baseT_Half);
>> - }
>>
>> - phylink_set(mask, 1000baseT_Full);
>> + if (state->interface != PHY_INTERFACE_MODE_MII) {
>> + phylink_set(mask, 1000baseT_Half);
>> + phylink_set(mask, 1000baseT_Full);
>> + }
>> + }
>
Hi Russell,
Thanks for your review and many useful comments and explanations.
> As port 5 could use an external PHY, and it supports gigabit speeds,
> consider that the PHY may provide not only copper but also fiber
> connectivity, so port 5 should probably also have 1000baseX modes
> too, which would allow such a PHY to bridge the switch to fiber.
I shall add the 1000baseX modes.
My device, Ubiquiti EdgeRouter X SFP, has this setup.
Port 5 is connected to a at8033 phy which acts as a RGMII-SerDes converter for
the SFP cage. According to the datasheet it only support 100BASE-FX and
1000BASE-X. With bootstrap resistors the PHY is put in RGMII-SerDes 1000BASE-X
mode.
The problem I had is that the current mainline driver doesn't support
this mode
so I had to hack it in myself [0][1]. I probably doing the wrong thing with my
phy driver. Driver works for me, it detects a link and sets-up a 1gbit link.
So I can test port 5. But the driver may report all the wrong values to
PHYLIB/PHYLINK. But now that I learned more about it I can revise the driver.
By reading your previous emails, my setup could official not support the
FiberStore SFP-GB-GE-T module, because it requests a SGMII interface.
But my PHY only supports 1000BaseX and my code currently doesn't error out.
dmesg output of this module:
[ 3.382637] sfp sfp_lan5: module FiberStore SFP-GB-GE-T
rev B sn <snip> dc 19-12-17
[ 3.402048] sfp sfp_lan5: unknown/unspecified connector, encoding
8b10b, nominal bitrate 1.3Gbps +0% -0%
[ 3.421268] sfp sfp_lan5: 1000BaseSX- 1000BaseLX- 1000BaseCX-
1000BaseT+ 100BaseLX- 100BaseFX- BaseBX10- BasePX-
[ 3.441867] sfp sfp_lan5: 10GBaseSR- 10GBaseLR- 10GBaseLRM- 10GBaseER-
[ 3.455208] sfp sfp_lan5: Copper length: 100m
[ 3.464225] sfp sfp_lan5: Options: txdisable
[ 3.473066] sfp sfp_lan5: Diagnostics:
[ 3.481034] sfp sfp_lan5: Unknown/unsupported extended compliance
code: 0x01
[ 3.495069] Atheros 8031 ethernet mdio-bus:07: SFP interface sgmii
What is the best way to do it in case of SGMII interface request?
Return that we don't support SGMII or report that we only support 1
mode and no
auto-negotiation?
Greats,
René
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
> According to speedtest.net: 11.9Mbps down 500kbps up
[0]:
https://github.com/vDorst/linux-1/commit/dad5d6ec65cfa99c204e9756b3fc234071709292
[1]:
https://github.com/vDorst/linux-1/commit/a3aa74e84796604ab8619cfaf1c299c115a8736f
^ permalink raw reply [flat|nested] 13+ messages in thread