[PATCH 1/3] MIPS: Disable pte_special() for MIPS32 with 4KiB pages & RiXi

[PATCH 1/3] MIPS: Disable pte_special() for MIPS32 with 4KiB pages & RiXi

[Paul Burton]

Commit 61cbfff4b1a7 ("MIPS: pte_special()/pte_mkspecial() support")
added a _PAGE_SPECIAL bit to the pgprot bits of our PTEs. Unfortunately
for MIPS32 configurations with RiXi support this pushed the number of
pgprot bits to 13 (ie. _PFN_SHIFT = 13). When using 4KB pages (ie.
PAGE_SHIFT = 12) this results in us shifting the most significant bit of
the physical address beyond the end of the PTE, leading any mapped
access to a physical address above 2GB to incorrectly access an address
2GB lower than intended.

For now, disable the pte_special() support for MIPS32 configurations
that use 4KB pages & support RiXi.

Fixes: 61cbfff4b1a7 ("MIPS: pte_special()/pte_mkspecial() support")
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Dmitry Korotin <dkorotin@wavecomp.com>
---

 arch/mips/Kconfig                    |  2 +-
 arch/mips/include/asm/pgtable-bits.h | 14 +++++++++++++-
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3f18aa018a0c..18163c138676 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -84,7 +84,7 @@ config MIPS
 	select RTC_LIB
 	select SYSCTL_EXCEPTION_TRACE
 	select VIRT_TO_BUS
-	select ARCH_HAS_PTE_SPECIAL
+	select ARCH_HAS_PTE_SPECIAL if !(32BIT && PAGE_SIZE_4KB && CPU_HAS_RIXI)
 
 menu "Machine selection"
 
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 409ae01ed7be..4da79b85c179 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -52,7 +52,9 @@ enum pgtable_bits {
 	_PAGE_WRITE_SHIFT,
 	_PAGE_ACCESSED_SHIFT,
 	_PAGE_MODIFIED_SHIFT,
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
 	_PAGE_SPECIAL_SHIFT,
+#endif
 };
 
 /*
@@ -79,7 +81,9 @@ enum pgtable_bits {
 	_PAGE_WRITE_SHIFT,
 	_PAGE_ACCESSED_SHIFT,
 	_PAGE_MODIFIED_SHIFT,
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
 	_PAGE_SPECIAL_SHIFT,
+#endif
 };
 
 #elif defined(CONFIG_CPU_R3K_TLB)
@@ -92,7 +96,9 @@ enum pgtable_bits {
 	_PAGE_WRITE_SHIFT,
 	_PAGE_ACCESSED_SHIFT,
 	_PAGE_MODIFIED_SHIFT,
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
 	_PAGE_SPECIAL_SHIFT,
+#endif
 
 	/* Used by TLB hardware (placed in EntryLo) */
 	_PAGE_GLOBAL_SHIFT = 8,
@@ -116,7 +122,9 @@ enum pgtable_bits {
 #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 	_PAGE_HUGE_SHIFT,
 #endif
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
 	_PAGE_SPECIAL_SHIFT,
+#endif
 
 	/* Used by TLB hardware (placed in EntryLo*) */
 #if defined(CONFIG_CPU_HAS_RIXI)
@@ -139,7 +147,11 @@ enum pgtable_bits {
 #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 # define _PAGE_HUGE		(1 << _PAGE_HUGE_SHIFT)
 #endif
-#define _PAGE_SPECIAL		(1 << _PAGE_SPECIAL_SHIFT)
+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
+# define _PAGE_SPECIAL		(1 << _PAGE_SPECIAL_SHIFT)
+#else
+# define _PAGE_SPECIAL		0
+#endif
 
 /* Used by TLB hardware (placed in EntryLo*) */
 #if defined(CONFIG_XPA)
-- 
2.23.0

[PATCH 2/3] MIPS: Disable hugepages for MIPS32 with 4KB pages

[Paul Burton]

Commit 35476311e529 ("MIPS: Add partial 32-bit huge page support") added
support for huge pages in MIPS32 kernels, which requires the addition of
the _PAGE_HUGE pgprot flag to PTEs. Unfortunately for configurations
that support RiXI this pushed the number of pgprot bits to 13 (ie.
_PFN_SHIFT = 13). When using 4KB pages (ie. PAGE_SHIFT = 12) this
results in us shifting the most significant bit of the physical address
beyond the end of the PTE, leading any mapped access to a physical
address above 2GB to incorrectly access an address 2GB lower than
intended.

Separately, commit 61cbfff4b1a7 ("MIPS: pte_special()/pte_mkspecial()
support") added support for pte_special() which involved another new
pgprot bit. This leads the lack of an available pgprot bit for
_PAGE_HUGE in MIPS32 4KiB page configurations to be extended to non-RiXi
configurations too.

Disable huge page support for the affected configurations to prevent
unexpected misbehaviour.

Fixes: 35476311e529 ("MIPS: Add partial 32-bit huge page support")
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Silsby <dansilsby@gmail.com>
Cc: Dmitry Korotin <dkorotin@wavecomp.com>
Cc: Paul Cercueil <paul@crapouillou.net>
---

 arch/mips/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 18163c138676..fb75ed5443b8 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1227,7 +1227,7 @@ config SYS_SUPPORTS_LITTLE_ENDIAN
 
 config SYS_SUPPORTS_HUGETLBFS
 	bool
-	depends on CPU_SUPPORTS_HUGEPAGES
+	depends on CPU_SUPPORTS_HUGEPAGES && !(32BIT && PAGE_SIZE_4KB)
 	default y
 
 config MIPS_HUGE_TLB_SUPPORT
-- 
2.23.0

[PATCH 3/3] MIPS: Detect bad _PFN_SHIFT values

[Paul Burton]

2 recent commits have fixed issues where _PFN_SHIFT grew too large due
to the introduction of too many pgprot bits in our PTEs for some MIPS32
kernel configurations. Tracking down such issues can be tricky, so add a
BUILD_BUG_ON() to help.

Signed-off-by: Paul Burton <paul.burton@mips.com>
---

 arch/mips/mm/init.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 6fea3b54c961..090fa653dfa9 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -446,6 +446,12 @@ static inline void __init mem_init_free_highmem(void)
 
 void __init mem_init(void)
 {
+	/*
+	 * When _PFN_SHIFT is greater than PAGE_SHIFT we won't have enough PTE
+	 * bits to hold a full 32b physical address on MIPS32 systems.
+	 */
+	BUILD_BUG_ON(IS_ENABLED(CONFIG_32BIT) && (_PFN_SHIFT > PAGE_SHIFT));
+
 #ifdef CONFIG_HIGHMEM
 #ifdef CONFIG_DISCONTIGMEM
 #error "CONFIG_HIGHMEM and CONFIG_DISCONTIGMEM dont work together yet"
-- 
2.23.0