* [PATCH 1/4] MIPS: Massage address spaces headers
2020-04-26 11:47 [PATCH 0/4] MIPS: Loongson64: Use logic_pio Jiaxun Yang
@ 2020-04-26 11:47 ` Jiaxun Yang
2020-04-26 11:47 ` [PATCH 2/4] MIPS: Introduce PCI_IO_VMMAP Jiaxun Yang
` (4 subsequent siblings)
5 siblings, 0 replies; 27+ messages in thread
From: Jiaxun Yang @ 2020-04-26 11:47 UTC (permalink / raw)
To: linux-mips
Cc: Jiaxun Yang, Thomas Bogendoerfer, Huacai Chen, Paul Burton,
Serge Semin, Thomas Gleixner, Stephen Kitt, Nick Desaulniers,
Andrew Morton, Anshuman Khandual, Geert Uytterhoeven,
Vlastimil Babka, Daniel Silsby, Mike Rapoport, Paul Cercueil,
Philippe Mathieu-Daudé,
Mark Tomlinson, Greg Kroah-Hartman, Allison Randal, Tiezhu Yang,
Wei Xu, John Garry, linux-kernel
That would allow us modify kernel vm address spaces without
step into the hell of includes.
Also use some marcos for address spaces to make spaces.h more
clear.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/include/asm/addrspace.h | 4 +--
arch/mips/include/asm/mach-generic/spaces.h | 33 ++++++++++++++-------
arch/mips/include/asm/page-def.h | 28 +++++++++++++++++
arch/mips/include/asm/page.h | 21 -------------
arch/mips/include/asm/pgtable-32.h | 2 --
arch/mips/include/asm/pgtable-64.h | 10 ++-----
arch/mips/include/asm/sync.h | 2 ++
arch/mips/kernel/cps-vec.S | 3 +-
arch/mips/lib/uncached.c | 6 ++--
9 files changed, 60 insertions(+), 49 deletions(-)
create mode 100644 arch/mips/include/asm/page-def.h
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 59a48c60a065..4fa8ee48ef02 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -10,7 +10,7 @@
#ifndef _ASM_ADDRSPACE_H
#define _ASM_ADDRSPACE_H
-#include <spaces.h>
+#include <linux/const.h>
/*
* Configure language
@@ -67,7 +67,7 @@
#define XKSEG _CONST64_(0xc000000000000000)
#define CKSEG0 _CONST64_(0xffffffff80000000)
#define CKSEG1 _CONST64_(0xffffffffa0000000)
-#define CKSSEG _CONST64_(0xffffffffc0000000)
+#define CKSEG2 _CONST64_(0xffffffffc0000000)
#define CKSEG3 _CONST64_(0xffffffffe0000000)
#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
index ee5ebe98f6cf..89162740951a 100644
--- a/arch/mips/include/asm/mach-generic/spaces.h
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -10,9 +10,9 @@
#ifndef _ASM_MACH_GENERIC_SPACES_H
#define _ASM_MACH_GENERIC_SPACES_H
-#include <linux/const.h>
-
+#include <asm/addrspace.h>
#include <asm/mipsregs.h>
+#include <asm/page-def.h>
/*
* This gives the physical RAM offset.
@@ -29,20 +29,20 @@
#ifdef CONFIG_KVM_GUEST
#define CAC_BASE _AC(0x40000000, UL)
#else
-#define CAC_BASE _AC(0x80000000, UL)
+#define CAC_BASE CKSEG0
#endif
#ifndef IO_BASE
-#define IO_BASE _AC(0xa0000000, UL)
+#define IO_BASE CKSEG1
#endif
#ifndef UNCAC_BASE
-#define UNCAC_BASE _AC(0xa0000000, UL)
+#define UNCAC_BASE CKSEG1
#endif
#ifndef MAP_BASE
#ifdef CONFIG_KVM_GUEST
#define MAP_BASE _AC(0x60000000, UL)
#else
-#define MAP_BASE _AC(0xc0000000, UL)
+#define MAP_BASE CKSEG2
#endif
#endif
@@ -58,19 +58,19 @@
#ifdef CONFIG_64BIT
#ifndef CAC_BASE
-#define CAC_BASE PHYS_TO_XKPHYS(read_c0_config() & CONF_CM_CMASK, 0)
+#define CAC_BASE PHYS_TO_XKPHYS(read_c0_config() & CONF_CM_CMASK, 0)
#endif
#ifndef IO_BASE
-#define IO_BASE _AC(0x9000000000000000, UL)
+#define IO_BASE PHYS_TO_XKPHYS(K_CALG_UNCACHED, 0)
#endif
#ifndef UNCAC_BASE
-#define UNCAC_BASE _AC(0x9000000000000000, UL)
+#define UNCAC_BASE PHYS_TO_XKPHYS(K_CALG_UNCACHED, 0)
#endif
#ifndef MAP_BASE
-#define MAP_BASE _AC(0xc000000000000000, UL)
+#define MAP_BASE XKSEG
#endif
/*
@@ -99,8 +99,19 @@
#ifdef CONFIG_KVM_GUEST
#define FIXADDR_TOP ((unsigned long)(long)(int)0x7ffe0000)
#else
-#define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
+#define FIXADDR_TOP (CKSEG3 + 0x1ffe0000)
+#endif
#endif
+
+#ifdef CONFIG_64BIT
+/*
+ * TLB refill handlers also map the vmalloc area into xuseg. Avoid
+ * the first couple of pages so NULL pointer dereferences will still
+ * reliably trap.
+ */
+#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE))
+#else
+#define VMALLOC_START MAP_BASE
#endif
#endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/arch/mips/include/asm/page-def.h b/arch/mips/include/asm/page-def.h
new file mode 100644
index 000000000000..a0110bcff7b3
--- /dev/null
+++ b/arch/mips/include/asm/page-def.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_PAGE_DEF_H
+#define __ASM_PAGE_DEF_H
+
+#include <linux/const.h>
+/*
+ * PAGE_SHIFT determines the page size
+ */
+#ifdef CONFIG_PAGE_SIZE_4KB
+#define PAGE_SHIFT 12
+#endif
+#ifdef CONFIG_PAGE_SIZE_8KB
+#define PAGE_SHIFT 13
+#endif
+#ifdef CONFIG_PAGE_SIZE_16KB
+#define PAGE_SHIFT 14
+#endif
+#ifdef CONFIG_PAGE_SIZE_32KB
+#define PAGE_SHIFT 15
+#endif
+#ifdef CONFIG_PAGE_SIZE_64KB
+#define PAGE_SHIFT 16
+#endif
+#define PAGE_SIZE (_AC(1 ,UL) << PAGE_SHIFT)
+#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
+
+#endif /* __ASM_PAGE_DEF_H */
+
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index e2f503fc7a84..07f6a55eec5d 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -14,27 +14,6 @@
#include <linux/kernel.h>
#include <asm/mipsregs.h>
-/*
- * PAGE_SHIFT determines the page size
- */
-#ifdef CONFIG_PAGE_SIZE_4KB
-#define PAGE_SHIFT 12
-#endif
-#ifdef CONFIG_PAGE_SIZE_8KB
-#define PAGE_SHIFT 13
-#endif
-#ifdef CONFIG_PAGE_SIZE_16KB
-#define PAGE_SHIFT 14
-#endif
-#ifdef CONFIG_PAGE_SIZE_32KB
-#define PAGE_SHIFT 15
-#endif
-#ifdef CONFIG_PAGE_SIZE_64KB
-#define PAGE_SHIFT 16
-#endif
-#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
-
/*
* This is used for calculating the real page sizes
* for FTLB or VTLB + FTLB configurations.
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index 1945c8970141..40049fda596b 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -95,8 +95,6 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
#define FIRST_USER_ADDRESS 0UL
-#define VMALLOC_START MAP_BASE
-
#define PKMAP_END ((FIXADDR_START) & ~((LAST_PKMAP << PAGE_SHIFT)-1))
#define PKMAP_BASE (PKMAP_END - PAGE_SIZE * LAST_PKMAP)
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index ee5dc0c145b9..037aec0a14de 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -139,21 +139,15 @@
#define USER_PTRS_PER_PGD ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1)
#define FIRST_USER_ADDRESS 0UL
-/*
- * TLB refill handlers also map the vmalloc area into xuseg. Avoid
- * the first couple of pages so NULL pointer dereferences will still
- * reliably trap.
- */
-#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE))
#define VMALLOC_END \
(MAP_BASE + \
min(PTRS_PER_PGD * PTRS_PER_PUD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \
(1UL << cpu_vmbits)) - (1UL << 32))
#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \
- VMALLOC_START != CKSSEG
+ VMALLOC_START != CKSEG2
/* Load modules into 32bit-compatible segment. */
-#define MODULE_START CKSSEG
+#define MODULE_START CKSEG2
#define MODULE_END (FIXADDR_START-2*PAGE_SIZE)
#endif
diff --git a/arch/mips/include/asm/sync.h b/arch/mips/include/asm/sync.h
index aabd097933fe..8b297255854b 100644
--- a/arch/mips/include/asm/sync.h
+++ b/arch/mips/include/asm/sync.h
@@ -2,6 +2,8 @@
#ifndef __MIPS_ASM_SYNC_H__
#define __MIPS_ASM_SYNC_H__
+#include <linux/stringify.h>
+
/*
* sync types are defined by the MIPS64 Instruction Set documentation in Volume
* II-A of the MIPS Architecture Reference Manual, which can be found here:
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index 4db7ff055c9f..ba5e89825308 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -4,7 +4,8 @@
* Author: Paul Burton <paul.burton@mips.com>
*/
-#include <asm/addrspace.h>
+#include <spaces.h>
+
#include <asm/asm.h>
#include <asm/asm-offsets.h>
#include <asm/asmmacro.h>
diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
index 09d5deea747f..5736f3f4c24f 100644
--- a/arch/mips/lib/uncached.c
+++ b/arch/mips/lib/uncached.c
@@ -9,13 +9,11 @@
*/
-#include <asm/addrspace.h>
+#include <spaces.h>
+
#include <asm/bug.h>
#include <asm/cacheflush.h>
-#ifndef CKSEG2
-#define CKSEG2 CKSSEG
-#endif
#ifndef TO_PHYS_MASK
#define TO_PHYS_MASK -1
#endif
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 2/4] MIPS: Introduce PCI_IO_VMMAP
2020-04-26 11:47 [PATCH 0/4] MIPS: Loongson64: Use logic_pio Jiaxun Yang
2020-04-26 11:47 ` [PATCH 1/4] MIPS: Massage address spaces headers Jiaxun Yang
@ 2020-04-26 11:47 ` Jiaxun Yang
2020-04-26 11:47 ` [PATCH 3/4] lib: logic_pio: Introduce MMIO_LOWER_RESERVED Jiaxun Yang
` (3 subsequent siblings)
5 siblings, 0 replies; 27+ messages in thread
From: Jiaxun Yang @ 2020-04-26 11:47 UTC (permalink / raw)
To: linux-mips
Cc: Jiaxun Yang, Thomas Bogendoerfer, Huacai Chen, Paul Burton,
Thomas Gleixner, Nathan Chancellor, Stephen Kitt, Serge Semin,
Nick Desaulniers, Philippe Mathieu-Daudé,
Anshuman Khandual, Geert Uytterhoeven, Paul Cercueil,
Mike Rapoport, Daniel Silsby, Mark Tomlinson, Greg Kroah-Hartman,
Allison Randal, Tiezhu Yang, John Garry, Wei Xu, linux-kernel
Define PCI_IOBASE for MIPS at the strat of kernel mapping segment.
That would allow virt address of I/O ports to be dynamicly mapped.
So we'll be able to combine multiple MMIO ranges into I/O ports
and thus we can take advantage of logic_pio mechanism.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/Kconfig | 3 ++
arch/mips/include/asm/io.h | 36 ++++++++++++++++-----
arch/mips/include/asm/mach-generic/spaces.h | 13 ++++++--
arch/mips/kernel/setup.c | 2 ++
arch/mips/lib/iomap-pci.c | 2 +-
5 files changed, 45 insertions(+), 11 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0519ca9f00f9..4e5308178649 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -3149,6 +3149,9 @@ config PCI_DRIVERS_LEGACY
select NO_GENERIC_PCI_IOPORT_MAP
select PCI_DOMAINS if PCI
+config PCI_IO_VMMAP
+ def_bool n
+
#
# ISA support is now enabled via select. Too many systems still have the one
# or other ISA chip on the board that users don't know about so don't expect
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 346fffd9e972..f15ddcd27f35 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -51,17 +51,36 @@
/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
+/*
+ * On MIPS I/O ports are memory mapped, so we access them using normal
+ * load/store instructions.
+ */
+#ifdef CONFIG_PCI_IO_VMMAP
+/*
+ * I/O port access primitives for dymatic I/O ports mapping.
+ *
+ * We'll create kmap for I/O ports in this space.
+ */
+#define arch_has_dev_port() (1)
+#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1)
+#define PCI_IOBASE ((void __iomem *)PCI_IO_START)
+#define IOPORT_RW_BASE PCI_IO_START
+
+#else
+
#define IO_SPACE_LIMIT 0xffff
/*
- * On MIPS I/O ports are memory mapped, so we access them using normal
- * load/store instructions. mips_io_port_base is the virtual address to
- * which all ports are being mapped. For sake of efficiency some code
- * assumes that this is an address that can be loaded with a single lui
- * instruction, so the lower 16 bits must be zero. Should be true on
- * on any sane architecture; generic code does not use this assumption.
+ * I/O port access primitives for fixed I/O ports mapping.
+ *
+ * mips_io_port_base is the virtual address to which all ports are
+ * being mapped. For sake of efficiency some code assumes that this
+ * is an address that can be loaded with a single lui, instruction, so
+ * the lower 16 bits must be zero. Should be true on on any sane architecture;
+ * generic code does not use this assumption.
*/
extern unsigned long mips_io_port_base;
+#define IOPORT_RW_BASE mips_io_port_base
static inline void set_io_port_base(unsigned long base)
{
@@ -78,6 +97,7 @@ static inline void set_io_port_base(unsigned long base)
#define PIO_OFFSET mips_io_port_base
#define PIO_MASK IO_SPACE_LIMIT
#define PIO_RESERVED 0x0UL
+#endif
/*
* Enforce in-order execution of data I/O. In the MIPS architecture
@@ -308,7 +328,7 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \
else \
war_io_reorder_wmb(); \
\
- __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+ __addr = (void *)__swizzle_addr_##bwlq(IOPORT_RW_BASE + port); \
\
__val = pfx##ioswab##bwlq(__addr, val); \
\
@@ -323,7 +343,7 @@ static inline type pfx##in##bwlq##p(unsigned long port) \
volatile type *__addr; \
type __val; \
\
- __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+ __addr = (void *)__swizzle_addr_##bwlq(IOPORT_RW_BASE + port); \
\
BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
\
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
index 89162740951a..a39714c5fd7b 100644
--- a/arch/mips/include/asm/mach-generic/spaces.h
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -103,15 +103,24 @@
#endif
#endif
+#ifdef CONFIG_PCI_IO_VMMAP
+#define PCI_IO_SIZE SZ_16M
+#else
+#define PCI_IO_SIZE 0
+#endif
+
#ifdef CONFIG_64BIT
/*
* TLB refill handlers also map the vmalloc area into xuseg. Avoid
* the first couple of pages so NULL pointer dereferences will still
* reliably trap.
*/
-#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE))
+#define PCI_IO_START (MAP_BASE + (2 * PAGE_SIZE))
#else
-#define VMALLOC_START MAP_BASE
+#define PCI_IO_START MAP_BASE
#endif
+#define PCI_IO_END (PCI_IO_START + PCI_IO_SIZE)
+#define VMALLOC_START PCI_IO_END
+
#endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 8db533cd816c..99225539de3c 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -73,12 +73,14 @@ static const char builtin_cmdline[] __initconst = CONFIG_CMDLINE;
static const char builtin_cmdline[] __initconst = "";
#endif
+#ifndef CONFIG_PCI_IO_VMMAP
/*
* mips_io_port_base is the begin of the address space to which x86 style
* I/O ports are mapped.
*/
unsigned long mips_io_port_base = -1;
EXPORT_SYMBOL(mips_io_port_base);
+#endif
static struct resource code_resource = { .name = "Kernel code", };
static struct resource data_resource = { .name = "Kernel data", };
diff --git a/arch/mips/lib/iomap-pci.c b/arch/mips/lib/iomap-pci.c
index 210f5a95ecb1..f28924aaac1d 100644
--- a/arch/mips/lib/iomap-pci.c
+++ b/arch/mips/lib/iomap-pci.c
@@ -27,7 +27,7 @@ void __iomem *__pci_ioport_map(struct pci_dev *dev,
while (bus->parent)
bus = bus->parent;
- ctrl->io_map_base = base = mips_io_port_base;
+ ctrl->io_map_base = base = IOPORT_RW_BASE;
sprintf(name, "%04x:%02x", pci_domain_nr(bus), bus->number);
printk(KERN_WARNING "io_map_base of root PCI bus %s unset. "
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 3/4] lib: logic_pio: Introduce MMIO_LOWER_RESERVED
2020-04-26 11:47 [PATCH 0/4] MIPS: Loongson64: Use logic_pio Jiaxun Yang
2020-04-26 11:47 ` [PATCH 1/4] MIPS: Massage address spaces headers Jiaxun Yang
2020-04-26 11:47 ` [PATCH 2/4] MIPS: Introduce PCI_IO_VMMAP Jiaxun Yang
@ 2020-04-26 11:47 ` Jiaxun Yang
2020-04-27 10:43 ` John Garry
2020-04-26 11:47 ` [PATCH 4/4] MIPS: Loongson64: Enable PCI_IO_VMMAP Jiaxun Yang
` (2 subsequent siblings)
5 siblings, 1 reply; 27+ messages in thread
From: Jiaxun Yang @ 2020-04-26 11:47 UTC (permalink / raw)
To: linux-mips
Cc: Jiaxun Yang, Thomas Bogendoerfer, Huacai Chen, Paul Burton,
Thomas Gleixner, Stephen Kitt, Nick Desaulniers, Serge Semin,
Anshuman Khandual, Geert Uytterhoeven, Andrew Morton,
Daniel Silsby, Mike Rapoport, Paul Cercueil, Mark Tomlinson,
Greg Kroah-Hartman, Allison Randal, Tiezhu Yang, John Garry,
Wei Xu, linux-kernel
That would allow platforms reserve some lower address in PIO MMIO range
to deal with legacy drivers with hardcoded I/O ports that can't be
managed by logic_pio.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
lib/logic_pio.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/lib/logic_pio.c b/lib/logic_pio.c
index f511a99bb389..57fff1cb7063 100644
--- a/lib/logic_pio.c
+++ b/lib/logic_pio.c
@@ -20,6 +20,10 @@
static LIST_HEAD(io_range_list);
static DEFINE_MUTEX(io_range_mutex);
+#ifndef MMIO_LOWER_RESERVED
+#define MMIO_LOWER_RESERVED 0
+#endif
+
/* Consider a kernel general helper for this */
#define in_range(b, first, len) ((b) >= (first) && (b) < (first) + (len))
@@ -36,7 +40,7 @@ int logic_pio_register_range(struct logic_pio_hwaddr *new_range)
struct logic_pio_hwaddr *range;
resource_size_t start;
resource_size_t end;
- resource_size_t mmio_end = 0;
+ resource_size_t mmio_end = MMIO_LOWER_RESERVED;
resource_size_t iio_sz = MMIO_UPPER_LIMIT;
int ret = 0;
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 3/4] lib: logic_pio: Introduce MMIO_LOWER_RESERVED
2020-04-26 11:47 ` [PATCH 3/4] lib: logic_pio: Introduce MMIO_LOWER_RESERVED Jiaxun Yang
@ 2020-04-27 10:43 ` John Garry
2020-04-27 11:03 ` Jiaxun Yang
0 siblings, 1 reply; 27+ messages in thread
From: John Garry @ 2020-04-27 10:43 UTC (permalink / raw)
To: Jiaxun Yang, linux-mips
Cc: Thomas Bogendoerfer, Huacai Chen, Paul Burton, Thomas Gleixner,
Stephen Kitt, Nick Desaulniers, Serge Semin, Anshuman Khandual,
Geert Uytterhoeven, Andrew Morton, Daniel Silsby, Mike Rapoport,
Paul Cercueil, Mark Tomlinson, Greg Kroah-Hartman,
Allison Randal, Tiezhu Yang, Wei Xu, linux-kernel, Arnd Bergmann,
Linuxarm, Bjorn Helgaas, Rob Herring
On 26/04/2020 12:47, Jiaxun Yang wrote:
> That would allow platforms reserve some lower address in PIO MMIO range
> to deal with legacy drivers with hardcoded I/O ports that can't be
> managed by logic_pio.
Hi,
Is there some reason why the logic_pio code cannot be improved to handle
these devices at these "fixed" addresses? Or do you have a plan to
improve it? We already support fixed bus address devices in the INDIRECT
IO region.
Carving out a region of IO space is less than ideal.
Thanks,
John
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> lib/logic_pio.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/lib/logic_pio.c b/lib/logic_pio.c
> index f511a99bb389..57fff1cb7063 100644
> --- a/lib/logic_pio.c
> +++ b/lib/logic_pio.c
> @@ -20,6 +20,10 @@
> static LIST_HEAD(io_range_list);
> static DEFINE_MUTEX(io_range_mutex);
>
> +#ifndef MMIO_LOWER_RESERVED
> +#define MMIO_LOWER_RESERVED 0
> +#endif
> +
> /* Consider a kernel general helper for this */
> #define in_range(b, first, len) ((b) >= (first) && (b) < (first) + (len))
>
> @@ -36,7 +40,7 @@ int logic_pio_register_range(struct logic_pio_hwaddr *new_range)
> struct logic_pio_hwaddr *range;
> resource_size_t start;
> resource_size_t end;
> - resource_size_t mmio_end = 0;
> + resource_size_t mmio_end = MMIO_LOWER_RESERVED;
> resource_size_t iio_sz = MMIO_UPPER_LIMIT;
> int ret = 0;
>
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 3/4] lib: logic_pio: Introduce MMIO_LOWER_RESERVED
2020-04-27 10:43 ` John Garry
@ 2020-04-27 11:03 ` Jiaxun Yang
2020-04-27 11:54 ` John Garry
0 siblings, 1 reply; 27+ messages in thread
From: Jiaxun Yang @ 2020-04-27 11:03 UTC (permalink / raw)
To: John Garry, linux-mips
Cc: Thomas Bogendoerfer, Huacai Chen, Paul Burton, Thomas Gleixner,
Stephen Kitt, Nick Desaulniers, Serge Semin, Anshuman Khandual,
Geert Uytterhoeven, Andrew Morton, Daniel Silsby, Mike Rapoport,
Paul Cercueil, Mark Tomlinson, Greg Kroah-Hartman,
Allison Randal, Tiezhu Yang, Wei Xu, linux-kernel, Arnd Bergmann,
Linuxarm, Bjorn Helgaas, Rob Herring
于 2020年4月27日 GMT+08:00 下午6:43:09, John Garry <john.garry@huawei.com> 写到:
>On 26/04/2020 12:47, Jiaxun Yang wrote:
>> That would allow platforms reserve some lower address in PIO MMIO range
>> to deal with legacy drivers with hardcoded I/O ports that can't be
>> managed by logic_pio.
>
>Hi,
>
>Is there some reason why the logic_pio code cannot be improved to handle
>these devices at these "fixed" addresses? Or do you have a plan to
>improve it? We already support fixed bus address devices in the INDIRECT
>IO region.
Hi,
The issue about "Fixed Address" is we can't control the ioport
That driver used to operate devices.
So any attempt to resolve it in logic_pio seems impossible.
Currently we have i8259, i8042, piix4_smbus, mc146818 rely on this assumption.
My plan is after getting this part merged, I'm going to work on a ISA Host bridge driver,
then convert device drivers into logic_pio and Devicetree based driver step by step.
Finally when we nologner have any legacy driver, we can safely remove this reserved
range.
Thanks.
>
>Carving out a region of IO space is less than ideal.
>
>Thanks,
>John
>
>>
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> ---
>> lib/logic_pio.c | 6 +++++-
>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/lib/logic_pio.c b/lib/logic_pio.c
>> index f511a99bb389..57fff1cb7063 100644
>> --- a/lib/logic_pio.c
>> +++ b/lib/logic_pio.c
>> @@ -20,6 +20,10 @@
>> static LIST_HEAD(io_range_list);
>> static DEFINE_MUTEX(io_range_mutex);
>>
>> +#ifndef MMIO_LOWER_RESERVED
>> +#define MMIO_LOWER_RESERVED 0
>> +#endif
>> +
>> /* Consider a kernel general helper for this */
>> #define in_range(b, first, len) ((b) >= (first) && (b) < (first) + (len))
>>
>> @@ -36,7 +40,7 @@ int logic_pio_register_range(struct logic_pio_hwaddr *new_range)
>> struct logic_pio_hwaddr *range;
>> resource_size_t start;
>> resource_size_t end;
>> - resource_size_t mmio_end = 0;
>> + resource_size_t mmio_end = MMIO_LOWER_RESERVED;
>> resource_size_t iio_sz = MMIO_UPPER_LIMIT;
>> int ret = 0;
>>
>>
>
--
Jiaxun Yang
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 3/4] lib: logic_pio: Introduce MMIO_LOWER_RESERVED
2020-04-27 11:03 ` Jiaxun Yang
@ 2020-04-27 11:54 ` John Garry
2020-04-27 12:21 ` Jiaxun Yang
0 siblings, 1 reply; 27+ messages in thread
From: John Garry @ 2020-04-27 11:54 UTC (permalink / raw)
To: jiaxun.yang, Arnd Bergmann, Bjorn Helgaas
Cc: linux-mips, Thomas Bogendoerfer, Huacai Chen, Paul Burton,
Thomas Gleixner, Stephen Kitt, Nick Desaulniers, Serge Semin,
Anshuman Khandual, Geert Uytterhoeven, Andrew Morton,
Daniel Silsby, Mike Rapoport, Paul Cercueil, Mark Tomlinson,
Greg Kroah-Hartman, Allison Randal, Tiezhu Yang, Wei Xu,
linux-kernel, Linuxarm, Rob Herring, linux-arch
On 27/04/2020 12:03, Jiaxun Yang wrote:
>
>
> 于 2020年4月27日 GMT+08:00 下午6:43:09, John Garry <john.garry@huawei.com> 写到:
>> On 26/04/2020 12:47, Jiaxun Yang wrote:
>>> That would allow platforms reserve some lower address in PIO MMIO range
>>> to deal with legacy drivers with hardcoded I/O ports that can't be
>>> managed by logic_pio.
>>
>> Hi,
>>
>> Is there some reason why the logic_pio code cannot be improved to handle
>> these devices at these "fixed" addresses? Or do you have a plan to
>> improve it? We already support fixed bus address devices in the INDIRECT
>> IO region.
>
> Hi,
>
> The issue about "Fixed Address" is we can't control the ioport
> That driver used to operate devices.
> So any attempt to resolve it in logic_pio seems impossible.
>
> Currently we have i8259, i8042, piix4_smbus, mc146818 rely on this assumption.
Right, and from glancing at a couple of drivers you mentioned, if we
were to register a logic pio region for that legacy region, there does
not seem to be an easy place to fixup to use logic pio addresses (for
those devices). They use hardcoded values. However if all those drivers
were mips specific, you could fixup those drivers to use logic_pio
addresses today through some macro. But not sure on that.
So, going back to your change, I have a dilemma wondering whether you
should still register a logic pio region for the legacy region instead
of the carveout reservation, but ensure it is the first region
registered, such that logic pio address base is 0 and no translation is
required. At least then you have a region registered and it shows in
/proc/ioports, but then this whole thing becomes a bit fragile.
Maybe Arnd or Bjorn have an opinion on this.
Thanks,
John
>
> My plan is after getting this part merged, I'm going to work on a ISA Host bridge driver,
> then convert device drivers into logic_pio and Devicetree based driver step by step.
>
> Finally when we nologner have any legacy driver, we can safely remove this reserved
> range.
>
> Thanks.
>
>
>>
>> Carving out a region of IO space is less than ideal.
>>
>> Thanks,
>> John
>>
>>>
>>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>>> ---
>>> lib/logic_pio.c | 6 +++++-
>>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/lib/logic_pio.c b/lib/logic_pio.c
>>> index f511a99bb389..57fff1cb7063 100644
>>> --- a/lib/logic_pio.c
>>> +++ b/lib/logic_pio.c
>>> @@ -20,6 +20,10 @@
>>> static LIST_HEAD(io_range_list);
>>> static DEFINE_MUTEX(io_range_mutex);
>>>
>>> +#ifndef MMIO_LOWER_RESERVED
>>> +#define MMIO_LOWER_RESERVED 0
>>> +#endif
>>> +
>>> /* Consider a kernel general helper for this */
>>> #define in_range(b, first, len) ((b) >= (first) && (b) < (first) + (len))
>>>
>>> @@ -36,7 +40,7 @@ int logic_pio_register_range(struct logic_pio_hwaddr *new_range)
>>> struct logic_pio_hwaddr *range;
>>> resource_size_t start;
>>> resource_size_t end;
>>> - resource_size_t mmio_end = 0;
>>> + resource_size_t mmio_end = MMIO_LOWER_RESERVED;
>>> resource_size_t iio_sz = MMIO_UPPER_LIMIT;
>>> int ret = 0;
>>>
>>>
>>
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 3/4] lib: logic_pio: Introduce MMIO_LOWER_RESERVED
2020-04-27 11:54 ` John Garry
@ 2020-04-27 12:21 ` Jiaxun Yang
0 siblings, 0 replies; 27+ messages in thread
From: Jiaxun Yang @ 2020-04-27 12:21 UTC (permalink / raw)
To: John Garry
Cc: Arnd Bergmann, Bjorn Helgaas, linux-mips, Thomas Bogendoerfer,
Huacai Chen, Paul Burton, Thomas Gleixner, Stephen Kitt,
Nick Desaulniers, Serge Semin, Anshuman Khandual,
Geert Uytterhoeven, Andrew Morton, Daniel Silsby, Mike Rapoport,
Paul Cercueil, Mark Tomlinson, Greg Kroah-Hartman,
Allison Randal, Tiezhu Yang, Wei Xu, linux-kernel, Linuxarm,
Rob Herring, linux-arch
On Mon, 27 Apr 2020 12:54:06 +0100
John Garry <john.garry@huawei.com> wrote:
> On 27/04/2020 12:03, Jiaxun Yang wrote:
> >
> >
> > 于 2020年4月27日 GMT+08:00 下午6:43:09, John Garry
> > <john.garry@huawei.com> 写到:
> >> On 26/04/2020 12:47, Jiaxun Yang wrote:
> >>> That would allow platforms reserve some lower address in PIO MMIO
> >>> range to deal with legacy drivers with hardcoded I/O ports that
> >>> can't be managed by logic_pio.
> >>
> >> Hi,
> >>
> >> Is there some reason why the logic_pio code cannot be improved to
> >> handle these devices at these "fixed" addresses? Or do you have a
> >> plan to improve it? We already support fixed bus address devices
> >> in the INDIRECT IO region.
> >
> > Hi,
> >
> > The issue about "Fixed Address" is we can't control the ioport
> > That driver used to operate devices.
> > So any attempt to resolve it in logic_pio seems impossible.
> >
> > Currently we have i8259, i8042, piix4_smbus, mc146818 rely on this
> > assumption.
>
> Right, and from glancing at a couple of drivers you mentioned, if we
> were to register a logic pio region for that legacy region, there
> does not seem to be an easy place to fixup to use logic pio addresses
> (for those devices). They use hardcoded values. However if all those
> drivers were mips specific, you could fixup those drivers to use
> logic_pio addresses today through some macro. But not sure on that.
>
Well, most of these drivers are shared with x86 so....
I guess the conversion needs two or more release cycles.
>
> So, going back to your change, I have a dilemma wondering whether you
> should still register a logic pio region for the legacy region
> instead of the carveout reservation, but ensure it is the first
> region registered, such that logic pio address base is 0 and no
> translation is required. At least then you have a region registered
> and it shows in /proc/ioports, but then this whole thing becomes a
> bit fragile.
Thanks for your solution. So I must register this range as early as
possible. As IRQ is the first subsystem using ISA, I'll do it before
IRQ init, just at the place I setup iormap for reserved region now.
Should be early enough to avoid any collision, as the only logic_pio
user on our system is PCI controller.
Thanks.
>
--
Jiaxun Yang
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 4/4] MIPS: Loongson64: Enable PCI_IO_VMMAP
2020-04-26 11:47 [PATCH 0/4] MIPS: Loongson64: Use logic_pio Jiaxun Yang
` (2 preceding siblings ...)
2020-04-26 11:47 ` [PATCH 3/4] lib: logic_pio: Introduce MMIO_LOWER_RESERVED Jiaxun Yang
@ 2020-04-26 11:47 ` Jiaxun Yang
2020-04-30 0:57 ` [PATCH v3 1/3] MIPS: Move VMALLOC_START into spaces.h Jiaxun Yang
2020-05-08 11:44 ` [PATCH RESEND v3 1/3] MIPS: Move VMALLOC_START into spaces.h Jiaxun Yang
5 siblings, 0 replies; 27+ messages in thread
From: Jiaxun Yang @ 2020-04-26 11:47 UTC (permalink / raw)
To: linux-mips
Cc: Jiaxun Yang, Thomas Bogendoerfer, Huacai Chen, Paul Burton,
Stephen Kitt, Andrew Morton, Nick Desaulniers, Serge Semin,
Geert Uytterhoeven, Anshuman Khandual,
Philippe Mathieu-Daudé,
Mike Rapoport, Daniel Silsby, Paul Cercueil, Mark Tomlinson,
Greg Kroah-Hartman, Allison Randal, Thomas Gleixner, Tiezhu Yang,
Wei Xu, John Garry, linux-kernel
Finally we are able to elegantly add I/O ports for PCI host bridge
via devicetree with logic_pio.
To deal with legacy drivers that have fixed I/O ports range we
reserved 0x10000 in PCI_IOBASE, should be enough for i8259 i8042
stuff.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/Kconfig | 1 +
arch/mips/include/asm/io.h | 4 ++++
arch/mips/loongson64/init.c | 12 ++++++++----
arch/mips/loongson64/pci.c | 2 +-
4 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 4e5308178649..1669735dacd8 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -479,6 +479,7 @@ config MACH_LOONGSON64
select I8259
select IRQ_MIPS_CPU
select NR_CPUS_DEFAULT_64
+ select PCI_IO_VMMAP
select USE_GENERIC_EARLY_PRINTK_8250
select SYS_HAS_CPU_LOONGSON64
select SYS_HAS_EARLY_PRINTK
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index f15ddcd27f35..7f9716c95aa0 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -66,6 +66,10 @@
#define PCI_IOBASE ((void __iomem *)PCI_IO_START)
#define IOPORT_RW_BASE PCI_IO_START
+#ifdef CONFIG_MACH_LOONGSON64
+#define MMIO_LOWER_RESERVED 0x10000
+#endif
+
#else
#define IO_SPACE_LIMIT 0xffff
diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c
index da38944471f4..3117edbbea46 100644
--- a/arch/mips/loongson64/init.c
+++ b/arch/mips/loongson64/init.c
@@ -29,10 +29,6 @@ void __init prom_init(void)
fw_init_cmdline();
prom_init_env();
- /* init base address of io space */
- set_io_port_base((unsigned long)
- ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
-
prom_init_numa_memory();
/* Hardcode to CPU UART 0 */
@@ -48,5 +44,13 @@ void __init prom_free_prom_memory(void)
void __init arch_init_irq(void)
{
+ /*
+ * i8259 would access I/O space, so mapping must be done here.
+ * Please remove it when all drivers can be managed by logic_pio.
+ */
+ ioremap_page_range(PCI_IO_START, PCI_IO_START + MMIO_LOWER_RESERVED,
+ LOONGSON_PCIIO_BASE,
+ pgprot_device(PAGE_KERNEL));
+
irqchip_init();
}
diff --git a/arch/mips/loongson64/pci.c b/arch/mips/loongson64/pci.c
index a440a2725a20..7aecb88dd377 100644
--- a/arch/mips/loongson64/pci.c
+++ b/arch/mips/loongson64/pci.c
@@ -37,7 +37,7 @@ extern int sbx00_acpi_init(void);
static int __init pcibios_init(void)
{
- loongson_pci_controller.io_map_base = mips_io_port_base;
+ loongson_pci_controller.io_map_base = IOPORT_RW_BASE;
loongson_pci_mem_resource.start = loongson_sysconf.pci_mem_start_addr;
loongson_pci_mem_resource.end = loongson_sysconf.pci_mem_end_addr;
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v3 1/3] MIPS: Move VMALLOC_START into spaces.h
2020-04-26 11:47 [PATCH 0/4] MIPS: Loongson64: Use logic_pio Jiaxun Yang
` (3 preceding siblings ...)
2020-04-26 11:47 ` [PATCH 4/4] MIPS: Loongson64: Enable PCI_IO_VMMAP Jiaxun Yang
@ 2020-04-30 0:57 ` Jiaxun Yang
2020-04-30 0:57 ` [PATCH v3 2/3] MIPS: Introduce PCI_IO_VMMAP Jiaxun Yang
2020-04-30 0:57 ` [PATCH v3 3/3] MIPS: Loongson64: Enable PCI_IO_VMMAP Jiaxun Yang
2020-05-08 11:44 ` [PATCH RESEND v3 1/3] MIPS: Move VMALLOC_START into spaces.h Jiaxun Yang
5 siblings, 2 replies; 27+ messages in thread
From: Jiaxun Yang @ 2020-04-30 0:57 UTC (permalink / raw)
To: linux-mips; +Cc: chenhc, tsbogend, john.garry, Jiaxun Yang
That would allow us modify kernel vm address spaces without
step into the hell of includes.
Also move some page defines into page-def.h to allow PAGE_SIZE
to be used in spaces.h.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/include/asm/mach-generic/spaces.h | 12 +++++++++
arch/mips/include/asm/page-def.h | 28 +++++++++++++++++++++
arch/mips/include/asm/page.h | 21 ----------------
arch/mips/include/asm/pgtable-32.h | 2 --
arch/mips/include/asm/pgtable-64.h | 6 -----
5 files changed, 40 insertions(+), 29 deletions(-)
create mode 100644 arch/mips/include/asm/page-def.h
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
index ee5ebe98f6cf..44fefde46a10 100644
--- a/arch/mips/include/asm/mach-generic/spaces.h
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -13,6 +13,7 @@
#include <linux/const.h>
#include <asm/mipsregs.h>
+#include <asm/page-def.h>
/*
* This gives the physical RAM offset.
@@ -103,4 +104,15 @@
#endif
#endif
+#ifdef CONFIG_64BIT
+/*
+ * TLB refill handlers also map the vmalloc area into xuseg. Avoid
+ * the first couple of pages so NULL pointer dereferences will still
+ * reliably trap.
+ */
+#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE))
+#else
+#define VMALLOC_START MAP_BASE
+#endif
+
#endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/arch/mips/include/asm/page-def.h b/arch/mips/include/asm/page-def.h
new file mode 100644
index 000000000000..6506b611f44b
--- /dev/null
+++ b/arch/mips/include/asm/page-def.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_PAGE_DEF_H
+#define __ASM_PAGE_DEF_H
+
+#include <linux/const.h>
+
+/*
+ * PAGE_SHIFT determines the page size
+ */
+#ifdef CONFIG_PAGE_SIZE_4KB
+#define PAGE_SHIFT 12
+#endif
+#ifdef CONFIG_PAGE_SIZE_8KB
+#define PAGE_SHIFT 13
+#endif
+#ifdef CONFIG_PAGE_SIZE_16KB
+#define PAGE_SHIFT 14
+#endif
+#ifdef CONFIG_PAGE_SIZE_32KB
+#define PAGE_SHIFT 15
+#endif
+#ifdef CONFIG_PAGE_SIZE_64KB
+#define PAGE_SHIFT 16
+#endif
+#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
+#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
+
+#endif /* __ASM_PAGE_DEF_H */
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index e2f503fc7a84..07f6a55eec5d 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -14,27 +14,6 @@
#include <linux/kernel.h>
#include <asm/mipsregs.h>
-/*
- * PAGE_SHIFT determines the page size
- */
-#ifdef CONFIG_PAGE_SIZE_4KB
-#define PAGE_SHIFT 12
-#endif
-#ifdef CONFIG_PAGE_SIZE_8KB
-#define PAGE_SHIFT 13
-#endif
-#ifdef CONFIG_PAGE_SIZE_16KB
-#define PAGE_SHIFT 14
-#endif
-#ifdef CONFIG_PAGE_SIZE_32KB
-#define PAGE_SHIFT 15
-#endif
-#ifdef CONFIG_PAGE_SIZE_64KB
-#define PAGE_SHIFT 16
-#endif
-#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
-
/*
* This is used for calculating the real page sizes
* for FTLB or VTLB + FTLB configurations.
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index 1945c8970141..40049fda596b 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -95,8 +95,6 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
#define FIRST_USER_ADDRESS 0UL
-#define VMALLOC_START MAP_BASE
-
#define PKMAP_END ((FIXADDR_START) & ~((LAST_PKMAP << PAGE_SHIFT)-1))
#define PKMAP_BASE (PKMAP_END - PAGE_SIZE * LAST_PKMAP)
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index ee5dc0c145b9..a3fb463ba86a 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -139,12 +139,6 @@
#define USER_PTRS_PER_PGD ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1)
#define FIRST_USER_ADDRESS 0UL
-/*
- * TLB refill handlers also map the vmalloc area into xuseg. Avoid
- * the first couple of pages so NULL pointer dereferences will still
- * reliably trap.
- */
-#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE))
#define VMALLOC_END \
(MAP_BASE + \
min(PTRS_PER_PGD * PTRS_PER_PUD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v3 2/3] MIPS: Introduce PCI_IO_VMMAP
2020-04-30 0:57 ` [PATCH v3 1/3] MIPS: Move VMALLOC_START into spaces.h Jiaxun Yang
@ 2020-04-30 0:57 ` Jiaxun Yang
2020-04-30 0:57 ` [PATCH v3 3/3] MIPS: Loongson64: Enable PCI_IO_VMMAP Jiaxun Yang
1 sibling, 0 replies; 27+ messages in thread
From: Jiaxun Yang @ 2020-04-30 0:57 UTC (permalink / raw)
To: linux-mips; +Cc: chenhc, tsbogend, john.garry, Jiaxun Yang
Define PCI_IOBASE for MIPS at the strat of kernel mapping segment.
That would allow virt address of I/O ports to be dynamicly mapped.
So we'll be able to combine multiple MMIO ranges into I/O ports
and thus we can take advantage of logic_pio mechanism.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/Kconfig | 3 ++
arch/mips/include/asm/io.h | 36 ++++++++++++++++-----
arch/mips/include/asm/mach-generic/spaces.h | 13 ++++++--
arch/mips/kernel/setup.c | 2 ++
arch/mips/lib/iomap-pci.c | 2 +-
5 files changed, 45 insertions(+), 11 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0519ca9f00f9..4e5308178649 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -3149,6 +3149,9 @@ config PCI_DRIVERS_LEGACY
select NO_GENERIC_PCI_IOPORT_MAP
select PCI_DOMAINS if PCI
+config PCI_IO_VMMAP
+ def_bool n
+
#
# ISA support is now enabled via select. Too many systems still have the one
# or other ISA chip on the board that users don't know about so don't expect
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 346fffd9e972..f15ddcd27f35 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -51,17 +51,36 @@
/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
+/*
+ * On MIPS I/O ports are memory mapped, so we access them using normal
+ * load/store instructions.
+ */
+#ifdef CONFIG_PCI_IO_VMMAP
+/*
+ * I/O port access primitives for dymatic I/O ports mapping.
+ *
+ * We'll create kmap for I/O ports in this space.
+ */
+#define arch_has_dev_port() (1)
+#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1)
+#define PCI_IOBASE ((void __iomem *)PCI_IO_START)
+#define IOPORT_RW_BASE PCI_IO_START
+
+#else
+
#define IO_SPACE_LIMIT 0xffff
/*
- * On MIPS I/O ports are memory mapped, so we access them using normal
- * load/store instructions. mips_io_port_base is the virtual address to
- * which all ports are being mapped. For sake of efficiency some code
- * assumes that this is an address that can be loaded with a single lui
- * instruction, so the lower 16 bits must be zero. Should be true on
- * on any sane architecture; generic code does not use this assumption.
+ * I/O port access primitives for fixed I/O ports mapping.
+ *
+ * mips_io_port_base is the virtual address to which all ports are
+ * being mapped. For sake of efficiency some code assumes that this
+ * is an address that can be loaded with a single lui, instruction, so
+ * the lower 16 bits must be zero. Should be true on on any sane architecture;
+ * generic code does not use this assumption.
*/
extern unsigned long mips_io_port_base;
+#define IOPORT_RW_BASE mips_io_port_base
static inline void set_io_port_base(unsigned long base)
{
@@ -78,6 +97,7 @@ static inline void set_io_port_base(unsigned long base)
#define PIO_OFFSET mips_io_port_base
#define PIO_MASK IO_SPACE_LIMIT
#define PIO_RESERVED 0x0UL
+#endif
/*
* Enforce in-order execution of data I/O. In the MIPS architecture
@@ -308,7 +328,7 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \
else \
war_io_reorder_wmb(); \
\
- __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+ __addr = (void *)__swizzle_addr_##bwlq(IOPORT_RW_BASE + port); \
\
__val = pfx##ioswab##bwlq(__addr, val); \
\
@@ -323,7 +343,7 @@ static inline type pfx##in##bwlq##p(unsigned long port) \
volatile type *__addr; \
type __val; \
\
- __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+ __addr = (void *)__swizzle_addr_##bwlq(IOPORT_RW_BASE + port); \
\
BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
\
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
index 44fefde46a10..adf559db50cd 100644
--- a/arch/mips/include/asm/mach-generic/spaces.h
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -104,15 +104,24 @@
#endif
#endif
+#ifdef CONFIG_PCI_IO_VMMAP
+#define PCI_IO_SIZE SZ_16M
+#else
+#define PCI_IO_SIZE 0
+#endif
+
#ifdef CONFIG_64BIT
/*
* TLB refill handlers also map the vmalloc area into xuseg. Avoid
* the first couple of pages so NULL pointer dereferences will still
* reliably trap.
*/
-#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE))
+#define PCI_IO_START (MAP_BASE + (2 * PAGE_SIZE))
#else
-#define VMALLOC_START MAP_BASE
+#define PCI_IO_START MAP_BASE
#endif
+#define PCI_IO_END (PCI_IO_START + PCI_IO_SIZE)
+#define VMALLOC_START PCI_IO_END
+
#endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 8db533cd816c..99225539de3c 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -73,12 +73,14 @@ static const char builtin_cmdline[] __initconst = CONFIG_CMDLINE;
static const char builtin_cmdline[] __initconst = "";
#endif
+#ifndef CONFIG_PCI_IO_VMMAP
/*
* mips_io_port_base is the begin of the address space to which x86 style
* I/O ports are mapped.
*/
unsigned long mips_io_port_base = -1;
EXPORT_SYMBOL(mips_io_port_base);
+#endif
static struct resource code_resource = { .name = "Kernel code", };
static struct resource data_resource = { .name = "Kernel data", };
diff --git a/arch/mips/lib/iomap-pci.c b/arch/mips/lib/iomap-pci.c
index 210f5a95ecb1..f28924aaac1d 100644
--- a/arch/mips/lib/iomap-pci.c
+++ b/arch/mips/lib/iomap-pci.c
@@ -27,7 +27,7 @@ void __iomem *__pci_ioport_map(struct pci_dev *dev,
while (bus->parent)
bus = bus->parent;
- ctrl->io_map_base = base = mips_io_port_base;
+ ctrl->io_map_base = base = IOPORT_RW_BASE;
sprintf(name, "%04x:%02x", pci_domain_nr(bus), bus->number);
printk(KERN_WARNING "io_map_base of root PCI bus %s unset. "
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v3 3/3] MIPS: Loongson64: Enable PCI_IO_VMMAP
2020-04-30 0:57 ` [PATCH v3 1/3] MIPS: Move VMALLOC_START into spaces.h Jiaxun Yang
2020-04-30 0:57 ` [PATCH v3 2/3] MIPS: Introduce PCI_IO_VMMAP Jiaxun Yang
@ 2020-04-30 0:57 ` Jiaxun Yang
1 sibling, 0 replies; 27+ messages in thread
From: Jiaxun Yang @ 2020-04-30 0:57 UTC (permalink / raw)
To: linux-mips; +Cc: chenhc, tsbogend, john.garry, Jiaxun Yang
Finally we are able to elegantly add I/O ports for PCI host bridge
via devicetree with logic_pio.
To deal with legacy drivers that have fixed I/O ports range we
reserved 0x10000 in PCI_IOBASE, should be enough for i8259 i8042
stuff.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/Kconfig | 1 +
.../include/asm/mach-loongson64/loongson.h | 2 +
arch/mips/loongson64/init.c | 43 +++++++++++++++++--
arch/mips/loongson64/pci.c | 2 +-
4 files changed, 43 insertions(+), 5 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 4e5308178649..1669735dacd8 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -479,6 +479,7 @@ config MACH_LOONGSON64
select I8259
select IRQ_MIPS_CPU
select NR_CPUS_DEFAULT_64
+ select PCI_IO_VMMAP
select USE_GENERIC_EARLY_PRINTK_8250
select SYS_HAS_CPU_LOONGSON64
select SYS_HAS_EARLY_PRINTK
diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h
index fde1b75c45ea..94035a47be5b 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson.h
@@ -86,6 +86,8 @@ extern int mach_i8259_irq(void);
#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
+#define MMIO_LOWER_RESERVED 0x10000
+
/* Loongson Register Bases */
#define LOONGSON_PCICONFIGBASE 0x00
diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c
index da38944471f4..f7c80b9e5243 100644
--- a/arch/mips/loongson64/init.c
+++ b/arch/mips/loongson64/init.c
@@ -5,6 +5,7 @@
*/
#include <linux/irqchip.h>
+#include <linux/logic_pio.h>
#include <linux/memblock.h>
#include <asm/bootinfo.h>
#include <asm/traps.h>
@@ -29,10 +30,6 @@ void __init prom_init(void)
fw_init_cmdline();
prom_init_env();
- /* init base address of io space */
- set_io_port_base((unsigned long)
- ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
-
prom_init_numa_memory();
/* Hardcode to CPU UART 0 */
@@ -46,7 +43,45 @@ void __init prom_free_prom_memory(void)
{
}
+static __init void reserve_pio_range(void)
+{
+ struct logic_pio_hwaddr *range;
+
+ range = kzalloc(sizeof(*range), GFP_ATOMIC);
+ if (!range)
+ return;
+
+ range->fwnode = &of_root->fwnode;
+ range->size = MMIO_LOWER_RESERVED;
+ range->hw_start = LOONGSON_PCIIO_BASE;
+ range->flags = LOGIC_PIO_CPU_MMIO;
+
+ if (logic_pio_register_range(range)) {
+ pr_err("Failed to reserve PIO range for legacy ISA\n");
+ goto free_range;
+ }
+
+ if (WARN(range->io_start != 0,
+ "Reserved PIO range does not start from 0\n"))
+ goto unregister;
+
+ /*
+ * i8259 would access I/O space, so mapping must be done here.
+ * Please remove it when all drivers can be managed by logic_pio.
+ */
+ ioremap_page_range(PCI_IO_START, PCI_IO_START + MMIO_LOWER_RESERVED,
+ LOONGSON_PCIIO_BASE,
+ pgprot_device(PAGE_KERNEL));
+
+ return;
+unregister:
+ logic_pio_unregister_range(range);
+free_range:
+ kfree(range);
+}
+
void __init arch_init_irq(void)
{
+ reserve_pio_range();
irqchip_init();
}
diff --git a/arch/mips/loongson64/pci.c b/arch/mips/loongson64/pci.c
index a440a2725a20..7aecb88dd377 100644
--- a/arch/mips/loongson64/pci.c
+++ b/arch/mips/loongson64/pci.c
@@ -37,7 +37,7 @@ extern int sbx00_acpi_init(void);
static int __init pcibios_init(void)
{
- loongson_pci_controller.io_map_base = mips_io_port_base;
+ loongson_pci_controller.io_map_base = IOPORT_RW_BASE;
loongson_pci_mem_resource.start = loongson_sysconf.pci_mem_start_addr;
loongson_pci_mem_resource.end = loongson_sysconf.pci_mem_end_addr;
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH RESEND v3 1/3] MIPS: Move VMALLOC_START into spaces.h
2020-04-26 11:47 [PATCH 0/4] MIPS: Loongson64: Use logic_pio Jiaxun Yang
` (4 preceding siblings ...)
2020-04-30 0:57 ` [PATCH v3 1/3] MIPS: Move VMALLOC_START into spaces.h Jiaxun Yang
@ 2020-05-08 11:44 ` Jiaxun Yang
2020-05-08 11:44 ` [PATCH RESEND v3 2/3] MIPS: Introduce PCI_IO_VMMAP Jiaxun Yang
2020-05-08 11:44 ` [PATCH RESEND v3 3/3] MIPS: Loongson64: Enable PCI_IO_VMMAP Jiaxun Yang
5 siblings, 2 replies; 27+ messages in thread
From: Jiaxun Yang @ 2020-05-08 11:44 UTC (permalink / raw)
To: linux-mips; +Cc: chenhc, tsbogend, john.garry, Jiaxun Yang
That would allow us modify kernel vm address spaces without
step into the hell of includes.
Also move some page defines into page-def.h to allow PAGE_SIZE
to be used in spaces.h.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
Resending as previous version was messed up.
---
arch/mips/include/asm/mach-generic/spaces.h | 12 +++++++++
arch/mips/include/asm/page-def.h | 28 +++++++++++++++++++++
arch/mips/include/asm/page.h | 21 ----------------
arch/mips/include/asm/pgtable-32.h | 2 --
arch/mips/include/asm/pgtable-64.h | 6 -----
5 files changed, 40 insertions(+), 29 deletions(-)
create mode 100644 arch/mips/include/asm/page-def.h
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
index ee5ebe98f6cf..44fefde46a10 100644
--- a/arch/mips/include/asm/mach-generic/spaces.h
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -13,6 +13,7 @@
#include <linux/const.h>
#include <asm/mipsregs.h>
+#include <asm/page-def.h>
/*
* This gives the physical RAM offset.
@@ -103,4 +104,15 @@
#endif
#endif
+#ifdef CONFIG_64BIT
+/*
+ * TLB refill handlers also map the vmalloc area into xuseg. Avoid
+ * the first couple of pages so NULL pointer dereferences will still
+ * reliably trap.
+ */
+#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE))
+#else
+#define VMALLOC_START MAP_BASE
+#endif
+
#endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/arch/mips/include/asm/page-def.h b/arch/mips/include/asm/page-def.h
new file mode 100644
index 000000000000..6506b611f44b
--- /dev/null
+++ b/arch/mips/include/asm/page-def.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_PAGE_DEF_H
+#define __ASM_PAGE_DEF_H
+
+#include <linux/const.h>
+
+/*
+ * PAGE_SHIFT determines the page size
+ */
+#ifdef CONFIG_PAGE_SIZE_4KB
+#define PAGE_SHIFT 12
+#endif
+#ifdef CONFIG_PAGE_SIZE_8KB
+#define PAGE_SHIFT 13
+#endif
+#ifdef CONFIG_PAGE_SIZE_16KB
+#define PAGE_SHIFT 14
+#endif
+#ifdef CONFIG_PAGE_SIZE_32KB
+#define PAGE_SHIFT 15
+#endif
+#ifdef CONFIG_PAGE_SIZE_64KB
+#define PAGE_SHIFT 16
+#endif
+#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
+#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
+
+#endif /* __ASM_PAGE_DEF_H */
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index e2f503fc7a84..07f6a55eec5d 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -14,27 +14,6 @@
#include <linux/kernel.h>
#include <asm/mipsregs.h>
-/*
- * PAGE_SHIFT determines the page size
- */
-#ifdef CONFIG_PAGE_SIZE_4KB
-#define PAGE_SHIFT 12
-#endif
-#ifdef CONFIG_PAGE_SIZE_8KB
-#define PAGE_SHIFT 13
-#endif
-#ifdef CONFIG_PAGE_SIZE_16KB
-#define PAGE_SHIFT 14
-#endif
-#ifdef CONFIG_PAGE_SIZE_32KB
-#define PAGE_SHIFT 15
-#endif
-#ifdef CONFIG_PAGE_SIZE_64KB
-#define PAGE_SHIFT 16
-#endif
-#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
-
/*
* This is used for calculating the real page sizes
* for FTLB or VTLB + FTLB configurations.
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index 1945c8970141..40049fda596b 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -95,8 +95,6 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
#define FIRST_USER_ADDRESS 0UL
-#define VMALLOC_START MAP_BASE
-
#define PKMAP_END ((FIXADDR_START) & ~((LAST_PKMAP << PAGE_SHIFT)-1))
#define PKMAP_BASE (PKMAP_END - PAGE_SIZE * LAST_PKMAP)
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index ee5dc0c145b9..a3fb463ba86a 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -139,12 +139,6 @@
#define USER_PTRS_PER_PGD ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1)
#define FIRST_USER_ADDRESS 0UL
-/*
- * TLB refill handlers also map the vmalloc area into xuseg. Avoid
- * the first couple of pages so NULL pointer dereferences will still
- * reliably trap.
- */
-#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE))
#define VMALLOC_END \
(MAP_BASE + \
min(PTRS_PER_PGD * PTRS_PER_PUD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH RESEND v3 2/3] MIPS: Introduce PCI_IO_VMMAP
2020-05-08 11:44 ` [PATCH RESEND v3 1/3] MIPS: Move VMALLOC_START into spaces.h Jiaxun Yang
@ 2020-05-08 11:44 ` Jiaxun Yang
2020-05-08 16:11 ` Thomas Bogendoerfer
2020-05-14 13:20 ` Jiaxun Yang
2020-05-08 11:44 ` [PATCH RESEND v3 3/3] MIPS: Loongson64: Enable PCI_IO_VMMAP Jiaxun Yang
1 sibling, 2 replies; 27+ messages in thread
From: Jiaxun Yang @ 2020-05-08 11:44 UTC (permalink / raw)
To: linux-mips; +Cc: chenhc, tsbogend, john.garry, Jiaxun Yang
Define PCI_IOBASE for MIPS at the strat of kernel mapping segment.
That would allow virt address of I/O ports to be dynamicly mapped.
So we'll be able to combine multiple MMIO ranges into I/O ports
and thus we can take advantage of logic_pio mechanism.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/Kconfig | 3 ++
arch/mips/include/asm/io.h | 36 ++++++++++++++++-----
arch/mips/include/asm/mach-generic/spaces.h | 13 ++++++--
arch/mips/kernel/setup.c | 2 ++
arch/mips/lib/iomap-pci.c | 2 +-
5 files changed, 45 insertions(+), 11 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0519ca9f00f9..4e5308178649 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -3149,6 +3149,9 @@ config PCI_DRIVERS_LEGACY
select NO_GENERIC_PCI_IOPORT_MAP
select PCI_DOMAINS if PCI
+config PCI_IO_VMMAP
+ def_bool n
+
#
# ISA support is now enabled via select. Too many systems still have the one
# or other ISA chip on the board that users don't know about so don't expect
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 346fffd9e972..f15ddcd27f35 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -51,17 +51,36 @@
/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
+/*
+ * On MIPS I/O ports are memory mapped, so we access them using normal
+ * load/store instructions.
+ */
+#ifdef CONFIG_PCI_IO_VMMAP
+/*
+ * I/O port access primitives for dymatic I/O ports mapping.
+ *
+ * We'll create kmap for I/O ports in this space.
+ */
+#define arch_has_dev_port() (1)
+#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1)
+#define PCI_IOBASE ((void __iomem *)PCI_IO_START)
+#define IOPORT_RW_BASE PCI_IO_START
+
+#else
+
#define IO_SPACE_LIMIT 0xffff
/*
- * On MIPS I/O ports are memory mapped, so we access them using normal
- * load/store instructions. mips_io_port_base is the virtual address to
- * which all ports are being mapped. For sake of efficiency some code
- * assumes that this is an address that can be loaded with a single lui
- * instruction, so the lower 16 bits must be zero. Should be true on
- * on any sane architecture; generic code does not use this assumption.
+ * I/O port access primitives for fixed I/O ports mapping.
+ *
+ * mips_io_port_base is the virtual address to which all ports are
+ * being mapped. For sake of efficiency some code assumes that this
+ * is an address that can be loaded with a single lui, instruction, so
+ * the lower 16 bits must be zero. Should be true on on any sane architecture;
+ * generic code does not use this assumption.
*/
extern unsigned long mips_io_port_base;
+#define IOPORT_RW_BASE mips_io_port_base
static inline void set_io_port_base(unsigned long base)
{
@@ -78,6 +97,7 @@ static inline void set_io_port_base(unsigned long base)
#define PIO_OFFSET mips_io_port_base
#define PIO_MASK IO_SPACE_LIMIT
#define PIO_RESERVED 0x0UL
+#endif
/*
* Enforce in-order execution of data I/O. In the MIPS architecture
@@ -308,7 +328,7 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \
else \
war_io_reorder_wmb(); \
\
- __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+ __addr = (void *)__swizzle_addr_##bwlq(IOPORT_RW_BASE + port); \
\
__val = pfx##ioswab##bwlq(__addr, val); \
\
@@ -323,7 +343,7 @@ static inline type pfx##in##bwlq##p(unsigned long port) \
volatile type *__addr; \
type __val; \
\
- __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
+ __addr = (void *)__swizzle_addr_##bwlq(IOPORT_RW_BASE + port); \
\
BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
\
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
index 44fefde46a10..adf559db50cd 100644
--- a/arch/mips/include/asm/mach-generic/spaces.h
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -104,15 +104,24 @@
#endif
#endif
+#ifdef CONFIG_PCI_IO_VMMAP
+#define PCI_IO_SIZE SZ_16M
+#else
+#define PCI_IO_SIZE 0
+#endif
+
#ifdef CONFIG_64BIT
/*
* TLB refill handlers also map the vmalloc area into xuseg. Avoid
* the first couple of pages so NULL pointer dereferences will still
* reliably trap.
*/
-#define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE))
+#define PCI_IO_START (MAP_BASE + (2 * PAGE_SIZE))
#else
-#define VMALLOC_START MAP_BASE
+#define PCI_IO_START MAP_BASE
#endif
+#define PCI_IO_END (PCI_IO_START + PCI_IO_SIZE)
+#define VMALLOC_START PCI_IO_END
+
#endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 8db533cd816c..99225539de3c 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -73,12 +73,14 @@ static const char builtin_cmdline[] __initconst = CONFIG_CMDLINE;
static const char builtin_cmdline[] __initconst = "";
#endif
+#ifndef CONFIG_PCI_IO_VMMAP
/*
* mips_io_port_base is the begin of the address space to which x86 style
* I/O ports are mapped.
*/
unsigned long mips_io_port_base = -1;
EXPORT_SYMBOL(mips_io_port_base);
+#endif
static struct resource code_resource = { .name = "Kernel code", };
static struct resource data_resource = { .name = "Kernel data", };
diff --git a/arch/mips/lib/iomap-pci.c b/arch/mips/lib/iomap-pci.c
index 210f5a95ecb1..f28924aaac1d 100644
--- a/arch/mips/lib/iomap-pci.c
+++ b/arch/mips/lib/iomap-pci.c
@@ -27,7 +27,7 @@ void __iomem *__pci_ioport_map(struct pci_dev *dev,
while (bus->parent)
bus = bus->parent;
- ctrl->io_map_base = base = mips_io_port_base;
+ ctrl->io_map_base = base = IOPORT_RW_BASE;
sprintf(name, "%04x:%02x", pci_domain_nr(bus), bus->number);
printk(KERN_WARNING "io_map_base of root PCI bus %s unset. "
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH RESEND v3 2/3] MIPS: Introduce PCI_IO_VMMAP
2020-05-08 11:44 ` [PATCH RESEND v3 2/3] MIPS: Introduce PCI_IO_VMMAP Jiaxun Yang
@ 2020-05-08 16:11 ` Thomas Bogendoerfer
2020-05-08 16:22 ` Jiaxun Yang
2020-05-14 13:20 ` Jiaxun Yang
1 sibling, 1 reply; 27+ messages in thread
From: Thomas Bogendoerfer @ 2020-05-08 16:11 UTC (permalink / raw)
To: Jiaxun Yang; +Cc: linux-mips, chenhc, john.garry
On Fri, May 08, 2020 at 07:44:37PM +0800, Jiaxun Yang wrote:
> Define PCI_IOBASE for MIPS at the strat of kernel mapping segment.
> That would allow virt address of I/O ports to be dynamicly mapped.
> So we'll be able to combine multiple MMIO ranges into I/O ports
> and thus we can take advantage of logic_pio mechanism.
What is the advantage ?
From my point of view this will be slower because of TLB faults for
PCI IO space accesses.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH RESEND v3 2/3] MIPS: Introduce PCI_IO_VMMAP
2020-05-08 16:11 ` Thomas Bogendoerfer
@ 2020-05-08 16:22 ` Jiaxun Yang
2020-05-08 16:52 ` Thomas Bogendoerfer
0 siblings, 1 reply; 27+ messages in thread
From: Jiaxun Yang @ 2020-05-08 16:22 UTC (permalink / raw)
To: Thomas Bogendoerfer; +Cc: linux-mips, chenhc, john.garry
于 2020年5月9日 GMT+08:00 上午12:11:02, Thomas Bogendoerfer <tsbogend@alpha.franken.de> 写到:
>On Fri, May 08, 2020 at 07:44:37PM +0800, Jiaxun Yang wrote:
>> Define PCI_IOBASE for MIPS at the strat of kernel mapping segment.
>> That would allow virt address of I/O ports to be dynamicly mapped.
>> So we'll be able to combine multiple MMIO ranges into I/O ports
>> and thus we can take advantage of logic_pio mechanism.
>
>What is the advantage ?
>
>From my point of view this will be slower because of TLB faults for
>PCI IO space accesses.
Advantage is we can use logic_pio to manage multiple I/O Port ranges.
That can help us reuse generic PCI I/O design.
Thanks.
>
>Thomas.
>
--
Jiaxun Yang
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH RESEND v3 2/3] MIPS: Introduce PCI_IO_VMMAP
2020-05-08 16:22 ` Jiaxun Yang
@ 2020-05-08 16:52 ` Thomas Bogendoerfer
2020-05-08 17:09 ` Jiaxun Yang
0 siblings, 1 reply; 27+ messages in thread
From: Thomas Bogendoerfer @ 2020-05-08 16:52 UTC (permalink / raw)
To: Jiaxun Yang; +Cc: linux-mips, chenhc, john.garry
On Sat, May 09, 2020 at 12:22:25AM +0800, Jiaxun Yang wrote:
>
>
> 于 2020年5月9日 GMT+08:00 上午12:11:02, Thomas Bogendoerfer <tsbogend@alpha.franken.de> 写到:
> >On Fri, May 08, 2020 at 07:44:37PM +0800, Jiaxun Yang wrote:
> >> Define PCI_IOBASE for MIPS at the strat of kernel mapping segment.
> >> That would allow virt address of I/O ports to be dynamicly mapped.
> >> So we'll be able to combine multiple MMIO ranges into I/O ports
> >> and thus we can take advantage of logic_pio mechanism.
> >
> >What is the advantage ?
> >
> >From my point of view this will be slower because of TLB faults for
> >PCI IO space accesses.
>
> Advantage is we can use logic_pio to manage multiple I/O Port ranges.
and what exactly does this buy us ? I looked at lib/logic_pio.c and
there didn't appear anything in my mind other than yet another
interface for doing the same thing...
> That can help us reuse generic PCI I/O design.
please explain this.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH RESEND v3 2/3] MIPS: Introduce PCI_IO_VMMAP
2020-05-08 16:52 ` Thomas Bogendoerfer
@ 2020-05-08 17:09 ` Jiaxun Yang
2020-05-14 14:21 ` Thomas Bogendoerfer
0 siblings, 1 reply; 27+ messages in thread
From: Jiaxun Yang @ 2020-05-08 17:09 UTC (permalink / raw)
To: Thomas Bogendoerfer; +Cc: linux-mips, chenhc, john.garry
于 2020年5月9日 GMT+08:00 上午12:52:35, Thomas Bogendoerfer <tsbogend@alpha.franken.de> 写到:
>On Sat, May 09, 2020 at 12:22:25AM +0800, Jiaxun Yang wrote:
>>
>>
>> 于 2020年5月9日 GMT+08:00 上午12:11:02, Thomas Bogendoerfer <tsbogend@alpha.franken.de> 写到:
>> >On Fri, May 08, 2020 at 07:44:37PM +0800, Jiaxun Yang wrote:
>> >> Define PCI_IOBASE for MIPS at the strat of kernel mapping segment.
>> >> That would allow virt address of I/O ports to be dynamicly mapped.
>> >> So we'll be able to combine multiple MMIO ranges into I/O ports
>> >> and thus we can take advantage of logic_pio mechanism.
>> >
>> >What is the advantage ?
>> >
>> >From my point of view this will be slower because of TLB faults for
>> >PCI IO space accesses.
>>
>> Advantage is we can use logic_pio to manage multiple I/O Port ranges.
>
>and what exactly does this buy us ? I looked at lib/logic_pio.c and
>there didn't appear anything in my mind other than yet another
>interface for doing the same thing...
With Logic_PIO subsystem, each I/O region will be registered
in logic_pio and being mapped in TLB, that means I/O regions can l
be sparsely layouted in MMIO.
And device drivers are accessing in*/out* functions via ioport allocated by
logic_pio instead of the physical I/O ports.
That will allow multiple I/O port region exist in a system.
>
>> That can help us reuse generic PCI I/O design.
>
>please explain this.
Generic PCI code are handling MMIO I/O ports via logic_pio,
it will register a logic_pio range for each Host Bridge's MMIO I/O ports.
Thanks.
>
>Thomas.
>
--
Jiaxun Yang
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH RESEND v3 2/3] MIPS: Introduce PCI_IO_VMMAP
2020-05-08 17:09 ` Jiaxun Yang
@ 2020-05-14 14:21 ` Thomas Bogendoerfer
2020-05-14 14:56 ` Jiaxun Yang
0 siblings, 1 reply; 27+ messages in thread
From: Thomas Bogendoerfer @ 2020-05-14 14:21 UTC (permalink / raw)
To: Jiaxun Yang; +Cc: linux-mips, chenhc, john.garry
On Sat, May 09, 2020 at 01:09:07AM +0800, Jiaxun Yang wrote:
>
>
> 于 2020年5月9日 GMT+08:00 上午12:52:35, Thomas Bogendoerfer <tsbogend@alpha.franken.de> 写到:
> >On Sat, May 09, 2020 at 12:22:25AM +0800, Jiaxun Yang wrote:
> >>
> >>
> >> 于 2020年5月9日 GMT+08:00 上午12:11:02, Thomas Bogendoerfer <tsbogend@alpha.franken.de> 写到:
> >> >On Fri, May 08, 2020 at 07:44:37PM +0800, Jiaxun Yang wrote:
> >> >> Define PCI_IOBASE for MIPS at the strat of kernel mapping segment.
> >> >> That would allow virt address of I/O ports to be dynamicly mapped.
> >> >> So we'll be able to combine multiple MMIO ranges into I/O ports
> >> >> and thus we can take advantage of logic_pio mechanism.
> >> >
> >> >What is the advantage ?
> >> >
> >> >From my point of view this will be slower because of TLB faults for
> >> >PCI IO space accesses.
> >>
> >> Advantage is we can use logic_pio to manage multiple I/O Port ranges.
> >
> >and what exactly does this buy us ? I looked at lib/logic_pio.c and
> >there didn't appear anything in my mind other than yet another
> >interface for doing the same thing...
>
> With Logic_PIO subsystem, each I/O region will be registered
> in logic_pio and being mapped in TLB, that means I/O regions can l
> be sparsely layouted in MMIO.
this isn't an advantage. You will get TLB miss exceptions, which you
don't get when using XPHYS addresses, which the current code does.
IMHO it you make more sense to use normal iomap/iounmap functions
in logic_pio.c. With that you would get TLB less access for memory
mapped PCI IO regions.
> And device drivers are accessing in*/out* functions via ioport allocated by
> logic_pio instead of the physical I/O ports.
your current patches don't select INDIRECT_PIO, so you are still
using the MIPS access methods just via the mapping from logic_pio. This
works as long as you are using already mapped ranges. This is at least
inconsistent.
If you really want to ignore the TLB miss problem, please drop
patch 1 and 2 and use something like
#define PCI_IOBASE _AC(0xc000000000000000, UL)
#define PCI_IOSIZE SZ_16SM
#define MAP_BASE (PCI_IOBASE + PCI_IOSIZE)
in arch/mips/include/asm/mach-loongson64/spaces.h
That should do the trick without moving stuff around and it will
keep it out of the normal MIPS stuff.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH RESEND v3 2/3] MIPS: Introduce PCI_IO_VMMAP
2020-05-14 14:21 ` Thomas Bogendoerfer
@ 2020-05-14 14:56 ` Jiaxun Yang
0 siblings, 0 replies; 27+ messages in thread
From: Jiaxun Yang @ 2020-05-14 14:56 UTC (permalink / raw)
To: Thomas Bogendoerfer; +Cc: linux-mips, chenhc, john.garry
于 2020年5月14日 GMT+08:00 下午10:21:49, Thomas Bogendoerfer <tsbogend@alpha.franken.de> 写到:
>On Sat, May 09, 2020 at 01:09:07AM +0800, Jiaxun Yang wrote:
>>
>>
>> 于 2020年5月9日 GMT+08:00 上午12:52:35, Thomas Bogendoerfer <tsbogend@alpha.franken.de> 写到:
>> >On Sat, May 09, 2020 at 12:22:25AM +0800, Jiaxun Yang wrote:
>> >>
>> >>
>> >> 于 2020年5月9日 GMT+08:00 上午12:11:02, Thomas Bogendoerfer <tsbogend@alpha.franken.de> 写到:
>> >> >On Fri, May 08, 2020 at 07:44:37PM +0800, Jiaxun Yang wrote:
>> >> >> Define PCI_IOBASE for MIPS at the strat of kernel mapping segment.
>> >> >> That would allow virt address of I/O ports to be dynamicly mapped.
>> >> >> So we'll be able to combine multiple MMIO ranges into I/O ports
>> >> >> and thus we can take advantage of logic_pio mechanism.
>> >> >
>> >> >What is the advantage ?
>> >> >
>> >> >From my point of view this will be slower because of TLB faults for
>> >> >PCI IO space accesses.
>> >>
>> >> Advantage is we can use logic_pio to manage multiple I/O Port ranges.
>> >
>> >and what exactly does this buy us ? I looked at lib/logic_pio.c and
>> >there didn't appear anything in my mind other than yet another
>> >interface for doing the same thing...
>>
>> With Logic_PIO subsystem, each I/O region will be registered
>> in logic_pio and being mapped in TLB, that means I/O regions can l
>> be sparsely layouted in MMIO.
>
>this isn't an advantage. You will get TLB miss exceptions, which you
>don't get when using XPHYS addresses, which the current code does.
>IMHO it you make more sense to use normal iomap/iounmap functions
>in logic_pio.c. With that you would get TLB less access for memory
>mapped PCI IO regions.
>
>> And device drivers are accessing in*/out* functions via ioport allocated by
>> logic_pio instead of the physical I/O ports.
>
>your current patches don't select INDIRECT_PIO, so you are still
>using the MIPS access methods just via the mapping from logic_pio. This
>works as long as you are using already mapped ranges. This is at least
>inconsistent.
Not exactly. I'm emulating the behaviour of Aarch64's PCI ioport handling.
And the mapping will done by pci_remap_iospace when adding resources
to PCI bridge.
PCI subsystem will ensure all the ioports they used is mapped so there won't be any inconsistent.
Except some legacy driver need to be converted.
Yeah, I was confused by logic_pio at very start and holded the same opinion
with you that it's totally misuse of MMIO ioports until John Garry
kindly explained [1] to me what it exactly did.
>
>If you really want to ignore the TLB miss problem, please drop
>patch 1 and 2 and use something like
>
>#define PCI_IOBASE _AC(0xc000000000000000, UL)
>#define PCI_IOSIZE SZ_16SM
>#define MAP_BASE (PCI_IOBASE + PCI_IOSIZE)
>
>in arch/mips/include/asm/mach-loongson64/spaces.h
>
>That should do the trick without moving stuff around and it will
>keep it out of the normal MIPS stuff.
I do believe that similar to Aarch64 world, device with multiple PCIe
host bridge and sparsely layouted MMIO IOport range will appear very soon.
So I'm creating a general method for MIPS.
If that's inappropriate for you
I'll make it as Loongson only.
Thanks.
>
>Thomas.
>
[1]: https://lkml.org/lkml/2020/2/20/1207
--
Jiaxun Yang
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH RESEND v3 2/3] MIPS: Introduce PCI_IO_VMMAP
2020-05-08 11:44 ` [PATCH RESEND v3 2/3] MIPS: Introduce PCI_IO_VMMAP Jiaxun Yang
2020-05-08 16:11 ` Thomas Bogendoerfer
@ 2020-05-14 13:20 ` Jiaxun Yang
1 sibling, 0 replies; 27+ messages in thread
From: Jiaxun Yang @ 2020-05-14 13:20 UTC (permalink / raw)
To: linux-mips; +Cc: chenhc, tsbogend, john.garry
On Fri, 8 May 2020 19:44:37 +0800
Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> Define PCI_IOBASE for MIPS at the strat of kernel mapping segment.
> That would allow virt address of I/O ports to be dynamicly mapped.
> So we'll be able to combine multiple MMIO ranges into I/O ports
> and thus we can take advantage of logic_pio mechanism.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
Any update?
Thanks.
[...]
--
Jiaxun Yang
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH RESEND v3 3/3] MIPS: Loongson64: Enable PCI_IO_VMMAP
2020-05-08 11:44 ` [PATCH RESEND v3 1/3] MIPS: Move VMALLOC_START into spaces.h Jiaxun Yang
2020-05-08 11:44 ` [PATCH RESEND v3 2/3] MIPS: Introduce PCI_IO_VMMAP Jiaxun Yang
@ 2020-05-08 11:44 ` Jiaxun Yang
2021-01-13 18:02 ` logical PIO code for mips question (was Re: [PATCH RESEND v3 3/3] MIPS: Loongson64: Enable PCI_IO_VMMAP) John Garry
1 sibling, 1 reply; 27+ messages in thread
From: Jiaxun Yang @ 2020-05-08 11:44 UTC (permalink / raw)
To: linux-mips; +Cc: chenhc, tsbogend, john.garry, Jiaxun Yang
Finally we are able to elegantly add I/O ports for PCI host bridge
via devicetree with logic_pio.
To deal with legacy drivers that have fixed I/O ports range we
reserved 0x10000 in PCI_IOBASE, should be enough for i8259 i8042
stuff.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
v3: Add warning to care ordering.
---
arch/mips/Kconfig | 1 +
.../include/asm/mach-loongson64/loongson.h | 2 +
arch/mips/loongson64/init.c | 43 +++++++++++++++++--
arch/mips/loongson64/pci.c | 2 +-
4 files changed, 43 insertions(+), 5 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 4e5308178649..1669735dacd8 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -479,6 +479,7 @@ config MACH_LOONGSON64
select I8259
select IRQ_MIPS_CPU
select NR_CPUS_DEFAULT_64
+ select PCI_IO_VMMAP
select USE_GENERIC_EARLY_PRINTK_8250
select SYS_HAS_CPU_LOONGSON64
select SYS_HAS_EARLY_PRINTK
diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h
index fde1b75c45ea..94035a47be5b 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson.h
@@ -86,6 +86,8 @@ extern int mach_i8259_irq(void);
#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
+#define MMIO_LOWER_RESERVED 0x10000
+
/* Loongson Register Bases */
#define LOONGSON_PCICONFIGBASE 0x00
diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c
index da38944471f4..f7c80b9e5243 100644
--- a/arch/mips/loongson64/init.c
+++ b/arch/mips/loongson64/init.c
@@ -5,6 +5,7 @@
*/
#include <linux/irqchip.h>
+#include <linux/logic_pio.h>
#include <linux/memblock.h>
#include <asm/bootinfo.h>
#include <asm/traps.h>
@@ -29,10 +30,6 @@ void __init prom_init(void)
fw_init_cmdline();
prom_init_env();
- /* init base address of io space */
- set_io_port_base((unsigned long)
- ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
-
prom_init_numa_memory();
/* Hardcode to CPU UART 0 */
@@ -46,7 +43,45 @@ void __init prom_free_prom_memory(void)
{
}
+static __init void reserve_pio_range(void)
+{
+ struct logic_pio_hwaddr *range;
+
+ range = kzalloc(sizeof(*range), GFP_ATOMIC);
+ if (!range)
+ return;
+
+ range->fwnode = &of_root->fwnode;
+ range->size = MMIO_LOWER_RESERVED;
+ range->hw_start = LOONGSON_PCIIO_BASE;
+ range->flags = LOGIC_PIO_CPU_MMIO;
+
+ if (logic_pio_register_range(range)) {
+ pr_err("Failed to reserve PIO range for legacy ISA\n");
+ goto free_range;
+ }
+
+ if (WARN(range->io_start != 0,
+ "Reserved PIO range does not start from 0\n"))
+ goto unregister;
+
+ /*
+ * i8259 would access I/O space, so mapping must be done here.
+ * Please remove it when all drivers can be managed by logic_pio.
+ */
+ ioremap_page_range(PCI_IO_START, PCI_IO_START + MMIO_LOWER_RESERVED,
+ LOONGSON_PCIIO_BASE,
+ pgprot_device(PAGE_KERNEL));
+
+ return;
+unregister:
+ logic_pio_unregister_range(range);
+free_range:
+ kfree(range);
+}
+
void __init arch_init_irq(void)
{
+ reserve_pio_range();
irqchip_init();
}
diff --git a/arch/mips/loongson64/pci.c b/arch/mips/loongson64/pci.c
index a440a2725a20..7aecb88dd377 100644
--- a/arch/mips/loongson64/pci.c
+++ b/arch/mips/loongson64/pci.c
@@ -37,7 +37,7 @@ extern int sbx00_acpi_init(void);
static int __init pcibios_init(void)
{
- loongson_pci_controller.io_map_base = mips_io_port_base;
+ loongson_pci_controller.io_map_base = IOPORT_RW_BASE;
loongson_pci_mem_resource.start = loongson_sysconf.pci_mem_start_addr;
loongson_pci_mem_resource.end = loongson_sysconf.pci_mem_end_addr;
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 27+ messages in thread* logical PIO code for mips question (was Re: [PATCH RESEND v3 3/3] MIPS: Loongson64: Enable PCI_IO_VMMAP)
2020-05-08 11:44 ` [PATCH RESEND v3 3/3] MIPS: Loongson64: Enable PCI_IO_VMMAP Jiaxun Yang
@ 2021-01-13 18:02 ` John Garry
2021-01-14 0:13 ` Jiaxun Yang
0 siblings, 1 reply; 27+ messages in thread
From: John Garry @ 2021-01-13 18:02 UTC (permalink / raw)
To: Jiaxun Yang, linux-mips; +Cc: chenhc, tsbogend
On 08/05/2020 12:44, Jiaxun Yang wrote:
Replying to an old mail ...
> range->fwnode = &of_root->fwnode;
> + range->size = MMIO_LOWER_RESERVED;
> + range->hw_start = LOONGSON_PCIIO_BASE;
> + range->flags = LOGIC_PIO_CPU_MMIO;
> +
> + if (logic_pio_register_range(range)) {
> + pr_err("Failed to reserve PIO range for legacy ISA\n");
> + goto free_range;
> + }
Hi Jiaxun,
> +
> + if (WARN(range->io_start != 0,
> + "Reserved PIO range does not start from 0\n"))
Do the mips code still rely on this check?
I was considering changing the logical PIO code to reserve the first 64K
of PCI MMIO space, but making that change would break this code as
things stand.
The motivation is that some drivers, like [0], access IO ports
unconditionally and can kill systems when no PCI host exists. By
reserving the first 64K, accesses by those drivers could nullified.
Thanks,
John
[0]
https://lore.kernel.org/linux-input/20210112055129.7840-1-song.bao.hua@hisilicon.com/T/#t
> + goto unregister;
> +
> + /*
> + * i8259 would access I/O space, so mapping must be done here.
> + * Please remove it when all drivers can be managed by logic_pio.
> + */
> + ioremap_page_range(PCI_IO_START, PCI_IO_START + MMIO_LOWER_RESERVED,
> + LOONGSON_PCIIO_BASE,
> + pgprot_device(PAGE_KERNEL));
> +
> + return;
> +unregister:
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: logical PIO code for mips question (was Re: [PATCH RESEND v3 3/3] MIPS: Loongson64: Enable PCI_IO_VMMAP)
2021-01-13 18:02 ` logical PIO code for mips question (was Re: [PATCH RESEND v3 3/3] MIPS: Loongson64: Enable PCI_IO_VMMAP) John Garry
@ 2021-01-14 0:13 ` Jiaxun Yang
2021-01-14 9:18 ` John Garry
0 siblings, 1 reply; 27+ messages in thread
From: Jiaxun Yang @ 2021-01-14 0:13 UTC (permalink / raw)
To: John Garry, linux-mips; +Cc: chenhc, tsbogend
在 2021/1/14 上午2:02, John Garry 写道:
> On 08/05/2020 12:44, Jiaxun Yang wrote:
>
> Replying to an old mail ...
>
>> range->fwnode = &of_root->fwnode;
>> + range->size = MMIO_LOWER_RESERVED;
>> + range->hw_start = LOONGSON_PCIIO_BASE;
>> + range->flags = LOGIC_PIO_CPU_MMIO;
>> +
>> + if (logic_pio_register_range(range)) {
>> + pr_err("Failed to reserve PIO range for legacy ISA\n");
>> + goto free_range;
>> + }
>
> Hi Jiaxun,
>
>> +
>> + if (WARN(range->io_start != 0,
>> + "Reserved PIO range does not start from 0\n"))
>
> Do the mips code still rely on this check?
Hi John,
Yes :-/
>
> I was considering changing the logical PIO code to reserve the first
> 64K of PCI MMIO space, but making that change would break this code as
> things stand.
>
> The motivation is that some drivers, like [0], access IO ports
> unconditionally and can kill systems when no PCI host exists. By
> reserving the first 64K, accesses by those drivers could nullified.
Actually we're trying to deal with almost the same problem.
The reserved region on MIPS is used to serve these driver that access
I/O ports bypassing resource subsystem.
Thanks.
- Jiaxun
>
> Thanks,
> John
>
> [0]
> https://lore.kernel.org/linux-input/20210112055129.7840-1-song.bao.hua@hisilicon.com/T/#t
>
>> + goto unregister;
>> +
>> + /*
>> + * i8259 would access I/O space, so mapping must be done here.
>> + * Please remove it when all drivers can be managed by logic_pio.
>> + */
>> + ioremap_page_range(PCI_IO_START, PCI_IO_START +
>> MMIO_LOWER_RESERVED,
>> + LOONGSON_PCIIO_BASE,
>> + pgprot_device(PAGE_KERNEL));
>> +
>> + return;
>> +unregister:
>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: logical PIO code for mips question (was Re: [PATCH RESEND v3 3/3] MIPS: Loongson64: Enable PCI_IO_VMMAP)
2021-01-14 0:13 ` Jiaxun Yang
@ 2021-01-14 9:18 ` John Garry
2021-01-14 11:10 ` Jiaxun Yang
0 siblings, 1 reply; 27+ messages in thread
From: John Garry @ 2021-01-14 9:18 UTC (permalink / raw)
To: Jiaxun Yang, linux-mips; +Cc: chenhc, tsbogend
On 14/01/2021 00:13, Jiaxun Yang wrote:
>>> range->fwnode = &of_root->fwnode;
>>> + range->size = MMIO_LOWER_RESERVED;
>>> + range->hw_start = LOONGSON_PCIIO_BASE;
>>> + range->flags = LOGIC_PIO_CPU_MMIO;
>>> +
>>> + if (logic_pio_register_range(range)) {
>>> + pr_err("Failed to reserve PIO range for legacy ISA\n");
>>> + goto free_range;
>>> + }
>>
>> Hi Jiaxun,
>>
>>> +
>>> + if (WARN(range->io_start != 0,
>>> + "Reserved PIO range does not start from 0\n"))
>>
>> Do the mips code still rely on this check?
Hi Jiaxun,
>
> Yes :-/
ok, but I was hoping that this dependency would be removed at some stage.
>
>>
>> I was considering changing the logical PIO code to reserve the first
>> 64K of PCI MMIO space, but making that change would break this code as
>> things stand.
>>
>> The motivation is that some drivers, like [0], access IO ports
>> unconditionally and can kill systems when no PCI host exists. By
>> reserving the first 64K, accesses by those drivers could nullified.
>
> Actually we're trying to deal with almost the same problem.
> The reserved region on MIPS is used to serve these driver that access
> I/O ports bypassing resource subsystem.
Yes, so reserving the first 64K of IO space would break mips, as things
stand. Has any work been done for these drivers that bypass resource
subsystem (or directly access hardcoded IO ports)?
I may just do this (reserve 64K) under INDIRECT_PIO for now, not sure yet.
Thanks,
John
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: logical PIO code for mips question (was Re: [PATCH RESEND v3 3/3] MIPS: Loongson64: Enable PCI_IO_VMMAP)
2021-01-14 9:18 ` John Garry
@ 2021-01-14 11:10 ` Jiaxun Yang
2021-01-14 11:20 ` John Garry
0 siblings, 1 reply; 27+ messages in thread
From: Jiaxun Yang @ 2021-01-14 11:10 UTC (permalink / raw)
To: John Garry, linux-mips; +Cc: chenhc, tsbogend
在 2021/1/14 下午5:18, John Garry 写道:
> On 14/01/2021 00:13, Jiaxun Yang wrote:
>>>> range->fwnode = &of_root->fwnode;
>>>> + range->size = MMIO_LOWER_RESERVED;
>>>> + range->hw_start = LOONGSON_PCIIO_BASE;
>>>> + range->flags = LOGIC_PIO_CPU_MMIO;
>>>> +
>>>> + if (logic_pio_register_range(range)) {
>>>> + pr_err("Failed to reserve PIO range for legacy ISA\n");
>>>> + goto free_range;
>>>> + }
>>>
>>> Hi Jiaxun,
>>>
>>>> +
>>>> + if (WARN(range->io_start != 0,
>>>> + "Reserved PIO range does not start from 0\n"))
>>>
>>> Do the mips code still rely on this check?
>
>
> Hi Jiaxun,
>
>>
>> Yes :-/
>
> ok, but I was hoping that this dependency would be removed at some stage.
>
>>
>>>
>>> I was considering changing the logical PIO code to reserve the first
>>> 64K of PCI MMIO space, but making that change would break this code
>>> as things stand.
>>>
>>> The motivation is that some drivers, like [0], access IO ports
>>> unconditionally and can kill systems when no PCI host exists. By
>>> reserving the first 64K, accesses by those drivers could nullified.
>>
>> Actually we're trying to deal with almost the same problem.
>> The reserved region on MIPS is used to serve these driver that access
>> I/O ports bypassing resource subsystem.
>
> Yes, so reserving the first 64K of IO space would break mips, as
> things stand. Has any work been done for these drivers that bypass
> resource subsystem (or directly access hardcoded IO ports)?
Not yet.
>
> I may just do this (reserve 64K) under INDIRECT_PIO for now, not sure
> yet.
Probably we can make the first page of LOGIC_PIO a special region. It
could be a
reserved region when no legacy ISA bus present or overlay by MMIO in
case like
MIPS here.
Thanks.
- Jiaxun
>
> Thanks,
> John
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: logical PIO code for mips question (was Re: [PATCH RESEND v3 3/3] MIPS: Loongson64: Enable PCI_IO_VMMAP)
2021-01-14 11:10 ` Jiaxun Yang
@ 2021-01-14 11:20 ` John Garry
0 siblings, 0 replies; 27+ messages in thread
From: John Garry @ 2021-01-14 11:20 UTC (permalink / raw)
To: Jiaxun Yang, linux-mips; +Cc: chenhc, tsbogend
On 14/01/2021 11:10, Jiaxun Yang wrote:
> Not yet.
>
>>
>> I may just do this (reserve 64K) under INDIRECT_PIO for now, not sure
>> yet.
>
> Probably we can make the first page of LOGIC_PIO a special region. It
> could be a
> reserved region when no legacy ISA bus present or overlay by MMIO in
> case like
> MIPS here.
Yeah, I could do that as well, but then I need special handling for that
region, which may complicate things.
Anyway, I'll cc you and linux-mips on any patch.
Thanks,
John
^ permalink raw reply [flat|nested] 27+ messages in thread