From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Serge Semin <fancer.lancer@gmail.com>,
Thomas Gleixner <tglx@linutronix.de>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
Rob Herring <robh+dt@kernel.org>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <maz@kernel.org>, James Hogan <jhogan@kernel.org>,
"open list:BROADCOM NVRAM DRIVER" <linux-mips@vger.kernel.org>,
DTML <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v5 5/6] bus: cdmm: Add MIPS R5 arch support
Date: Tue, 14 Jul 2020 17:15:04 +0300 [thread overview]
Message-ID: <20200714141504.oybqzaii5hcdy7cq@mobilestation> (raw)
In-Reply-To: <CAK8P3a09RW+zCMJ9Luh2C3NkYPdY4Esu6EKk_QX_i4faV-rUjg@mail.gmail.com>
On Tue, Jul 14, 2020 at 03:28:30PM +0200, Arnd Bergmann wrote:
> On Tue, Jul 14, 2020 at 2:58 PM Serge Semin
> <Sergey.Semin@baikalelectronics.ru> wrote:
> >
> > config MIPS_CDMM
> > bool "MIPS Common Device Memory Map (CDMM) Driver"
> > - depends on CPU_MIPSR2
> > + depends on CPU_MIPSR2 || CPU_MIPSR5
> > help
>
> Wouldn't a kernel built for P5600 have CPU_MIPSR2 set already?
No. P5600 core is based on MIPS32 r5, for which since 5.8 there has been a
dedicated kernel config CPU_MIPSR5 available.
> I thought R5 was just a backwards-compatible extension of R2.
Yes, it's an extension and they are compatible in most of aspects, but
there are still differences, which when activated/used make kernel built
for R5 being incompatible with R2. For instance there is an ISA
extension in R5 which hasn't been available in R5 like "eretnc"
(return from exceptions with no atomic flag cleared), "mfhc/mthc0"
(extended C0 register move instructions), etc. There is some other
features/optimizations available since R5. Please see commit
ab7c01fdc3cf ("mips: Add MIPS Release 5 support") for details.
>
> If not, what about R3?
Currently if some chip is equipped with R3, then the kernel must be built
for R2 with features like EVA enabled if it's required.
-Sergey
>
> Arnd
next prev parent reply other threads:[~2020-07-14 14:15 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-14 12:57 [PATCH v5 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC Serge Semin
2020-07-14 12:57 ` [PATCH v5 1/6] dt-bindings: power: Convert mti,mips-cpc to DT schema Serge Semin
2020-07-14 12:57 ` [PATCH v5 2/6] dt-bindings: interrupt-controller: Convert mti,gic " Serge Semin
2020-07-14 12:57 ` [PATCH v5 3/6] dt-bindings: bus: Add MIPS CDMM controller Serge Semin
2020-07-14 12:57 ` [PATCH v5 4/6] mips: cdmm: Add mti,mips-cdmm dtb node support Serge Semin
2020-07-14 12:57 ` [PATCH v5 5/6] bus: cdmm: Add MIPS R5 arch support Serge Semin
2020-07-14 13:28 ` Arnd Bergmann
2020-07-14 14:15 ` Serge Semin [this message]
2020-07-14 12:57 ` [PATCH v5 6/6] MAINTAINERS: Add maintainers for MIPS core drivers Serge Semin
2020-07-17 4:29 ` Daniel Lezcano
2020-07-17 12:41 ` Serge Semin
2020-07-21 8:30 ` [PATCH v5 0/6] mips: Add DT bindings for MIPS CDMM and MIPS GIC Thomas Bogendoerfer
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