* [PATCH Fixes] MIPS: add missing MSACSR and upper MSA initialization
@ 2020-08-28 8:57 Huang Pei
2020-08-28 15:26 ` WANG Xuerui
0 siblings, 1 reply; 3+ messages in thread
From: Huang Pei @ 2020-08-28 8:57 UTC (permalink / raw)
To: Thomas Bogendoerfer, ambrosehua
Cc: Li Xuefeng, Yang Tiezhu, Gao Juxin, Fuxin Zhang, Huacai Chen, linux-mips
init_fp_ctx just initialize the fp/msa context, and own_fp_inatomic
just restore FCSR and 64bit FP regs from it, but miss MSACSR and upper
MSA regs for MSA, so MSACSR and MSA upper regs's value from previous
task on current cpu can leak into current task and cause unpredictable
behavior when MSA context not initialized.
Signed-off-by: Huang Pei <huangpei@loongson.cn>
---
arch/mips/kernel/traps.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 38aa07ccdbcc..cf788591f091 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1287,6 +1287,18 @@ static int enable_restore_fp_context(int msa)
err = own_fpu_inatomic(1);
if (msa && !err) {
enable_msa();
+ /*
+ * with MSA enabled, userspace can see MSACSR
+ * and MSA regs, but the values in them are from
+ * other task before current task, restore them
+ * from saved fp/msa context
+ */
+ write_msa_csr(current->thread.fpu.msacsr);
+ /*
+ * own_fpu_inatomic(1) just restore low 64bit,
+ * fix the high 64bit
+ */
+ init_msa_upper();
set_thread_flag(TIF_USEDMSA);
set_thread_flag(TIF_MSA_CTX_LIVE);
}
--
2.17.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH Fixes] MIPS: add missing MSACSR and upper MSA initialization
2020-08-28 8:57 [PATCH Fixes] MIPS: add missing MSACSR and upper MSA initialization Huang Pei
@ 2020-08-28 15:26 ` WANG Xuerui
2020-08-31 1:38 ` Huang Pei
0 siblings, 1 reply; 3+ messages in thread
From: WANG Xuerui @ 2020-08-28 15:26 UTC (permalink / raw)
To: Huang Pei, Thomas Bogendoerfer, ambrosehua
Cc: Li Xuefeng, Yang Tiezhu, Gao Juxin, Fuxin Zhang, Huacai Chen, linux-mips
Hi Pei,
On 8/28/20 4:57 PM, Huang Pei wrote:
> init_fp_ctx just initialize the fp/msa context, and own_fp_inatomic
> just restore FCSR and 64bit FP regs from it, but miss MSACSR and upper
> MSA regs for MSA, so MSACSR and MSA upper regs's value from previous
> task on current cpu can leak into current task and cause unpredictable
> behavior when MSA context not initialized.
>
> Signed-off-by: Huang Pei <huangpei@loongson.cn>
Actually I think what Thomas meant by saying "add a Fixes tag" in the
previous thread was "to add a Fixes: tag to refer to the broken commit"
. So perhaps send a v3?
> ---
> arch/mips/kernel/traps.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> index 38aa07ccdbcc..cf788591f091 100644
> --- a/arch/mips/kernel/traps.c
> +++ b/arch/mips/kernel/traps.c
> @@ -1287,6 +1287,18 @@ static int enable_restore_fp_context(int msa)
> err = own_fpu_inatomic(1);
> if (msa && !err) {
> enable_msa();
> + /*
> + * with MSA enabled, userspace can see MSACSR
> + * and MSA regs, but the values in them are from
> + * other task before current task, restore them
> + * from saved fp/msa context
> + */
> + write_msa_csr(current->thread.fpu.msacsr);
> + /*
> + * own_fpu_inatomic(1) just restore low 64bit,
> + * fix the high 64bit
> + */
> + init_msa_upper();
> set_thread_flag(TIF_USEDMSA);
> set_thread_flag(TIF_MSA_CTX_LIVE);
> }
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH Fixes] MIPS: add missing MSACSR and upper MSA initialization
2020-08-28 15:26 ` WANG Xuerui
@ 2020-08-31 1:38 ` Huang Pei
0 siblings, 0 replies; 3+ messages in thread
From: Huang Pei @ 2020-08-31 1:38 UTC (permalink / raw)
To: WANG Xuerui; +Cc: linux-mips
On Fri, Aug 28, 2020 at 11:26:19PM +0800, WANG Xuerui wrote:
> Hi Pei,
>
> On 8/28/20 4:57 PM, Huang Pei wrote:
> > init_fp_ctx just initialize the fp/msa context, and own_fp_inatomic
> > just restore FCSR and 64bit FP regs from it, but miss MSACSR and upper
> > MSA regs for MSA, so MSACSR and MSA upper regs's value from previous
> > task on current cpu can leak into current task and cause unpredictable
> > behavior when MSA context not initialized.
> >
> > Signed-off-by: Huang Pei <huangpei@loongson.cn>
> Actually I think what Thomas meant by saying "add a Fixes tag" in the
> previous thread was "to add a Fixes: tag to refer to the broken commit" . So
> perhaps send a v3?
> > ---
> > arch/mips/kernel/traps.c | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> > index 38aa07ccdbcc..cf788591f091 100644
> > --- a/arch/mips/kernel/traps.c
> > +++ b/arch/mips/kernel/traps.c
> > @@ -1287,6 +1287,18 @@ static int enable_restore_fp_context(int msa)
> > err = own_fpu_inatomic(1);
> > if (msa && !err) {
> > enable_msa();
> > + /*
> > + * with MSA enabled, userspace can see MSACSR
> > + * and MSA regs, but the values in them are from
> > + * other task before current task, restore them
> > + * from saved fp/msa context
> > + */
> > + write_msa_csr(current->thread.fpu.msacsr);
> > + /*
> > + * own_fpu_inatomic(1) just restore low 64bit,
> > + * fix the high 64bit
> > + */
> > + init_msa_upper();
> > set_thread_flag(TIF_USEDMSA);
> > set_thread_flag(TIF_MSA_CTX_LIVE);
> > }
Got it, resend with a tag refering to hte broken commit
^ permalink raw reply [flat|nested] 3+ messages in thread
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