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From: Paul Cercueil <paul@crapouillou.net>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: "Maciej W . Rozycki" <macro@linux-mips.org>,
	Paul Burton <paulburton@kernel.org>,
	Zhou Yanjie <zhouyanjie@wanyeetech.com>,
	od@zcrc.me, linux-kernel@vger.kernel.org,
	linux-mips@vger.kernel.org, Paul Cercueil <paul@crapouillou.net>
Subject: [PATCH v3 02/15] MIPS: cpu-probe: Set Ingenic's writecombine to _CACHE_CACHABLE_WA
Date: Sun,  6 Sep 2020 21:29:22 +0200	[thread overview]
Message-ID: <20200906192935.107086-3-paul@crapouillou.net> (raw)
In-Reply-To: <20200906192935.107086-1-paul@crapouillou.net>

Previously, in cpu_probe_ingenic(), c->writecombine was set to
_CACHE_UNCACHED_ACCELERATED, but this macro was defined differently when
CONFIG_MACH_INGENIC was set. This made it impossible to support multiple
CPUs.

Address this issue by setting c->writecombine to _CACHE_CACHABLE_WA
directly and removing the dependency on CONFIG_MACH_INGENIC.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---

Notes:
    v2-v3: No change

 arch/mips/include/asm/pgtable-bits.h | 5 -----
 arch/mips/kernel/cpu-probe.c         | 3 ++-
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index e26dc41a8a68..2362842ee2b5 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -249,11 +249,6 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 
 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
 
-#elif defined(CONFIG_MACH_INGENIC)
-
-/* Ingenic uses the WA bit to achieve write-combine memory writes */
-#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
-
 #endif
 
 #ifndef _CACHE_CACHABLE_NO_WA
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index e2955f1f6316..a18f3611fa5e 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -2169,8 +2169,9 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 
 	/* XBurst®1 with MXU2.0 SIMD ISA */
 	case PRID_IMP_XBURST_REV2:
+		/* Ingenic uses the WA bit to achieve write-combine memory writes */
+		c->writecombine = _CACHE_CACHABLE_WA;
 		c->cputype = CPU_XBURST;
-		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
 		__cpu_name[cpu] = "Ingenic XBurst";
 		break;
 
-- 
2.28.0


  parent reply	other threads:[~2020-09-06 19:30 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-06 19:29 [PATCH v3 00/15] MIPS: Convert Ingenic to a generic board v3 Paul Cercueil
2020-09-06 19:29 ` [PATCH v3 01/15] MIPS: configs: lb60: Fix defconfig not selecting correct board Paul Cercueil
2020-09-06 19:29 ` Paul Cercueil [this message]
2020-09-06 19:29 ` [PATCH v3 03/15] MIPS: cpu-probe: Mark XBurst CPU as having vtagged caches Paul Cercueil
2020-09-06 19:29 ` [PATCH v3 04/15] MIPS: cpu-probe: ingenic: Fix broken BUG_ON Paul Cercueil
2020-09-06 19:29 ` [PATCH v3 05/15] MIPS: Kconfig: add MIPS_GENERIC_KERNEL symbol Paul Cercueil
2020-09-06 19:29 ` [PATCH v3 06/15] MIPS: generic: Allow boards to set system type Paul Cercueil
2020-09-08 16:27   ` Philippe Mathieu-Daudé
2020-09-06 19:29 ` [PATCH v3 07/15] MIPS: generic: Init command line with fw_init_cmdline() Paul Cercueil
2020-09-06 19:29 ` [PATCH v3 08/15] MIPS: generic: Support booting with built-in or appended DTB Paul Cercueil
2020-09-07  7:54   ` Sergei Shtylyov
2020-09-07 12:39     ` Paul Cercueil
2020-09-06 19:29 ` [PATCH v3 09/15] MIPS: generic: Add support for zboot Paul Cercueil
2020-09-06 19:29 ` [PATCH v3 10/15] MIPS: generic: Increase NR_IRQS to 256 Paul Cercueil
2020-09-07 19:53   ` Thomas Bogendoerfer
2020-09-06 19:29 ` [PATCH v3 11/15] MIPS: generic: Add support for Ingenic SoCs Paul Cercueil
2020-10-12 14:33   ` Guenter Roeck
2020-10-12 14:59     ` Paul Cercueil
2020-10-12 18:26       ` Guenter Roeck
2020-10-12 19:27     ` [PATCH] MIPS: ingenic: Remove CPU_SUPPORTS_HUGEPAGES Paul Cercueil
2020-10-13  9:31       ` Thomas Bogendoerfer
2020-09-06 19:29 ` [PATCH v3 12/15] MIPS: jz4740: Drop all obsolete files Paul Cercueil
2020-09-06 19:29 ` [PATCH v3 13/15] MIPS: jz4740: Rename jz4740 folders to ingenic Paul Cercueil
2020-09-06 19:29 ` [PATCH v3 14/15] MIPS: configs: Regenerate configs of Ingenic boards Paul Cercueil
2020-09-06 19:29 ` [PATCH v3 15/15] MAINTAINERS: Update paths to Ingenic platform code Paul Cercueil
2020-09-18 14:40 ` [PATCH v3 00/15] MIPS: Convert Ingenic to a generic board v3 Thomas Bogendoerfer

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