* [PATCH v3 0/3] Repair Ingenic SoCs L2 cache capacity detection.
@ 2020-09-22 1:24 周琰杰 (Zhou Yanjie)
2020-09-22 1:24 ` [PATCH v3 1/3] dt-bindings: MIPS: Add X2000E based CU2000-Neo 周琰杰 (Zhou Yanjie)
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-09-22 1:24 UTC (permalink / raw)
To: tsbogend, robh+dt, paul, paulburton
Cc: linux-kernel, linux-mips, devicetree, jiaxun.yang, Sergey.Semin,
akpm, rppt, dongsheng.qiu, aric.pzqi, rick.tyliu, yanfei.li,
sernia.zhou, zhenwenjin
1.The X1000E SoC has a 4-way L2 cache with a capacity of 128 KiB.
The current code cannot detect its correctly, which will cause the
CU1000-Neo board using the X1000E SoC to report that it has found
a 5-way 320KiB L2 cache at boot time.
2.The JZ4775 SoC has a 4-way L2 cache with a capacity of 256 KiB.
The current code cannot detect its correctly, which will cause the
Mensa board using the JZ4775 SoC to report that it has found a 5-way
320KiB L2 cache at boot time.
This series of patches is to fix this problem.
v2->v3:
Fix the warning that appears when running checkpatch, add relevant
compatible string.
周琰杰 (Zhou Yanjie) (3):
dt-bindings: MIPS: Add X2000E based CU2000-Neo.
MIPS: Ingenic: Add system type for new Ingenic SoCs.
MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E.
Documentation/devicetree/bindings/mips/ingenic/devices.yaml | 5 +++++
arch/mips/generic/board-ingenic.c | 12 ++++++++++++
arch/mips/include/asm/bootinfo.h | 2 ++
arch/mips/mm/sc-mips.c | 2 ++
4 files changed, 21 insertions(+)
--
2.11.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 1/3] dt-bindings: MIPS: Add X2000E based CU2000-Neo.
2020-09-22 1:24 [PATCH v3 0/3] Repair Ingenic SoCs L2 cache capacity detection 周琰杰 (Zhou Yanjie)
@ 2020-09-22 1:24 ` 周琰杰 (Zhou Yanjie)
2020-09-22 1:24 ` [PATCH v3 2/3] MIPS: Ingenic: Add system type for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-09-22 1:24 UTC (permalink / raw)
To: tsbogend, robh+dt, paul, paulburton
Cc: linux-kernel, linux-mips, devicetree, jiaxun.yang, Sergey.Semin,
akpm, rppt, dongsheng.qiu, aric.pzqi, rick.tyliu, yanfei.li,
sernia.zhou, zhenwenjin
Add bindings for Ingenic X2000E based board, prepare for later dts.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v3:
New patch.
Documentation/devicetree/bindings/mips/ingenic/devices.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/mips/ingenic/devices.yaml b/Documentation/devicetree/bindings/mips/ingenic/devices.yaml
index 83c86cbe4716..dc21b4630c25 100644
--- a/Documentation/devicetree/bindings/mips/ingenic/devices.yaml
+++ b/Documentation/devicetree/bindings/mips/ingenic/devices.yaml
@@ -47,4 +47,9 @@ properties:
items:
- const: yna,cu1830-neo
- const: ingenic,x1830
+
+ - description: YSH & ATIL General Board, CU2000 Module with Neo Backplane
+ items:
+ - const: yna,cu2000-neo
+ - const: ingenic,x2000e
...
--
2.11.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 2/3] MIPS: Ingenic: Add system type for new Ingenic SoCs.
2020-09-22 1:24 [PATCH v3 0/3] Repair Ingenic SoCs L2 cache capacity detection 周琰杰 (Zhou Yanjie)
2020-09-22 1:24 ` [PATCH v3 1/3] dt-bindings: MIPS: Add X2000E based CU2000-Neo 周琰杰 (Zhou Yanjie)
@ 2020-09-22 1:24 ` 周琰杰 (Zhou Yanjie)
2020-09-22 1:24 ` [PATCH v3 3/3] MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E 周琰杰 (Zhou Yanjie)
2020-09-27 9:03 ` [PATCH v3 0/3] Repair Ingenic SoCs L2 cache capacity detection Thomas Bogendoerfer
3 siblings, 0 replies; 5+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-09-22 1:24 UTC (permalink / raw)
To: tsbogend, robh+dt, paul, paulburton
Cc: linux-kernel, linux-mips, devicetree, jiaxun.yang, Sergey.Semin,
akpm, rppt, dongsheng.qiu, aric.pzqi, rick.tyliu, yanfei.li,
sernia.zhou, zhenwenjin
Add JZ4775, X1000E, X2000, and X2000E system type for cat /proc/cpuinfo
to give out JZ4775, X1000E, X2000 and X2000E.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
---
Notes:
v1->v2:
1.Add system type for JZ4775, X2000, and X2000E.
2.Add Paul Cercueil's Reviewed-by.
v2->v3:
No change.
arch/mips/generic/board-ingenic.c | 12 ++++++++++++
arch/mips/include/asm/bootinfo.h | 2 ++
2 files changed, 14 insertions(+)
diff --git a/arch/mips/generic/board-ingenic.c b/arch/mips/generic/board-ingenic.c
index 0d7de8f9713d..0cec0bea13d6 100644
--- a/arch/mips/generic/board-ingenic.c
+++ b/arch/mips/generic/board-ingenic.c
@@ -21,12 +21,20 @@
static __init char *ingenic_get_system_type(unsigned long machtype)
{
switch (machtype) {
+ case MACH_INGENIC_X2000E:
+ return "X2000E";
+ case MACH_INGENIC_X2000:
+ return "X2000";
case MACH_INGENIC_X1830:
return "X1830";
+ case MACH_INGENIC_X1000E:
+ return "X1000E";
case MACH_INGENIC_X1000:
return "X1000";
case MACH_INGENIC_JZ4780:
return "JZ4780";
+ case MACH_INGENIC_JZ4775:
+ return "JZ4775";
case MACH_INGENIC_JZ4770:
return "JZ4770";
case MACH_INGENIC_JZ4725B:
@@ -56,9 +64,13 @@ static const struct of_device_id ingenic_of_match[] __initconst = {
{ .compatible = "ingenic,jz4740", .data = (void *)MACH_INGENIC_JZ4740 },
{ .compatible = "ingenic,jz4725b", .data = (void *)MACH_INGENIC_JZ4725B },
{ .compatible = "ingenic,jz4770", .data = (void *)MACH_INGENIC_JZ4770 },
+ { .compatible = "ingenic,jz4775", .data = (void *)MACH_INGENIC_JZ4775 },
{ .compatible = "ingenic,jz4780", .data = (void *)MACH_INGENIC_JZ4780 },
{ .compatible = "ingenic,x1000", .data = (void *)MACH_INGENIC_X1000 },
+ { .compatible = "ingenic,x1000e", .data = (void *)MACH_INGENIC_X1000E },
{ .compatible = "ingenic,x1830", .data = (void *)MACH_INGENIC_X1830 },
+ { .compatible = "ingenic,x2000", .data = (void *)MACH_INGENIC_X2000 },
+ { .compatible = "ingenic,x2000e", .data = (void *)MACH_INGENIC_X2000E },
{}
};
diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 147c9327ce04..6dd173a22aeb 100644
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -79,8 +79,10 @@ enum ingenic_machine_type {
MACH_INGENIC_JZ4775,
MACH_INGENIC_JZ4780,
MACH_INGENIC_X1000,
+ MACH_INGENIC_X1000E,
MACH_INGENIC_X1830,
MACH_INGENIC_X2000,
+ MACH_INGENIC_X2000E,
};
extern char *system_type;
--
2.11.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v3 3/3] MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E.
2020-09-22 1:24 [PATCH v3 0/3] Repair Ingenic SoCs L2 cache capacity detection 周琰杰 (Zhou Yanjie)
2020-09-22 1:24 ` [PATCH v3 1/3] dt-bindings: MIPS: Add X2000E based CU2000-Neo 周琰杰 (Zhou Yanjie)
2020-09-22 1:24 ` [PATCH v3 2/3] MIPS: Ingenic: Add system type for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
@ 2020-09-22 1:24 ` 周琰杰 (Zhou Yanjie)
2020-09-27 9:03 ` [PATCH v3 0/3] Repair Ingenic SoCs L2 cache capacity detection Thomas Bogendoerfer
3 siblings, 0 replies; 5+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-09-22 1:24 UTC (permalink / raw)
To: tsbogend, robh+dt, paul, paulburton
Cc: linux-kernel, linux-mips, devicetree, jiaxun.yang, Sergey.Semin,
akpm, rppt, dongsheng.qiu, aric.pzqi, rick.tyliu, yanfei.li,
sernia.zhou, zhenwenjin
1.Fix bugs when detecting ways value of JZ4775's L2 cache.
2.Fix bugs when detecting sets value and ways value of X1000E's L2 cache.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
---
Notes:
v1->v2:
1.Add corrections to JZ4775's L2 cache ways parameter.
2.Add Paul Cercueil's Reviewed-by.
v2->v3:
No change.
arch/mips/mm/sc-mips.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 97dc0511e63f..dd0a5becaabd 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -228,6 +228,7 @@ static inline int __init mips_sc_probe(void)
* contradicted by all documentation.
*/
case MACH_INGENIC_JZ4770:
+ case MACH_INGENIC_JZ4775:
c->scache.ways = 4;
break;
@@ -236,6 +237,7 @@ static inline int __init mips_sc_probe(void)
* but that is contradicted by all documentation.
*/
case MACH_INGENIC_X1000:
+ case MACH_INGENIC_X1000E:
c->scache.sets = 256;
c->scache.ways = 4;
break;
--
2.11.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v3 0/3] Repair Ingenic SoCs L2 cache capacity detection.
2020-09-22 1:24 [PATCH v3 0/3] Repair Ingenic SoCs L2 cache capacity detection 周琰杰 (Zhou Yanjie)
` (2 preceding siblings ...)
2020-09-22 1:24 ` [PATCH v3 3/3] MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E 周琰杰 (Zhou Yanjie)
@ 2020-09-27 9:03 ` Thomas Bogendoerfer
3 siblings, 0 replies; 5+ messages in thread
From: Thomas Bogendoerfer @ 2020-09-27 9:03 UTC (permalink / raw)
To: 周琰杰 (Zhou Yanjie)
Cc: robh+dt, paul, paulburton, linux-kernel, linux-mips, devicetree,
jiaxun.yang, Sergey.Semin, akpm, rppt, dongsheng.qiu, aric.pzqi,
rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
On Tue, Sep 22, 2020 at 09:24:41AM +0800, 周琰杰 (Zhou Yanjie) wrote:
> 1.The X1000E SoC has a 4-way L2 cache with a capacity of 128 KiB.
> The current code cannot detect its correctly, which will cause the
> CU1000-Neo board using the X1000E SoC to report that it has found
> a 5-way 320KiB L2 cache at boot time.
> 2.The JZ4775 SoC has a 4-way L2 cache with a capacity of 256 KiB.
> The current code cannot detect its correctly, which will cause the
> Mensa board using the JZ4775 SoC to report that it has found a 5-way
> 320KiB L2 cache at boot time.
>
> This series of patches is to fix this problem.
>
> v2->v3:
> Fix the warning that appears when running checkpatch, add relevant
> compatible string.
>
> 周琰杰 (Zhou Yanjie) (3):
> dt-bindings: MIPS: Add X2000E based CU2000-Neo.
> MIPS: Ingenic: Add system type for new Ingenic SoCs.
> MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E.
>
> Documentation/devicetree/bindings/mips/ingenic/devices.yaml | 5 +++++
> arch/mips/generic/board-ingenic.c | 12 ++++++++++++
> arch/mips/include/asm/bootinfo.h | 2 ++
> arch/mips/mm/sc-mips.c | 2 ++
> 4 files changed, 21 insertions(+)
series applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 5+ messages in thread
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2020-09-22 1:24 [PATCH v3 0/3] Repair Ingenic SoCs L2 cache capacity detection 周琰杰 (Zhou Yanjie)
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2020-09-22 1:24 ` [PATCH v3 2/3] MIPS: Ingenic: Add system type for new Ingenic SoCs 周琰杰 (Zhou Yanjie)
2020-09-22 1:24 ` [PATCH v3 3/3] MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E 周琰杰 (Zhou Yanjie)
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