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From: Mike Kravetz <mike.kravetz@oracle.com>
To: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>,
	Bibo Mao <maobibo@loongson.cn>,
	Andrew Morton <akpm@linux-foundation.org>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Paul Burton <paulburton@kernel.org>,
	Anshuman Khandual <anshuman.khandual@arm.com>,
	Mike Rapoport <rppt@linux.ibm.com>,
	Daniel Silsby <dansilsby@gmail.com>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-mm@kvack.org
Subject: Re: [PATCH 2/3] mm/huge_memory.c: update tlb entry if pmd is changed
Date: Thu, 25 Jun 2020 09:46:06 -0700
Message-ID: <6071df89-1438-1a25-136d-228b8863364e@oracle.com> (raw)
In-Reply-To: <87lfkbl5gz.fsf@linux.ibm.com>

On 6/25/20 5:01 AM, Aneesh Kumar K.V wrote:
> Mike Kravetz <mike.kravetz@oracle.com> writes:
> 
>> On 6/24/20 2:26 AM, Bibo Mao wrote:
>>> When set_pmd_at is called in function do_huge_pmd_anonymous_page,
>>> new tlb entry can be added by software on MIPS platform.
>>>
>>> Here add update_mmu_cache_pmd when pmd entry is set, and
>>> update_mmu_cache_pmd is defined as empty excepts arc/mips platform.
>>> This patch has no negative effect on other platforms except arc/mips
>>> system.
>>
>> I am confused by this comment.  It appears that update_mmu_cache_pmd
>> is defined as non-empty on arc, mips, powerpc and sparc architectures.
>> Am I missing something?
>>
>> If those architectures do provide update_mmu_cache_pmd, then the previous
>> patch and this one now call update_mmu_cache_pmd with the actual faulting
>> address instead of the huge page aligned address.  This was intentional
>> for mips.  However, are there any potential issues on the other architectures?
>> I am no expert in any of those architectures.  arc looks like it could be
>> problematic as update_mmu_cache_pmd calls update_mmu_cache and then
>> operates on (address & PAGE_MASK).  That could now be different.
>>
> 
> Also we added update_mmu_cache_pmd to update a THP entry. That could be
> different from a hugetlb entry on some architectures. If we need to do
> hugetlb equivalent for update_mmu_cache, we should add a different
> function.

I do not know the mips architecture well enough or if the motivation for
this patch was based on THP or hugetlb pages.  However, it will change
the address passed to update_mmu_cache_pmd from huge page aligned to the
actual faulting address.  Will such a change in the passed address impact
the powerpc update_mmu_cache_pmd routine?

-- 
Mike Kravetz

  reply index

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-24  9:26 [PATCH 1/3] mm: set page fault address for update_mmu_cache_pmd Bibo Mao
2020-06-24  9:26 ` [PATCH 2/3] mm/huge_memory.c: update tlb entry if pmd is changed Bibo Mao
2020-06-25  0:30   ` Mike Kravetz
2020-06-25  9:57     ` maobibo
2020-06-25 12:01     ` Aneesh Kumar K.V
2020-06-25 16:46       ` Mike Kravetz [this message]
2020-06-26  8:13         ` Aneesh Kumar K.V
2020-08-07  4:35           ` Andrew Morton
2020-06-24  9:26 ` [PATCH 3/3] MIPS: Do not call flush_tlb_all when setting pmd entry Bibo Mao
2020-06-24 19:49 ` [PATCH 1/3] mm: set page fault address for update_mmu_cache_pmd Andrew Morton
2020-06-30 10:09 ` Kirill A. Shutemov
2020-06-30 10:42   ` maobibo
2020-07-01  2:54     ` maobibo

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