* [PATCH v2] clocksource: Ingenic: Improve the code.
@ 2021-07-30 9:43 周琰杰 (Zhou Yanjie)
2021-07-30 19:00 ` Paul Cercueil
0 siblings, 1 reply; 2+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2021-07-30 9:43 UTC (permalink / raw)
To: daniel.lezcano, tglx
Cc: paul, linux-mips, linux-kernel, dongsheng.qiu, aric.pzqi,
rick.tyliu, sihui.liu, jun.jiang, sernia.zhou
Use "FIELD_GET()" and "FIELD_PREP()" to simplify the code.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v1->v2:
Split "val = (val & ~OSTCCR_PRESCALEx_MASK) | FIELD_PREP(OSTCCR_PRESCALEx_MASK, prescale)"
into "val &= ~OSTCCR_PRESCALEx_MASK" and "val |= FIELD_PREP(OSTCCR_PRESCALEx_MASK, prescale)"
as Paul Cercueil's suggestion.
drivers/clocksource/ingenic-sysost.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/clocksource/ingenic-sysost.c b/drivers/clocksource/ingenic-sysost.c
index a129840..cb6fc2f 100644
--- a/drivers/clocksource/ingenic-sysost.c
+++ b/drivers/clocksource/ingenic-sysost.c
@@ -4,6 +4,7 @@
* Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
*/
+#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
@@ -34,8 +35,6 @@
/* bits within the OSTCCR register */
#define OSTCCR_PRESCALE1_MASK 0x3
#define OSTCCR_PRESCALE2_MASK 0xc
-#define OSTCCR_PRESCALE1_LSB 0
-#define OSTCCR_PRESCALE2_LSB 2
/* bits within the OSTCR register */
#define OSTCR_OST1CLR BIT(0)
@@ -98,7 +97,7 @@ static unsigned long ingenic_ost_percpu_timer_recalc_rate(struct clk_hw *hw,
prescale = readl(ost_clk->ost->base + info->ostccr_reg);
- prescale = (prescale & OSTCCR_PRESCALE1_MASK) >> OSTCCR_PRESCALE1_LSB;
+ prescale = FIELD_GET(OSTCCR_PRESCALE1_MASK, prescale);
return parent_rate >> (prescale * 2);
}
@@ -112,7 +111,7 @@ static unsigned long ingenic_ost_global_timer_recalc_rate(struct clk_hw *hw,
prescale = readl(ost_clk->ost->base + info->ostccr_reg);
- prescale = (prescale & OSTCCR_PRESCALE2_MASK) >> OSTCCR_PRESCALE2_LSB;
+ prescale = FIELD_GET(OSTCCR_PRESCALE2_MASK, prescale);
return parent_rate >> (prescale * 2);
}
@@ -151,7 +150,8 @@ static int ingenic_ost_percpu_timer_set_rate(struct clk_hw *hw, unsigned long re
int val;
val = readl(ost_clk->ost->base + info->ostccr_reg);
- val = (val & ~OSTCCR_PRESCALE1_MASK) | (prescale << OSTCCR_PRESCALE1_LSB);
+ val &= ~OSTCCR_PRESCALE1_MASK;
+ val |= FIELD_PREP(OSTCCR_PRESCALE1_MASK, prescale);
writel(val, ost_clk->ost->base + info->ostccr_reg);
return 0;
@@ -166,7 +166,8 @@ static int ingenic_ost_global_timer_set_rate(struct clk_hw *hw, unsigned long re
int val;
val = readl(ost_clk->ost->base + info->ostccr_reg);
- val = (val & ~OSTCCR_PRESCALE2_MASK) | (prescale << OSTCCR_PRESCALE2_LSB);
+ val &= ~OSTCCR_PRESCALE2_MASK;
+ val |= FIELD_PREP(OSTCCR_PRESCALE2_MASK, prescale);
writel(val, ost_clk->ost->base + info->ostccr_reg);
return 0;
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v2] clocksource: Ingenic: Improve the code.
2021-07-30 9:43 [PATCH v2] clocksource: Ingenic: Improve the code 周琰杰 (Zhou Yanjie)
@ 2021-07-30 19:00 ` Paul Cercueil
0 siblings, 0 replies; 2+ messages in thread
From: Paul Cercueil @ 2021-07-30 19:00 UTC (permalink / raw)
To: 周琰杰
Cc: daniel.lezcano, tglx, linux-mips, linux-kernel, dongsheng.qiu,
aric.pzqi, rick.tyliu, sihui.liu, jun.jiang, sernia.zhou
Hi,
Le ven., juil. 30 2021 at 17:43:08 +0800, 周琰杰 (Zhou Yanjie)
<zhouyanjie@wanyeetech.com> a écrit :
> Use "FIELD_GET()" and "FIELD_PREP()" to simplify the code.
>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Thanks!
-Paul
> ---
>
> Notes:
> v1->v2:
> Split "val = (val & ~OSTCCR_PRESCALEx_MASK) |
> FIELD_PREP(OSTCCR_PRESCALEx_MASK, prescale)"
> into "val &= ~OSTCCR_PRESCALEx_MASK" and "val |=
> FIELD_PREP(OSTCCR_PRESCALEx_MASK, prescale)"
> as Paul Cercueil's suggestion.
>
> drivers/clocksource/ingenic-sysost.c | 13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clocksource/ingenic-sysost.c
> b/drivers/clocksource/ingenic-sysost.c
> index a129840..cb6fc2f 100644
> --- a/drivers/clocksource/ingenic-sysost.c
> +++ b/drivers/clocksource/ingenic-sysost.c
> @@ -4,6 +4,7 @@
> * Copyright (c) 2020 周琰杰 (Zhou Yanjie)
> <zhouyanjie@wanyeetech.com>
> */
>
> +#include <linux/bitfield.h>
> #include <linux/bitops.h>
> #include <linux/clk.h>
> #include <linux/clk-provider.h>
> @@ -34,8 +35,6 @@
> /* bits within the OSTCCR register */
> #define OSTCCR_PRESCALE1_MASK 0x3
> #define OSTCCR_PRESCALE2_MASK 0xc
> -#define OSTCCR_PRESCALE1_LSB 0
> -#define OSTCCR_PRESCALE2_LSB 2
>
> /* bits within the OSTCR register */
> #define OSTCR_OST1CLR BIT(0)
> @@ -98,7 +97,7 @@ static unsigned long
> ingenic_ost_percpu_timer_recalc_rate(struct clk_hw *hw,
>
> prescale = readl(ost_clk->ost->base + info->ostccr_reg);
>
> - prescale = (prescale & OSTCCR_PRESCALE1_MASK) >>
> OSTCCR_PRESCALE1_LSB;
> + prescale = FIELD_GET(OSTCCR_PRESCALE1_MASK, prescale);
>
> return parent_rate >> (prescale * 2);
> }
> @@ -112,7 +111,7 @@ static unsigned long
> ingenic_ost_global_timer_recalc_rate(struct clk_hw *hw,
>
> prescale = readl(ost_clk->ost->base + info->ostccr_reg);
>
> - prescale = (prescale & OSTCCR_PRESCALE2_MASK) >>
> OSTCCR_PRESCALE2_LSB;
> + prescale = FIELD_GET(OSTCCR_PRESCALE2_MASK, prescale);
>
> return parent_rate >> (prescale * 2);
> }
> @@ -151,7 +150,8 @@ static int
> ingenic_ost_percpu_timer_set_rate(struct clk_hw *hw, unsigned long re
> int val;
>
> val = readl(ost_clk->ost->base + info->ostccr_reg);
> - val = (val & ~OSTCCR_PRESCALE1_MASK) | (prescale <<
> OSTCCR_PRESCALE1_LSB);
> + val &= ~OSTCCR_PRESCALE1_MASK;
> + val |= FIELD_PREP(OSTCCR_PRESCALE1_MASK, prescale);
> writel(val, ost_clk->ost->base + info->ostccr_reg);
>
> return 0;
> @@ -166,7 +166,8 @@ static int
> ingenic_ost_global_timer_set_rate(struct clk_hw *hw, unsigned long re
> int val;
>
> val = readl(ost_clk->ost->base + info->ostccr_reg);
> - val = (val & ~OSTCCR_PRESCALE2_MASK) | (prescale <<
> OSTCCR_PRESCALE2_LSB);
> + val &= ~OSTCCR_PRESCALE2_MASK;
> + val |= FIELD_PREP(OSTCCR_PRESCALE2_MASK, prescale);
> writel(val, ost_clk->ost->base + info->ostccr_reg);
>
> return 0;
> --
> 2.7.4
>
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2021-07-30 19:00 ` Paul Cercueil
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