* Question about utilizing more than one MIPS shadow register set
@ 2021-12-24 11:31 Hakurei Reimu
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From: Hakurei Reimu @ 2021-12-24 11:31 UTC (permalink / raw)
To: linux-mips
Hello. I examined a lot of existing MIPS related code in mainline
kernel and it appears that the kernel is using a shared interrupt
handler and at most one shadow register set when handling interrupts.
I'm currently trying to get Linux running properly on the Microchip
PIC32MZ platform, and it has 8 shadow register sets. I want to make
use of all of them by using multiple interrupt handlers. Is this
possible?
Regards.
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