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From: Zhongwu Zhu <zzhu@wavecomp.com>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	Tommy Jin <tjin@wavecomp.com>
Cc: "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>
Subject: 答复: [EXTERNAL]Re: [PATCH] MIPS64: add KASAN support
Date: Thu, 5 Sep 2019 03:17:56 +0000	[thread overview]
Message-ID: <CY4PR22MB0405AB0E7E26CFF4B3E9800FBCBB0@CY4PR22MB0405.namprd22.prod.outlook.com> (raw)
In-Reply-To: <20190829113320.GB9113@alpha.franken.de>

Hi Thomas,
	Tommy and me are responsible for mips KASAN issue. Thank you for your comments.
	We didn't consider cachable non coherent (0x98) and cachable exclusive (0xa0) mainly because we had not seen them be used. Do you know in which case this two segment address will be applied/accessed?
	but if these two segments are really needed, we can add it to our code. And correspondingly the KASAN address space need to be extend.(from 512G to 1024G, that is change the PGD_ORDER from 1 to 2).
BR
Zhongwu

-----邮件原件-----
发件人: Thomas Bogendoerfer <tsbogend@alpha.franken.de> 
发送时间: 2019年8月29日 19:33
收件人: Tommy Jin <tjin@wavecomp.com>
抄送: linux-mips@vger.kernel.org; Zhongwu Zhu <zzhu@wavecomp.com>
主题: [EXTERNAL]Re: [PATCH] MIPS64: add KASAN support

On Tue, Aug 27, 2019 at 08:28:38AM +0000, Tommy Jin wrote:
> +/* 64-bit segment value. */
> +#define XKPHYS_CACHE_SEG	(0xa8)

that's just cachable coherent exclusive on write, what about cachable non coherent (0x98) and cachable exclusive (0xa0) ?

Thomas.

--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

      reply	other threads:[~2019-09-05  3:18 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-27  8:28 [PATCH] MIPS64: add KASAN support Tommy Jin
2019-08-29 11:33 ` Thomas Bogendoerfer
2019-09-05  3:17   ` Zhongwu Zhu [this message]

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