From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Tommy Jin <tjin@wavecomp.com>
Cc: "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
Zhongwu Zhu <zzhu@wavecomp.com>
Subject: Re: [PATCH] MIPS64: add KASAN support
Date: Thu, 29 Aug 2019 13:33:20 +0200 [thread overview]
Message-ID: <20190829113320.GB9113@alpha.franken.de> (raw)
In-Reply-To: <1566894474-31011-1-git-send-email-tjin@wavecomp.com>
On Tue, Aug 27, 2019 at 08:28:38AM +0000, Tommy Jin wrote:
> +/* 64-bit segment value. */
> +#define XKPHYS_CACHE_SEG (0xa8)
that's just cachable coherent exclusive on write, what about
cachable non coherent (0x98) and cachable exclusive (0xa0) ?
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
next prev parent reply other threads:[~2019-08-29 11:38 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-27 8:28 [PATCH] MIPS64: add KASAN support Tommy Jin
2019-08-29 11:33 ` Thomas Bogendoerfer [this message]
2019-09-05 3:17 ` 答复: [EXTERNAL]Re: " Zhongwu Zhu
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