Re: [PATCH 1/2] MIPS: Loongson, add sync before target of branch between llsc

From: Yunqiang Su <ysu@wavecomp.com>
To: huangpei <huangpei@loongson.cn>
Cc: 徐成华 <xuchenghua@loongson.cn>,
	"Paul Burton" <pburton@wavecomp.com>,
	"Paul Burton" <pburton@wavecomp.com>,
	"linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
	"chenhc@lemote.com" <chenhc@lemote.com>,
	"zhangfx@lemote.com" <zhangfx@lemote.com>,
	"wuzhangjin@gmail.com" <wuzhangjin@gmail.com>,
	"linux-mips@linux-mips.org" <linux-mips@linux-mips.org>
Subject: Re: [PATCH 1/2] MIPS: Loongson, add sync before target of branch between llsc
Date: Sat, 12 Jan 2019 03:41:56 +0000	[thread overview]
Message-ID: <D6CAABA8-132C-4BDB-AFE0-5E7D782D5142@wavecomp.com> (raw)
In-Reply-To: <20190112112518.4cc0b1d7@ambrosehua-ThinkPad-X201s>

>+#define __LS3A_WAR_LLSC		"	.set mips64r2\nsynci 0\n.set mips0\n"
>+#define __ls3a_war_llsc()	__asm__ __volatile__("synci 0" : : :"memory”)

看起来这个只用于1000，所以我觉得名字应该是 __ls3x1k 或者类似的
俩下划线需要么？

> smp_llsc_mb in cmpxchg.h is enought
enought拼写错了

-		__WEAK_LLSC_MB
 		"3:							\n"
+		__WEAK_LLSC_MB

这里可能会影响其他CPU的性能？


 #define TX49XX_ICACHE_INDEX_INV_WAR	0
 #define ICACHE_REFILLS_WORKAROUND_WAR	0
 #define R10000_LLSC_WAR			0
+#define LOONGSON_LLSC_WAR		0
 #define MIPS34K_MISSED_ITLB_WAR		0

这个应该要搞个CONFIG_啥啥啥 ？毕竟以后的芯片很可能没这问题了。


> 在 2019年1月12日，上午11:25，huangpei <huangpei@loongson.cn> 写道：
> 
> hi, this is the patch for ll/sc bug in Loongson3 based on Linux-4.20
> (8fe28cb58bcb235034b64cbbb7550a8a43fd88be)
> 
> +. it cover all loongson3 CPU;
> 
> +. to fix the ll/sc bug *sufficiently and exactly*, this patch shows
> how many places need to touch
> 
> +. it is built ok for on Loongson3 and Cavium/Octeon, old version is
> tested in high pressure test
> 
> 
> On Fri, 11 Jan 2019 20:40:49 +0800 (GMT+08:00)
> 徐成华 <xuchenghua@loongson.cn> wrote:
> 
>> Hi Paul Burton,
>> 
>> For Loongson 3A1000 and 3A3000, when a memory access instruction
>> (load, store, or prefetch)'s executing occurs between the execution
>> of LL and SC, the success or failure of SC is not predictable.
>> Although programmer would not insert memory access instructions
>> between LL and SC, the memory instructions before LL in
>> program-order, may dynamically executed between the execution of
>> LL/SC, so a memory fence(SYNC) is needed before LL/LLD to avoid this
>> situation.
>> 
>> Since 3A3000, we improved our hardware design to handle this case.
>> But we later deduce a rarely circumstance that some speculatively
>> executed memory instructions due to branch misprediction between
>> LL/SC still fall into the above case, so a memory fence(SYNC) at
>> branch-target(if its target is not between LL/SC) is needed for
>> 3A1000 and 3A3000.
>> 
>> Our processor is continually evolving and we aim to to remove all
>> these workaround-SYNCs around LL/SC for new-come processor. 
>> 
>> 北京市海淀区中关村环保科技示范园龙芯产业园2号楼 100095电话: +86 (10)
>> 62546668传真: +86 (10)
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> <0001-loongson64-add-helper-for-ll-sc-bugfix-in-loongson3.patch><0002-loongson64-fix-ll-sc-bug-of-loongson3-in-inline-asm.patch><0003-loongson64-fix-ll-sc-bug-of-Loongson-3-in-handle_tlb.patch>