From: Keith Busch <keith.busch@intel.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org,
linux-mm@kvack.org,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Rafael Wysocki <rafael@kernel.org>,
Dave Hansen <dave.hansen@intel.com>,
Dan Williams <dan.j.williams@intel.com>
Subject: Re: [PATCH 4/7] node: Add memory caching attributes
Date: Mon, 19 Nov 2018 16:06:00 -0700 [thread overview]
Message-ID: <20181119230600.GC26707@localhost.localdomain> (raw)
In-Reply-To: <91698cef-cdcd-5143-884f-3da5536e156f@arm.com>
On Mon, Nov 19, 2018 at 09:44:00AM +0530, Anshuman Khandual wrote:
> On 11/15/2018 04:19 AM, Keith Busch wrote:
> > System memory may have side caches to help improve access speed. While
> > the system provided cache is transparent to the software accessing
> > these memory ranges, applications can optimize their own access based
> > on cache attributes.
>
> Cache is not a separate memory attribute. It impacts how the real attributes
> like bandwidth, latency e.g which are already captured in the previous patch.
> What is the purpose of adding this as a separate attribute ? Can you explain
> how this is going to help the user space apart from the hints it has already
> received with bandwidth, latency etc properties.
I am not sure I understand the question here. Access bandwidth and latency
are entirely attributes different than what this patch provides. If the
system side-caches memory, the associativity, line size, and total size
can optionally be used by software to improve performance.
> > In preparation for such systems, provide a new API for the kernel to
> > register these memory side caches under the memory node that provides it.
>
> Under target memory node interface /sys/devices/system/node/nodeY/target* ?
Yes.
> >
> > The kernel's sysfs representation is modeled from the cpu cacheinfo
> > attributes, as seen from /sys/devices/system/cpu/cpuX/cache/. Unlike CPU
> > cacheinfo, though, a higher node's memory cache level is nearer to the
> > CPU, while lower levels are closer to the backing memory. Also unlike
> > CPU cache, the system handles flushing any dirty cached memory to the
> > last level the memory on a power failure if the range is persistent.
>
> Lets assume that a CPU has got four levels of caches L1, L2, L3, L4 before
> reaching memory. L4 is the backing cache for the memory
I don't quite understand this question either. The cache doesn't back
the memory; the system side caches access to memory.
> and L1-L3 is from
> CPU till the system bus. Hence some of them will be represented as CPU
> caches and some of them will be represented as memory caches ?
>
> /sys/devices/system/cpu/cpuX/cache/ --> L1, L2, L3
> /sys/devices/system/node/nodeY/target --> L4
>
> L4 will be listed even if the node is memory only ?
The system provided memory side caches are independent of the
CPU. I'm just providing the CPU caches as a more familiar example to
compare/contrast system memory cache attributes.
next prev parent reply other threads:[~2018-11-19 23:09 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-14 22:49 [PATCH 1/7] node: Link memory nodes to their compute nodes Keith Busch
2018-11-14 22:49 ` [PATCH 2/7] node: Add heterogenous memory performance Keith Busch
2018-11-19 3:35 ` Anshuman Khandual
2018-11-19 15:46 ` Keith Busch
2018-11-22 13:22 ` Anshuman Khandual
2018-11-27 7:00 ` Dan Williams
2018-11-27 17:42 ` Dan Williams
2018-11-27 17:44 ` Keith Busch
2018-11-14 22:49 ` [PATCH 3/7] doc/vm: New documentation for " Keith Busch
2018-11-15 12:59 ` Jonathan Cameron
2018-12-10 16:12 ` Dan Williams
2018-11-20 13:51 ` Mike Rapoport
2018-11-20 15:31 ` Keith Busch
2018-11-14 22:49 ` [PATCH 4/7] node: Add memory caching attributes Keith Busch
2018-11-15 0:40 ` Dave Hansen
2018-11-19 4:14 ` Anshuman Khandual
2018-11-19 23:06 ` Keith Busch [this message]
2018-11-22 13:29 ` Anshuman Khandual
2018-11-26 15:14 ` Keith Busch
2018-11-26 19:06 ` Greg Kroah-Hartman
2018-11-26 19:53 ` Keith Busch
2018-11-26 19:06 ` Greg Kroah-Hartman
2018-11-14 22:49 ` [PATCH 5/7] doc/vm: New documentation for memory cache Keith Busch
2018-11-15 0:41 ` Dave Hansen
2018-11-15 13:16 ` Jonathan Cameron
2018-11-20 13:53 ` Mike Rapoport
2018-11-14 22:49 ` [PATCH 6/7] acpi: Create subtable parsing infrastructure Keith Busch
2018-11-19 9:58 ` Rafael J. Wysocki
2018-11-19 18:36 ` Keith Busch
2018-11-14 22:49 ` [PATCH 7/7] acpi/hmat: Parse and report heterogeneous memory Keith Busch
2018-11-15 13:57 ` [PATCH 1/7] node: Link memory nodes to their compute nodes Matthew Wilcox
2018-11-15 14:59 ` Keith Busch
2018-11-15 17:50 ` Dan Williams
2018-11-19 3:04 ` Anshuman Khandual
2018-11-15 20:36 ` Matthew Wilcox
2018-11-16 18:32 ` Keith Busch
2018-11-19 3:15 ` Anshuman Khandual
2018-11-19 15:49 ` Keith Busch
2018-12-04 15:43 ` Aneesh Kumar K.V
2018-12-04 16:54 ` Keith Busch
2018-11-16 22:55 ` Dan Williams
2018-11-19 2:52 ` Anshuman Khandual
2018-11-19 2:46 ` Anshuman Khandual
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