From: Zhenyu Ye <yezhenyu2@huawei.com>
To: <will@kernel.org>, <mark.rutland@arm.com>,
<catalin.marinas@arm.com>, <aneesh.kumar@linux.ibm.com>,
<akpm@linux-foundation.org>, <npiggin@gmail.com>,
<peterz@infradead.org>, <arnd@arndb.de>, <rostedt@goodmis.org>,
<maz@kernel.org>, <suzuki.poulose@arm.com>, <tglx@linutronix.de>,
<yuzhao@google.com>, <Dave.Martin@arm.com>,
<steven.price@arm.com>, <broonie@kernel.org>,
<guohanjun@huawei.com>
Cc: <yezhenyu2@huawei.com>, <linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-arch@vger.kernel.org>,
<linux-mm@kvack.org>, <arm@kernel.org>, <xiexiangyou@huawei.com>,
<prime.zeng@hisilicon.com>, <zhangshaokun@hisilicon.com>
Subject: [RFC PATCH v4 5/6] arm64: tlb: Use translation level hint in vm_flags
Date: Tue, 24 Mar 2020 21:45:33 +0800 [thread overview]
Message-ID: <20200324134534.1570-6-yezhenyu2@huawei.com> (raw)
In-Reply-To: <20200324134534.1570-1-yezhenyu2@huawei.com>
This patch used the VM_LEVEL flags in vma->vm_flags to set the
TTL field in tlbi instruction.
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
---
arch/arm64/include/asm/mmu.h | 2 ++
arch/arm64/include/asm/tlbflush.h | 14 ++++++++------
arch/arm64/mm/mmu.c | 14 ++++++++++++++
3 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h
index d79ce6df9e12..a8b8824a7405 100644
--- a/arch/arm64/include/asm/mmu.h
+++ b/arch/arm64/include/asm/mmu.h
@@ -86,6 +86,8 @@ extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys,
extern void *fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t prot);
extern void mark_linear_text_alias_ro(void);
extern bool kaslr_requires_kpti(void);
+extern unsigned int get_vma_level(struct vm_area_struct *vma);
+
#define INIT_MM_CONTEXT(name) \
.pgd = init_pg_dir,
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index d141c080e494..93bb09fdfafd 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -218,10 +218,11 @@ static inline void flush_tlb_page_nosync(struct vm_area_struct *vma,
unsigned long uaddr)
{
unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm));
+ unsigned int level = get_vma_level(vma);
dsb(ishst);
- __tlbi_level(vale1is, addr, 0);
- __tlbi_user_level(vale1is, addr, 0);
+ __tlbi_level(vale1is, addr, level);
+ __tlbi_user_level(vale1is, addr, level);
}
static inline void flush_tlb_page(struct vm_area_struct *vma,
@@ -242,6 +243,7 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma,
unsigned long stride, bool last_level)
{
unsigned long asid = ASID(vma->vm_mm);
+ unsigned int level = get_vma_level(vma);
unsigned long addr;
start = round_down(start, stride);
@@ -261,11 +263,11 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma,
dsb(ishst);
for (addr = start; addr < end; addr += stride) {
if (last_level) {
- __tlbi_level(vale1is, addr, 0);
- __tlbi_user_level(vale1is, addr, 0);
+ __tlbi_level(vale1is, addr, level);
+ __tlbi_user_level(vale1is, addr, level);
} else {
- __tlbi_level(vae1is, addr, 0);
- __tlbi_user_level(vae1is, addr, 0);
+ __tlbi_level(vae1is, addr, level);
+ __tlbi_user_level(vae1is, addr, level);
}
}
dsb(ish);
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 128f70852bf3..e6a1221cd86b 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -60,6 +60,20 @@ static pud_t bm_pud[PTRS_PER_PUD] __page_aligned_bss __maybe_unused;
static DEFINE_SPINLOCK(swapper_pgdir_lock);
+inline unsigned int get_vma_level(struct vm_area_struct *vma)
+{
+ unsigned int level = 0;
+ if (vma->vm_flags & VM_LEVEL_PUD)
+ level = 1;
+ else if (vma->vm_flags & VM_LEVEL_PMD)
+ level = 2;
+ else if (vma->vm_flags & VM_LEVEL_PTE)
+ level = 3;
+
+ vma->vm_flags &= ~(VM_LEVEL_PUD | VM_LEVEL_PMD | VM_LEVEL_PTE);
+ return level;
+}
+
void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd)
{
pgd_t *fixmap_pgdp;
--
2.19.1
next prev parent reply other threads:[~2020-03-24 13:46 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-24 13:45 [RFC PATCH v4 0/6] arm64: tlb: add support for TTL feature Zhenyu Ye
2020-03-24 13:45 ` [RFC PATCH v4 1/6] arm64: Detect the ARMv8.4 " Zhenyu Ye
2020-03-24 13:45 ` [RFC PATCH v4 2/6] arm64: Add level-hinted TLB invalidation helper Zhenyu Ye
2020-03-24 13:45 ` [RFC PATCH v4 3/6] arm64: Add level-hinted TLB invalidation helper to tlbi_user Zhenyu Ye
2020-03-24 14:19 ` Marc Zyngier
2020-03-25 2:47 ` Zhenyu Ye
2020-03-24 13:45 ` [RFC PATCH v4 4/6] mm: Add page table level flags to vm_flags Zhenyu Ye
2020-03-24 18:44 ` Steven Rostedt
2020-03-25 2:10 ` yezhenyu (A)
2020-03-24 13:45 ` Zhenyu Ye [this message]
2020-03-24 14:45 ` [RFC PATCH v4 5/6] arm64: tlb: Use translation level hint in vm_flags Marc Zyngier
2020-03-25 8:00 ` Zhenyu Ye
2020-03-25 14:13 ` Marc Zyngier
2020-03-26 7:11 ` Zhenyu Ye
2020-03-24 13:45 ` [RFC PATCH v4 6/6] mm: Set VM_LEVEL flags in some tlb_flush functions Zhenyu Ye
2020-03-24 15:01 ` [RFC PATCH v4 0/6] arm64: tlb: add support for TTL feature Peter Zijlstra
2020-03-25 4:49 ` Zhenyu Ye
2020-03-25 13:32 ` Peter Zijlstra
2020-03-26 7:15 ` Zhenyu Ye
2020-03-25 16:15 ` James Morse
2020-03-25 16:41 ` Peter Zijlstra
2020-03-26 6:45 ` Zhenyu Ye
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