Re: [PATCH v4 15/36] microblaze: Implement the new page table range API

From: Mike Rapoport <rppt@kernel.org>
To: "Matthew Wilcox (Oracle)" <willy@infradead.org>
Cc: linux-arch@vger.kernel.org, linux-mm@kvack.org,
	linux-kernel@vger.kernel.org, Michal Simek <monstr@monstr.eu>
Subject: Re: [PATCH v4 15/36] microblaze: Implement the new page table range API
Date: Wed, 15 Mar 2023 12:07:50 +0200	[thread overview]
Message-ID: <ZBGY9pn2jGiCUl8f@kernel.org> (raw)
In-Reply-To: <20230315051444.3229621-16-willy@infradead.org>

On Wed, Mar 15, 2023 at 05:14:23AM +0000, Matthew Wilcox (Oracle) wrote:
> Rename PFN_SHIFT_OFFSET to PTE_PFN_SHIFT.  Change the calling
> convention for set_pte() to be the same as other architectures.  Add
> update_mmu_cache_range(), flush_icache_pages() and flush_dcache_folio().
> 
> Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org>
> Cc: Michal Simek <monstr@monstr.eu>

Acked-by: Mike Rapoport (IBM) <rppt@kernel.org>

> ---
>  arch/microblaze/include/asm/cacheflush.h |  8 ++++++++
>  arch/microblaze/include/asm/pgtable.h    | 15 ++++-----------
>  arch/microblaze/include/asm/tlbflush.h   |  4 +++-
>  3 files changed, 15 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/microblaze/include/asm/cacheflush.h b/arch/microblaze/include/asm/cacheflush.h
> index 39f8fb6768d8..e6641ff98cb3 100644
> --- a/arch/microblaze/include/asm/cacheflush.h
> +++ b/arch/microblaze/include/asm/cacheflush.h
> @@ -74,6 +74,14 @@ do { \
>  	flush_dcache_range((unsigned) (addr), (unsigned) (addr) + PAGE_SIZE); \
>  } while (0);
>  
> +static void flush_dcache_folio(struct folio *folio)
> +{
> +	unsigned long addr = folio_pfn(folio) << PAGE_SHIFT;
> +
> +	flush_dcache_range(addr, addr + folio_size(folio));
> +}
> +#define flush_dcache_folio flush_dcache_folio
> +
>  #define flush_cache_page(vma, vmaddr, pfn) \
>  	flush_dcache_range(pfn << PAGE_SHIFT, (pfn << PAGE_SHIFT) + PAGE_SIZE);
>  
> diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
> index d1b8272abcd9..19fcd7f8517e 100644
> --- a/arch/microblaze/include/asm/pgtable.h
> +++ b/arch/microblaze/include/asm/pgtable.h
> @@ -230,12 +230,12 @@ extern unsigned long empty_zero_page[1024];
>  
>  #define pte_page(x)		(mem_map + (unsigned long) \
>  				((pte_val(x) - memory_start) >> PAGE_SHIFT))
> -#define PFN_SHIFT_OFFSET	(PAGE_SHIFT)
> +#define PTE_PFN_SHIFT		PAGE_SHIFT
>  
> -#define pte_pfn(x)		(pte_val(x) >> PFN_SHIFT_OFFSET)
> +#define pte_pfn(x)		(pte_val(x) >> PTE_PFN_SHIFT)
>  
>  #define pfn_pte(pfn, prot) \
> -	__pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) | pgprot_val(prot))
> +	__pte(((pte_basic_t)(pfn) << PTE_PFN_SHIFT) | pgprot_val(prot))
>  
>  #ifndef __ASSEMBLY__
>  /*
> @@ -330,14 +330,7 @@ static inline unsigned long pte_update(pte_t *p, unsigned long clr,
>  /*
>   * set_pte stores a linux PTE into the linux page table.
>   */
> -static inline void set_pte(struct mm_struct *mm, unsigned long addr,
> -		pte_t *ptep, pte_t pte)
> -{
> -	*ptep = pte;
> -}
> -
> -static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
> -		pte_t *ptep, pte_t pte)
> +static inline void set_pte(pte_t *ptep, pte_t pte)
>  {
>  	*ptep = pte;
>  }
> diff --git a/arch/microblaze/include/asm/tlbflush.h b/arch/microblaze/include/asm/tlbflush.h
> index 2038168ed128..1b179e5e9062 100644
> --- a/arch/microblaze/include/asm/tlbflush.h
> +++ b/arch/microblaze/include/asm/tlbflush.h
> @@ -33,7 +33,9 @@ static inline void local_flush_tlb_range(struct vm_area_struct *vma,
>  
>  #define flush_tlb_kernel_range(start, end)	do { } while (0)
>  
> -#define update_mmu_cache(vma, addr, ptep)	do { } while (0)
> +#define update_mmu_cache_range(vma, addr, ptep, nr)	do { } while (0)
> +#define update_mmu_cache(vma, addr, pte) \
> +	update_mmu_cache_range(vma, addr, ptep, 1)
>  
>  #define flush_tlb_all local_flush_tlb_all
>  #define flush_tlb_mm local_flush_tlb_mm
> -- 
> 2.39.2
> 
> 

-- 
Sincerely yours,
Mike.