Re: [PATCH v24 04/30] x86/cpufeatures: Introduce X86_FEATURE_CET and setup functions

["Yu, Yu-cheng" <yu-cheng.yu@intel.com>]

On 4/9/2021 3:12 AM, Borislav Petkov wrote:
> On Thu, Apr 01, 2021 at 03:10:38PM -0700, Yu-cheng Yu wrote:
>> Introduce a software-defined X86_FEATURE_CET, which indicates either Shadow
>> Stack or Indirect Branch Tracking (or both) is present.  Also introduce
>> related cpu init/setup functions.
>>
>> Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
>> Cc: Kees Cook <keescook@chromium.org>
>> ---
>> v24:
>> - Update #ifdef placement to reflect Kconfig changes of splitting shadow stack and ibt.
>>
>>   arch/x86/include/asm/cpufeatures.h          |  2 +-
>>   arch/x86/include/asm/disabled-features.h    |  9 ++++++++-
>>   arch/x86/include/uapi/asm/processor-flags.h |  2 ++
>>   arch/x86/kernel/cpu/common.c                | 14 ++++++++++++++
>>   arch/x86/kernel/cpu/intel.c                 |  3 +++
>>   5 files changed, 28 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
>> index bf861fc89fef..d771e62677de 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -108,7 +108,7 @@
>>   #define X86_FEATURE_EXTD_APICID		( 3*32+26) /* Extended APICID (8 bits) */
>>   #define X86_FEATURE_AMD_DCM		( 3*32+27) /* AMD multi-node processor */
>>   #define X86_FEATURE_APERFMPERF		( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */
>> -/* free					( 3*32+29) */
>> +#define X86_FEATURE_CET			( 3*32+29) /* Control-flow enforcement */
> 
> Right, I know we talked about having this synthetic flag but now that we
> are moving to CONFIG_X86_SHADOW_STACK and separate SHSTK and IBT feature
> bits, that synthetic flag is not needed anymore.
> 
> For the cases where you wanna test whether any of the two are present,
> we're probably better off adding a x86_cet_enabled() helper which tests
> SHSTK and IBT bits.
> 

Recall we had complicated code for the XSAVES features detection in 
xstate.c.  Dave Hansen proposed the solution and then the whole thing 
becomes simple.  Because of this flag, even when only the shadow stack 
is available, the code handles it nicely.

> I haven't gone through the whole thing yet but depending on the context
> and the fact that AMD doesn't support IBT, that helper might need some
> tweaking too. I'll see.
> 
>>   #define X86_FEATURE_NONSTOP_TSC_S3	( 3*32+30) /* TSC doesn't stop in S3 state */
>>   #define X86_FEATURE_TSC_KNOWN_FREQ	( 3*32+31) /* TSC has known frequency */
>>   
>> diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h
>> index e5c6ed9373e8..018cd7acd3e9 100644
>> --- a/arch/x86/include/asm/disabled-features.h
>> +++ b/arch/x86/include/asm/disabled-features.h
>> @@ -74,13 +74,20 @@
>>   #define DISABLE_SHSTK	(1 << (X86_FEATURE_SHSTK & 31))
>>   #endif
>>   
>> +#ifdef CONFIG_X86_CET
> 
> And you don't need that config item either - AFAICT, you can use
> CONFIG_X86_SHADOW_STACK everywhere.
> 
> Which would simplify that config space.

Would this equal to only CONFIG_X86_CET (one Kconfig option)?  In fact, 
when you proposed only CONFIG_X86_CET, things became much simpler.
Practically, IBT is not much in terms of code size.  Since we have 
already separated the two, why don't we leave it as-is.  When people 
start using it more, there will be more feedback, and we can decide if 
one Kconfig is better?

Thanks,
Yu-cheng