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* [RFC PATCH] mmc: sdhci: switch from programmable clock mode to divided one if needed
@ 2014-10-07  8:11 Ludovic Desroches
  2014-11-04  8:06 ` Ulf Hansson
  0 siblings, 1 reply; 3+ messages in thread
From: Ludovic Desroches @ 2014-10-07  8:11 UTC (permalink / raw)
  To: linux-mmc; +Cc: chris, ulf.hansson, nicolas.ferre, Ludovic Desroches

In programmable mode, if the clock frequency is too high, the divider
can be too small to meet the clock frequency requirement especially to
init the SD card. In this case, switch to the divided clock mode.

Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
---

Hi all,

I would like to know if this patch can be accepted. Use case, I have a base
clock at 12 MHz, M is 40. So in programmable mode, using the greater divider,
minimum clock frequency will be higher than 400 KHz so it could cause issues to
init the card.

Thanks for your feedback.

Ludovic

 drivers/mmc/host/sdhci.c | 29 ++++++++++++++++++++---------
 1 file changed, 20 insertions(+), 9 deletions(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index df0e7e1..70d4c18 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1126,6 +1126,7 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 	int real_div = div, clk_mul = 1;
 	u16 clk = 0;
 	unsigned long timeout;
+	bool switch_base_clk = false;
 
 	host->mmc->actual_clock = 0;
 
@@ -1163,15 +1164,25 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 					<= clock)
 					break;
 			}
-			/*
-			 * Set Programmable Clock Mode in the Clock
-			 * Control register.
-			 */
-			clk = SDHCI_PROG_CLOCK_MODE;
-			real_div = div;
-			clk_mul = host->clk_mul;
-			div--;
-		} else {
+			if ((host->max_clk * host->clk_mul / div) <= clock) {
+				/*
+				 * Set Programmable Clock Mode in the Clock
+				 * Control register.
+				 */
+				clk = SDHCI_PROG_CLOCK_MODE;
+				real_div = div;
+				clk_mul = host->clk_mul;
+				div--;
+			} else {
+				/*
+				 * Divisor can be too small to reach clock
+				 * speed requirement. Then use the base clock.
+				 */
+				switch_base_clk = true;
+			}
+		}
+
+		if (!host->clk_mul || switch_base_clk) {
 			/* Version 3.00 divisors must be a multiple of 2. */
 			if (host->max_clk <= clock)
 				div = 1;
-- 
2.0.3


^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [RFC PATCH] mmc: sdhci: switch from programmable clock mode to divided one if needed
  2014-10-07  8:11 [RFC PATCH] mmc: sdhci: switch from programmable clock mode to divided one if needed Ludovic Desroches
@ 2014-11-04  8:06 ` Ulf Hansson
  2014-11-27 13:39   ` Ludovic Desroches
  0 siblings, 1 reply; 3+ messages in thread
From: Ulf Hansson @ 2014-11-04  8:06 UTC (permalink / raw)
  To: linux-mmc; +Cc: Chris Ball, Nicolas Ferre, Ludovic Desroches

On 7 October 2014 10:11, Ludovic Desroches <ludovic.desroches@atmel.com> wrote:
> In programmable mode, if the clock frequency is too high, the divider
> can be too small to meet the clock frequency requirement especially to
> init the SD card. In this case, switch to the divided clock mode.
>
> Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
> ---
>
> Hi all,
>
> I would like to know if this patch can be accepted. Use case, I have a base
> clock at 12 MHz, M is 40. So in programmable mode, using the greater divider,
> minimum clock frequency will be higher than 400 KHz so it could cause issues to
> init the card.
>
> Thanks for your feedback.
>
> Ludovic

It would be nice if some of the senior sdhci developers could help out
review patches likes this.

It touches the core of sdhci, thus affecting many of the sdhci drivers.

Anybody?

Kind regards
Uffe

>
>  drivers/mmc/host/sdhci.c | 29 ++++++++++++++++++++---------
>  1 file changed, 20 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index df0e7e1..70d4c18 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1126,6 +1126,7 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
>         int real_div = div, clk_mul = 1;
>         u16 clk = 0;
>         unsigned long timeout;
> +       bool switch_base_clk = false;
>
>         host->mmc->actual_clock = 0;
>
> @@ -1163,15 +1164,25 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
>                                         <= clock)
>                                         break;
>                         }
> -                       /*
> -                        * Set Programmable Clock Mode in the Clock
> -                        * Control register.
> -                        */
> -                       clk = SDHCI_PROG_CLOCK_MODE;
> -                       real_div = div;
> -                       clk_mul = host->clk_mul;
> -                       div--;
> -               } else {
> +                       if ((host->max_clk * host->clk_mul / div) <= clock) {
> +                               /*
> +                                * Set Programmable Clock Mode in the Clock
> +                                * Control register.
> +                                */
> +                               clk = SDHCI_PROG_CLOCK_MODE;
> +                               real_div = div;
> +                               clk_mul = host->clk_mul;
> +                               div--;
> +                       } else {
> +                               /*
> +                                * Divisor can be too small to reach clock
> +                                * speed requirement. Then use the base clock.
> +                                */
> +                               switch_base_clk = true;
> +                       }
> +               }
> +
> +               if (!host->clk_mul || switch_base_clk) {
>                         /* Version 3.00 divisors must be a multiple of 2. */
>                         if (host->max_clk <= clock)
>                                 div = 1;
> --
> 2.0.3
>

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [RFC PATCH] mmc: sdhci: switch from programmable clock mode to divided one if needed
  2014-11-04  8:06 ` Ulf Hansson
@ 2014-11-27 13:39   ` Ludovic Desroches
  0 siblings, 0 replies; 3+ messages in thread
From: Ludovic Desroches @ 2014-11-27 13:39 UTC (permalink / raw)
  To: Ulf Hansson; +Cc: linux-mmc, Chris Ball, Nicolas Ferre, Ludovic Desroches

On Tue, Nov 04, 2014 at 09:06:07AM +0100, Ulf Hansson wrote:
> On 7 October 2014 10:11, Ludovic Desroches <ludovic.desroches@atmel.com> wrote:
> > In programmable mode, if the clock frequency is too high, the divider
> > can be too small to meet the clock frequency requirement especially to
> > init the SD card. In this case, switch to the divided clock mode.
> >
> > Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
> > ---
> >
> > Hi all,
> >
> > I would like to know if this patch can be accepted. Use case, I have a base
> > clock at 12 MHz, M is 40. So in programmable mode, using the greater divider,
> > minimum clock frequency will be higher than 400 KHz so it could cause issues to
> > init the card.
> >
> > Thanks for your feedback.
> >
> > Ludovic
> 
> It would be nice if some of the senior sdhci developers could help out
> review patches likes this.
> 
> It touches the core of sdhci, thus affecting many of the sdhci drivers.
> 
> Anybody?
> 

Ping, any feedback?

Regards

Ludovic

> Kind regards
> Uffe
> 
> >
> >  drivers/mmc/host/sdhci.c | 29 ++++++++++++++++++++---------
> >  1 file changed, 20 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> > index df0e7e1..70d4c18 100644
> > --- a/drivers/mmc/host/sdhci.c
> > +++ b/drivers/mmc/host/sdhci.c
> > @@ -1126,6 +1126,7 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
> >         int real_div = div, clk_mul = 1;
> >         u16 clk = 0;
> >         unsigned long timeout;
> > +       bool switch_base_clk = false;
> >
> >         host->mmc->actual_clock = 0;
> >
> > @@ -1163,15 +1164,25 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
> >                                         <= clock)
> >                                         break;
> >                         }
> > -                       /*
> > -                        * Set Programmable Clock Mode in the Clock
> > -                        * Control register.
> > -                        */
> > -                       clk = SDHCI_PROG_CLOCK_MODE;
> > -                       real_div = div;
> > -                       clk_mul = host->clk_mul;
> > -                       div--;
> > -               } else {
> > +                       if ((host->max_clk * host->clk_mul / div) <= clock) {
> > +                               /*
> > +                                * Set Programmable Clock Mode in the Clock
> > +                                * Control register.
> > +                                */
> > +                               clk = SDHCI_PROG_CLOCK_MODE;
> > +                               real_div = div;
> > +                               clk_mul = host->clk_mul;
> > +                               div--;
> > +                       } else {
> > +                               /*
> > +                                * Divisor can be too small to reach clock
> > +                                * speed requirement. Then use the base clock.
> > +                                */
> > +                               switch_base_clk = true;
> > +                       }
> > +               }
> > +
> > +               if (!host->clk_mul || switch_base_clk) {
> >                         /* Version 3.00 divisors must be a multiple of 2. */
> >                         if (host->max_clk <= clock)
> >                                 div = 1;
> > --
> > 2.0.3
> >

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2014-11-27 13:39 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2014-10-07  8:11 [RFC PATCH] mmc: sdhci: switch from programmable clock mode to divided one if needed Ludovic Desroches
2014-11-04  8:06 ` Ulf Hansson
2014-11-27 13:39   ` Ludovic Desroches

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