From: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
To: ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com,
adrian.hunter@intel.com
Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
wan.ahmad.zainie.wan.mohamad@intel.com
Subject: [PATCH 1/2] dt-bindings: mmc: arasan: Add compatible strings for Intel Keem Bay
Date: Mon, 16 Mar 2020 17:13:23 +0800 [thread overview]
Message-ID: <20200316091324.15968-2-wan.ahmad.zainie.wan.mohamad@intel.com> (raw)
In-Reply-To: <20200316091324.15968-1-wan.ahmad.zainie.wan.mohamad@intel.com>
Add new compatible strings in sdhci-of-arasan.c to support Intel Keem Bay
eMMC/SD/SDIO controller, based on Arasan SDHCI 5.1.
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
---
.../devicetree/bindings/mmc/arasan,sdhci.txt | 39 +++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 428685eb2ded..50f9cc0eff2a 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -24,6 +24,10 @@ Required Properties:
For this device it is strongly suggested to include arasan,soc-ctl-syscon.
- "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
For this device it is strongly suggested to include arasan,soc-ctl-syscon.
+ - "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1": Keem Bay eMMC PHY
+ For this device it is strongly suggested to include arasan,soc-ctl-syscon.
+ - "intel,keembay-sdhci-5.1-sd": Keem Bay SD controller
+ - "intel,keembay-sdhci-5.1-sdio": Keem Bay SDIO controller
[5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
@@ -133,3 +137,38 @@ Example:
phy-names = "phy_arasan";
arasan,soc-ctl-syscon = <&sysconf>;
};
+
+ mmc: mmc@33000000 {
+ compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x33000000 0x0 0x300>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
+ <&scmi_clk KEEM_BAY_PSS_EMMC>;
+ phys = <&emmc_phy>;
+ phy-names = "phy_arasan";
+ assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
+ clock-output-names = "emmc_cardclock";
+ #clock-cells = <0>;
+ arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
+ };
+
+ sd0: sdhci@31000000 {
+ compatible = "intel,keembay-sdhci-5.1-sd";
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x31000000 0x0 0x300>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
+ <&scmi_clk KEEM_BAY_PSS_SD0>;
+ arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
+ };
+
+ sd1: sdhci@32000000 {
+ compatible = "intel,keembay-sdhci-5.1-sdio";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x32000000 0x0 0x300>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>,
+ <&scmi_clk KEEM_BAY_PSS_SD1>;
+ arasan,soc-ctl-syscon = <&sd1_phy_syscon>;
+ };
--
2.17.1
next prev parent reply other threads:[~2020-03-16 9:13 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-16 9:13 [PATCH 0/2] mmc: sdhci-of-arasan: Add support for Intel Keem Wan Ahmad Zainie
2020-03-16 9:13 ` Wan Ahmad Zainie [this message]
2020-03-18 11:08 ` [PATCH 1/2] dt-bindings: mmc: arasan: Add compatible strings for Intel Keem Bay Ulf Hansson
2020-03-19 12:15 ` Wan Mohamad, Wan Ahmad Zainie
2020-03-16 9:13 ` [PATCH 2/2] mmc: sdhci-of-arasan: Add support " Wan Ahmad Zainie
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