From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: linux-renesas-soc@vger.kernel.org
Cc: linux-clk@vger.kernel.org, linux-mmc@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
Wolfram Sang <wsa+renesas@sang-engineering.com>
Subject: [RFC PATCH 1/9] clk: renesas: gen3-cpg: add dummy SDnH clock
Date: Tue, 28 Sep 2021 22:07:56 +0200 [thread overview]
Message-ID: <20210928200804.50922-2-wsa+renesas@sang-engineering.com> (raw)
In-Reply-To: <20210928200804.50922-1-wsa+renesas@sang-engineering.com>
Currently, SDnH is handled together with SDn. This caused lots of
problems, so we want SDnH as a seperate clock. Introduce a dummy SDnH
type here which creates a fixed-factor clock with factor 1. That allows
us to convert the per-SoC CPG drivers while keeping the old behaviour
for now. A later patch then will add the proper functionality.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
drivers/clk/renesas/rcar-cpg-lib.c | 9 +++++++++
drivers/clk/renesas/rcar-cpg-lib.h | 4 ++++
drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++++
drivers/clk/renesas/rcar-gen3-cpg.h | 4 ++++
4 files changed, 21 insertions(+)
diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c
index 5678768ee1f2..351cb9c04f5c 100644
--- a/drivers/clk/renesas/rcar-cpg-lib.c
+++ b/drivers/clk/renesas/rcar-cpg-lib.c
@@ -65,6 +65,15 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
/*
* SDn Clock
*/
+
+struct clk * __init cpg_sdh_clk_register(const char *name,
+ void __iomem *sdnckcr, const char *parent_name,
+ struct raw_notifier_head *notifiers)
+{
+ /* placeholder during transition */
+ return clk_register_fixed_factor(NULL, name, parent_name, 0, 1, 1);
+}
+
#define CPG_SD_STP_HCK BIT(9)
#define CPG_SD_STP_CK BIT(8)
diff --git a/drivers/clk/renesas/rcar-cpg-lib.h b/drivers/clk/renesas/rcar-cpg-lib.h
index d00c91b116ca..548cb9562f35 100644
--- a/drivers/clk/renesas/rcar-cpg-lib.h
+++ b/drivers/clk/renesas/rcar-cpg-lib.h
@@ -26,6 +26,10 @@ void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set);
+struct clk * __init cpg_sdh_clk_register(const char *name,
+ void __iomem *sdnckcr, const char *parent_name,
+ struct raw_notifier_head *notifiers);
+
struct clk * __init cpg_sd_clk_register(const char *name,
void __iomem *base, unsigned int offset, const char *parent_name,
struct raw_notifier_head *notifiers, bool skip_first);
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 558191c99b48..182b189bc8f4 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -486,6 +486,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
mult *= 2;
break;
+ case CLK_TYPE_GEN3_SDH:
+ return cpg_sdh_clk_register(core->name, base + core->offset,
+ __clk_get_name(parent), notifiers);
+
case CLK_TYPE_GEN3_SD:
return cpg_sd_clk_register(core->name, base, core->offset,
__clk_get_name(parent), notifiers,
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 3d949c4a3244..2bc0afadf604 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -17,6 +17,7 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_PLL2,
CLK_TYPE_GEN3_PLL3,
CLK_TYPE_GEN3_PLL4,
+ CLK_TYPE_GEN3_SDH,
CLK_TYPE_GEN3_SD,
CLK_TYPE_GEN3_R,
CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
@@ -32,6 +33,9 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_SOC_BASE,
};
+#define DEF_GEN3_SDH(_name, _id, _parent, _offset) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
+
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
--
2.30.2
next prev parent reply other threads:[~2021-09-28 20:08 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-28 20:07 [RFC PATCH 0/9] clk/mmc: renesas_sdhi: refactor SDnH to be a seperate clock Wolfram Sang
2021-09-28 20:07 ` Wolfram Sang [this message]
2021-10-11 18:03 ` [RFC PATCH 1/9] clk: renesas: gen3-cpg: add dummy SDnH clock Geert Uytterhoeven
2021-09-28 20:07 ` [RFC PATCH 2/9] clk: renesas: add SDnH clock to Gen3 SoCs Wolfram Sang
2021-10-11 18:03 ` Geert Uytterhoeven
2021-09-28 20:07 ` [RFC PATCH 3/9] clk: renesas: r8a779a0: add SDnH clock to V3U Wolfram Sang
2021-10-11 18:03 ` Geert Uytterhoeven
2021-09-28 20:07 ` [RFC PATCH 4/9] clk: renesas: gen3: switch to new SD clock handling Wolfram Sang
2021-10-13 8:33 ` Geert Uytterhoeven
2021-10-21 9:59 ` Wolfram Sang
2021-10-21 11:10 ` Geert Uytterhoeven
2021-09-28 20:08 ` [RFC PATCH 5/9] clk: renesas: gen3-cpg: remove outdated SD_SKIP_FIRST Wolfram Sang
2021-10-11 18:03 ` Geert Uytterhoeven
2021-09-28 20:08 ` [RFC PATCH 6/9] dt-bindings: mmc: renesas,sdhi: add optional SDnH clock Wolfram Sang
2021-10-11 18:04 ` Geert Uytterhoeven
2021-09-28 20:08 ` [RFC PATCH 7/9] arm64: dts: r8a77951: add SDnH clocks Wolfram Sang
2021-10-11 18:04 ` Geert Uytterhoeven
2021-09-28 20:08 ` [RFC PATCH 8/9] arm64: dts: r8a77965: " Wolfram Sang
2021-10-11 18:04 ` Geert Uytterhoeven
2021-09-28 20:08 ` [RFC PATCH 9/9] mmc: renesas_sdhi: parse DT for SDnH Wolfram Sang
2021-10-11 18:04 ` Geert Uytterhoeven
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