From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: linux-renesas-soc@vger.kernel.org
Cc: linux-clk@vger.kernel.org, linux-mmc@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
Wolfram Sang <wsa+renesas@sang-engineering.com>
Subject: [RFC PATCH 5/9] clk: renesas: gen3-cpg: remove outdated SD_SKIP_FIRST
Date: Tue, 28 Sep 2021 22:08:00 +0200 [thread overview]
Message-ID: <20210928200804.50922-6-wsa+renesas@sang-engineering.com> (raw)
In-Reply-To: <20210928200804.50922-1-wsa+renesas@sang-engineering.com>
We handle it differently meanwhile.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
drivers/clk/renesas/rcar-gen3-cpg.c | 15 +++------------
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index aa0797b98e89..c4b36c90e159 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -397,29 +397,20 @@ static u32 cpg_quirks __initdata;
#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
-#define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
{
.soc_id = "r8a7795", .revision = "ES1.0",
- .data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST),
+ .data = (void *)(PLL_ERRATA | RCKCR_CKSEL),
},
{
.soc_id = "r8a7795", .revision = "ES1.*",
- .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
- },
- {
- .soc_id = "r8a7795", .revision = "ES2.0",
- .data = (void *)SD_SKIP_FIRST,
+ .data = (void *)(RCKCR_CKSEL),
},
{
.soc_id = "r8a7796", .revision = "ES1.0",
- .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
- },
- {
- .soc_id = "r8a7796", .revision = "ES1.1",
- .data = (void *)SD_SKIP_FIRST,
+ .data = (void *)(RCKCR_CKSEL),
},
{ /* sentinel */ }
};
--
2.30.2
next prev parent reply other threads:[~2021-09-28 20:08 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-28 20:07 [RFC PATCH 0/9] clk/mmc: renesas_sdhi: refactor SDnH to be a seperate clock Wolfram Sang
2021-09-28 20:07 ` [RFC PATCH 1/9] clk: renesas: gen3-cpg: add dummy SDnH clock Wolfram Sang
2021-10-11 18:03 ` Geert Uytterhoeven
2021-09-28 20:07 ` [RFC PATCH 2/9] clk: renesas: add SDnH clock to Gen3 SoCs Wolfram Sang
2021-10-11 18:03 ` Geert Uytterhoeven
2021-09-28 20:07 ` [RFC PATCH 3/9] clk: renesas: r8a779a0: add SDnH clock to V3U Wolfram Sang
2021-10-11 18:03 ` Geert Uytterhoeven
2021-09-28 20:07 ` [RFC PATCH 4/9] clk: renesas: gen3: switch to new SD clock handling Wolfram Sang
2021-10-13 8:33 ` Geert Uytterhoeven
2021-10-21 9:59 ` Wolfram Sang
2021-10-21 11:10 ` Geert Uytterhoeven
2021-09-28 20:08 ` Wolfram Sang [this message]
2021-10-11 18:03 ` [RFC PATCH 5/9] clk: renesas: gen3-cpg: remove outdated SD_SKIP_FIRST Geert Uytterhoeven
2021-09-28 20:08 ` [RFC PATCH 6/9] dt-bindings: mmc: renesas,sdhi: add optional SDnH clock Wolfram Sang
2021-10-11 18:04 ` Geert Uytterhoeven
2021-09-28 20:08 ` [RFC PATCH 7/9] arm64: dts: r8a77951: add SDnH clocks Wolfram Sang
2021-10-11 18:04 ` Geert Uytterhoeven
2021-09-28 20:08 ` [RFC PATCH 8/9] arm64: dts: r8a77965: " Wolfram Sang
2021-10-11 18:04 ` Geert Uytterhoeven
2021-09-28 20:08 ` [RFC PATCH 9/9] mmc: renesas_sdhi: parse DT for SDnH Wolfram Sang
2021-10-11 18:04 ` Geert Uytterhoeven
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