* [PATCH V2 1/3] mmc: sdhci-pci-gli: Add Genesys Logic GL9767 support
2023-05-30 9:53 [PATCH V2 0/3] Add Genesys Logic GL9767 support Victor Shih
@ 2023-05-30 9:53 ` Victor Shih
2023-05-31 7:01 ` Adrian Hunter
2023-05-30 9:53 ` [PATCH V2 2/3] mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz and enable SSC for GL9767 Victor Shih
2023-05-30 9:53 ` [PATCH V2 3/3] mmc: sdhci-pci-gli: Add support SD Express card " Victor Shih
2 siblings, 1 reply; 9+ messages in thread
From: Victor Shih @ 2023-05-30 9:53 UTC (permalink / raw)
To: ulf.hansson, adrian.hunter
Cc: linux-mmc, linux-kernel, benchuanggli, HL.Liu, Greg.tu,
Victor Shih, Ben Chuang, Victor Shih
From: Victor Shih <victor.shih@genesyslogic.com.tw>
Add support for the GL9767 chipset. GL9767 supports
SD3 mode likes UHS-I SDR50, SDR104.
Enable MSI interrupt for GL9767. Some platform do not
support PCI INTx and devices can not work without
interrupt.
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
---
drivers/mmc/host/sdhci-pci-core.c | 1 +
drivers/mmc/host/sdhci-pci-gli.c | 160 ++++++++++++++++++++++++++++++
drivers/mmc/host/sdhci-pci.h | 2 +
3 files changed, 163 insertions(+)
diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c
index 01975d145200..1c2572c0f012 100644
--- a/drivers/mmc/host/sdhci-pci-core.c
+++ b/drivers/mmc/host/sdhci-pci-core.c
@@ -1903,6 +1903,7 @@ static const struct pci_device_id pci_ids[] = {
SDHCI_PCI_DEVICE(GLI, 9750, gl9750),
SDHCI_PCI_DEVICE(GLI, 9755, gl9755),
SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e),
+ SDHCI_PCI_DEVICE(GLI, 9767, gl9767),
SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
/* Generic SD host controller */
{PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index 633a8ee8f8c5..3ed207b89d1a 100644
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -149,6 +149,32 @@
#define PCI_GLI_9755_PM_CTRL 0xFC
#define PCI_GLI_9755_PM_STATE GENMASK(1, 0)
+#define SDHCI_GLI_9767_GM_BURST_SIZE 0x510
+#define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8)
+
+#define PCIE_GLI_9767_VHS 0x884
+#define GLI_9767_VHS_REV GENMASK(19, 16)
+#define GLI_9767_VHS_REV_R 0x0
+#define GLI_9767_VHS_REV_M 0x1
+#define GLI_9767_VHS_REV_W 0x2
+
+#define PCIE_GLI_9767_PWR_MACRO_CTL 0x8D0
+#define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0)
+#define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12)
+#define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE 0x7
+#define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL GENMASK(29, 28)
+#define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE 0x3
+
+#define PCIE_GLI_9767_SCR 0x8E0
+#define PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST BIT(6)
+#define PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST BIT(7)
+#define PCIE_GLI_9767_SCR_AXI_REQ BIT(9)
+#define PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN BIT(10)
+#define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 BIT(16)
+#define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 BIT(17)
+#define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21)
+#define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30)
+
#define GLI_MAX_TUNING_LOOP 40
/* Genesys Logic chipset */
@@ -693,6 +719,89 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
gl9755_wt_off(pdev);
}
+static inline void gl9767_vhs_read(struct pci_dev *pdev)
+{
+ u32 vhs_enable;
+ u32 vhs_value;
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value);
+ vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value);
+
+ if (vhs_enable == GLI_9767_VHS_REV_R)
+ return;
+
+ vhs_value &= ~GLI_9767_VHS_REV;
+ vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_R);
+
+ pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
+}
+
+static inline void gl9767_vhs_write(struct pci_dev *pdev)
+{
+ u32 vhs_enable;
+ u32 vhs_value;
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value);
+ vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value);
+
+ if (vhs_enable == GLI_9767_VHS_REV_W)
+ return;
+
+ vhs_value &= ~GLI_9767_VHS_REV;
+ vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_W);
+
+ pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
+}
+
+static void gli_set_9767(struct sdhci_host *host)
+{
+ u32 value;
+
+ value = sdhci_readl(host, SDHCI_GLI_9767_GM_BURST_SIZE);
+ value &= ~SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET;
+ sdhci_writel(host, value, SDHCI_GLI_9767_GM_BURST_SIZE);
+}
+
+static void gl9767_hw_setting(struct sdhci_pci_slot *slot)
+{
+ struct pci_dev *pdev = slot->chip->pdev;
+ u32 value;
+
+ gl9767_vhs_write(pdev);
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, &value);
+ value &= ~(PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE |
+ PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE |
+ PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL);
+
+ value |= PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE |
+ FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE,
+ PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE) |
+ FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL,
+ PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE);
+ pci_write_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, value);
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_SCR, &value);
+ value &= ~(PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 |
+ PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 |
+ PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN);
+
+ value |= PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST |
+ PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST |
+ PCIE_GLI_9767_SCR_AXI_REQ |
+ PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN |
+ PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF;
+ pci_write_config_dword(pdev, PCIE_GLI_9767_SCR, value);
+
+ gl9767_vhs_read(pdev);
+}
+
+static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask)
+{
+ sdhci_reset(host, mask);
+ gli_set_9767(host);
+}
+
static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
{
struct sdhci_host *host = slot->host;
@@ -717,6 +826,19 @@ static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)
return 0;
}
+static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot)
+{
+ struct sdhci_host *host = slot->host;
+
+ gli_set_9767(host);
+ gl9767_hw_setting(slot);
+ gli_pcie_enable_msi(slot);
+ slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
+ sdhci_enable_v4_mode(host);
+
+ return 0;
+}
+
static void sdhci_gli_voltage_switch(struct sdhci_host *host)
{
/*
@@ -740,6 +862,25 @@ static void sdhci_gli_voltage_switch(struct sdhci_host *host)
usleep_range(100000, 110000);
}
+static void sdhci_gl9767_voltage_switch(struct sdhci_host *host)
+{
+ /*
+ * According to Section 3.6.1 signal voltage switch procedure in
+ * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
+ * follows:
+ * (6) Set 1.8V Signal Enable in the Host Control 2 register.
+ * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
+ * period.
+ * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
+ * step (12).
+ *
+ * Wait 5ms after set 1.8V signal enable in Host Control 2 register
+ * to ensure 1.8V signal enable bit is set by GL9767.
+ *
+ */
+ usleep_range(5000, 5500);
+}
+
static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
{
sdhci_reset(host, mask);
@@ -1150,3 +1291,22 @@ const struct sdhci_pci_fixes sdhci_gl9763e = {
#endif
.add_host = gl9763e_add_host,
};
+
+static const struct sdhci_ops sdhci_gl9767_ops = {
+ .set_clock = sdhci_set_clock,
+ .enable_dma = sdhci_pci_enable_dma,
+ .set_bus_width = sdhci_set_bus_width,
+ .reset = sdhci_gl9767_reset,
+ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ .voltage_switch = sdhci_gl9767_voltage_switch,
+};
+
+const struct sdhci_pci_fixes sdhci_gl9767 = {
+ .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
+ .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
+ .probe_slot = gli_probe_slot_gl9767,
+ .ops = &sdhci_gl9767_ops,
+#ifdef CONFIG_PM_SLEEP
+ .resume = sdhci_pci_gli_resume,
+#endif
+};
diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h
index 3661a224fb04..9c8863956381 100644
--- a/drivers/mmc/host/sdhci-pci.h
+++ b/drivers/mmc/host/sdhci-pci.h
@@ -76,6 +76,7 @@
#define PCI_DEVICE_ID_GLI_9755 0x9755
#define PCI_DEVICE_ID_GLI_9750 0x9750
#define PCI_DEVICE_ID_GLI_9763E 0xe763
+#define PCI_DEVICE_ID_GLI_9767 0x9767
/*
* PCI device class and mask
@@ -195,5 +196,6 @@ extern const struct sdhci_pci_fixes sdhci_o2;
extern const struct sdhci_pci_fixes sdhci_gl9750;
extern const struct sdhci_pci_fixes sdhci_gl9755;
extern const struct sdhci_pci_fixes sdhci_gl9763e;
+extern const struct sdhci_pci_fixes sdhci_gl9767;
#endif /* __SDHCI_PCI_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH V2 1/3] mmc: sdhci-pci-gli: Add Genesys Logic GL9767 support
2023-05-30 9:53 ` [PATCH V2 1/3] mmc: sdhci-pci-gli: " Victor Shih
@ 2023-05-31 7:01 ` Adrian Hunter
0 siblings, 0 replies; 9+ messages in thread
From: Adrian Hunter @ 2023-05-31 7:01 UTC (permalink / raw)
To: Victor Shih, ulf.hansson
Cc: linux-mmc, linux-kernel, benchuanggli, HL.Liu, Greg.tu,
Ben Chuang, Victor Shih
On 30/05/23 12:53, Victor Shih wrote:
> From: Victor Shih <victor.shih@genesyslogic.com.tw>
>
> Add support for the GL9767 chipset. GL9767 supports
> SD3 mode likes UHS-I SDR50, SDR104.
> Enable MSI interrupt for GL9767. Some platform do not
> support PCI INTx and devices can not work without
> interrupt.
>
> Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
> Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
> drivers/mmc/host/sdhci-pci-core.c | 1 +
> drivers/mmc/host/sdhci-pci-gli.c | 160 ++++++++++++++++++++++++++++++
> drivers/mmc/host/sdhci-pci.h | 2 +
> 3 files changed, 163 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c
> index 01975d145200..1c2572c0f012 100644
> --- a/drivers/mmc/host/sdhci-pci-core.c
> +++ b/drivers/mmc/host/sdhci-pci-core.c
> @@ -1903,6 +1903,7 @@ static const struct pci_device_id pci_ids[] = {
> SDHCI_PCI_DEVICE(GLI, 9750, gl9750),
> SDHCI_PCI_DEVICE(GLI, 9755, gl9755),
> SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e),
> + SDHCI_PCI_DEVICE(GLI, 9767, gl9767),
> SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
> /* Generic SD host controller */
> {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index 633a8ee8f8c5..3ed207b89d1a 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -149,6 +149,32 @@
> #define PCI_GLI_9755_PM_CTRL 0xFC
> #define PCI_GLI_9755_PM_STATE GENMASK(1, 0)
>
> +#define SDHCI_GLI_9767_GM_BURST_SIZE 0x510
> +#define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8)
> +
> +#define PCIE_GLI_9767_VHS 0x884
> +#define GLI_9767_VHS_REV GENMASK(19, 16)
> +#define GLI_9767_VHS_REV_R 0x0
> +#define GLI_9767_VHS_REV_M 0x1
> +#define GLI_9767_VHS_REV_W 0x2
> +
> +#define PCIE_GLI_9767_PWR_MACRO_CTL 0x8D0
> +#define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0)
> +#define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12)
> +#define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE 0x7
> +#define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL GENMASK(29, 28)
> +#define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE 0x3
> +
> +#define PCIE_GLI_9767_SCR 0x8E0
> +#define PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST BIT(6)
> +#define PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST BIT(7)
> +#define PCIE_GLI_9767_SCR_AXI_REQ BIT(9)
> +#define PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN BIT(10)
> +#define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 BIT(16)
> +#define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 BIT(17)
> +#define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21)
> +#define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30)
> +
> #define GLI_MAX_TUNING_LOOP 40
>
> /* Genesys Logic chipset */
> @@ -693,6 +719,89 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
> gl9755_wt_off(pdev);
> }
>
> +static inline void gl9767_vhs_read(struct pci_dev *pdev)
> +{
> + u32 vhs_enable;
> + u32 vhs_value;
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value);
> + vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value);
> +
> + if (vhs_enable == GLI_9767_VHS_REV_R)
> + return;
> +
> + vhs_value &= ~GLI_9767_VHS_REV;
> + vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_R);
> +
> + pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
> +}
> +
> +static inline void gl9767_vhs_write(struct pci_dev *pdev)
> +{
> + u32 vhs_enable;
> + u32 vhs_value;
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value);
> + vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value);
> +
> + if (vhs_enable == GLI_9767_VHS_REV_W)
> + return;
> +
> + vhs_value &= ~GLI_9767_VHS_REV;
> + vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_W);
> +
> + pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
> +}
> +
> +static void gli_set_9767(struct sdhci_host *host)
> +{
> + u32 value;
> +
> + value = sdhci_readl(host, SDHCI_GLI_9767_GM_BURST_SIZE);
> + value &= ~SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET;
> + sdhci_writel(host, value, SDHCI_GLI_9767_GM_BURST_SIZE);
> +}
> +
> +static void gl9767_hw_setting(struct sdhci_pci_slot *slot)
> +{
> + struct pci_dev *pdev = slot->chip->pdev;
> + u32 value;
> +
> + gl9767_vhs_write(pdev);
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, &value);
> + value &= ~(PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE |
> + PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE |
> + PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL);
> +
> + value |= PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE |
> + FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE,
> + PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE) |
> + FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL,
> + PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE);
> + pci_write_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, value);
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_SCR, &value);
> + value &= ~(PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 |
> + PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 |
> + PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN);
> +
> + value |= PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST |
> + PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST |
> + PCIE_GLI_9767_SCR_AXI_REQ |
> + PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN |
> + PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF;
> + pci_write_config_dword(pdev, PCIE_GLI_9767_SCR, value);
> +
> + gl9767_vhs_read(pdev);
> +}
> +
> +static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask)
> +{
> + sdhci_reset(host, mask);
> + gli_set_9767(host);
> +}
> +
> static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
> {
> struct sdhci_host *host = slot->host;
> @@ -717,6 +826,19 @@ static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)
> return 0;
> }
>
> +static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot)
> +{
> + struct sdhci_host *host = slot->host;
> +
> + gli_set_9767(host);
> + gl9767_hw_setting(slot);
> + gli_pcie_enable_msi(slot);
> + slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
> + sdhci_enable_v4_mode(host);
> +
> + return 0;
> +}
> +
> static void sdhci_gli_voltage_switch(struct sdhci_host *host)
> {
> /*
> @@ -740,6 +862,25 @@ static void sdhci_gli_voltage_switch(struct sdhci_host *host)
> usleep_range(100000, 110000);
> }
>
> +static void sdhci_gl9767_voltage_switch(struct sdhci_host *host)
> +{
> + /*
> + * According to Section 3.6.1 signal voltage switch procedure in
> + * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
> + * follows:
> + * (6) Set 1.8V Signal Enable in the Host Control 2 register.
> + * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
> + * period.
> + * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
> + * step (12).
> + *
> + * Wait 5ms after set 1.8V signal enable in Host Control 2 register
> + * to ensure 1.8V signal enable bit is set by GL9767.
> + *
> + */
> + usleep_range(5000, 5500);
> +}
> +
> static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
> {
> sdhci_reset(host, mask);
> @@ -1150,3 +1291,22 @@ const struct sdhci_pci_fixes sdhci_gl9763e = {
> #endif
> .add_host = gl9763e_add_host,
> };
> +
> +static const struct sdhci_ops sdhci_gl9767_ops = {
> + .set_clock = sdhci_set_clock,
> + .enable_dma = sdhci_pci_enable_dma,
> + .set_bus_width = sdhci_set_bus_width,
> + .reset = sdhci_gl9767_reset,
> + .set_uhs_signaling = sdhci_set_uhs_signaling,
> + .voltage_switch = sdhci_gl9767_voltage_switch,
> +};
> +
> +const struct sdhci_pci_fixes sdhci_gl9767 = {
> + .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
> + .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,
> + .probe_slot = gli_probe_slot_gl9767,
> + .ops = &sdhci_gl9767_ops,
> +#ifdef CONFIG_PM_SLEEP
> + .resume = sdhci_pci_gli_resume,
> +#endif
> +};
> diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h
> index 3661a224fb04..9c8863956381 100644
> --- a/drivers/mmc/host/sdhci-pci.h
> +++ b/drivers/mmc/host/sdhci-pci.h
> @@ -76,6 +76,7 @@
> #define PCI_DEVICE_ID_GLI_9755 0x9755
> #define PCI_DEVICE_ID_GLI_9750 0x9750
> #define PCI_DEVICE_ID_GLI_9763E 0xe763
> +#define PCI_DEVICE_ID_GLI_9767 0x9767
>
> /*
> * PCI device class and mask
> @@ -195,5 +196,6 @@ extern const struct sdhci_pci_fixes sdhci_o2;
> extern const struct sdhci_pci_fixes sdhci_gl9750;
> extern const struct sdhci_pci_fixes sdhci_gl9755;
> extern const struct sdhci_pci_fixes sdhci_gl9763e;
> +extern const struct sdhci_pci_fixes sdhci_gl9767;
>
> #endif /* __SDHCI_PCI_H */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH V2 2/3] mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz and enable SSC for GL9767
2023-05-30 9:53 [PATCH V2 0/3] Add Genesys Logic GL9767 support Victor Shih
2023-05-30 9:53 ` [PATCH V2 1/3] mmc: sdhci-pci-gli: " Victor Shih
@ 2023-05-30 9:53 ` Victor Shih
2023-05-31 7:01 ` Adrian Hunter
2023-05-30 9:53 ` [PATCH V2 3/3] mmc: sdhci-pci-gli: Add support SD Express card " Victor Shih
2 siblings, 1 reply; 9+ messages in thread
From: Victor Shih @ 2023-05-30 9:53 UTC (permalink / raw)
To: ulf.hansson, adrian.hunter
Cc: linux-mmc, linux-kernel, benchuanggli, HL.Liu, Greg.tu,
Victor Shih, Ben Chuang, Victor Shih
From: Victor Shih <victor.shih@genesyslogic.com.tw>
Set GL9767 SDR104's clock to 205MHz and enable SSC feature
depend on register 0x888 BIT(1).
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
---
drivers/mmc/host/sdhci-pci-gli.c | 135 ++++++++++++++++++++++++++++++-
1 file changed, 134 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index 3ed207b89d1a..178253a7e86f 100644
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -158,6 +158,12 @@
#define GLI_9767_VHS_REV_M 0x1
#define GLI_9767_VHS_REV_W 0x2
+#define PCIE_GLI_9767_COM_MAILBOX 0x888
+#define PCIE_GLI_9767_COM_MAILBOX_SSC_EN BIT(1)
+
+#define PCIE_GLI_9767_CFG 0x8A0
+#define PCIE_GLI_9767_CFG_LOW_PWR_OFF BIT(12)
+
#define PCIE_GLI_9767_PWR_MACRO_CTL 0x8D0
#define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0)
#define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12)
@@ -175,6 +181,16 @@
#define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21)
#define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30)
+#define PCIE_GLI_9767_SD_PLL_CTL 0x938
+#define PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV GENMASK(9, 0)
+#define PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV GENMASK(15, 12)
+#define PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN BIT(16)
+#define PCIE_GLI_9767_SD_PLL_CTL_SSC_EN BIT(19)
+#define PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING GENMASK(28, 24)
+
+#define PCIE_GLI_9767_SD_PLL_CTL2 0x93C
+#define PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM GENMASK(31, 16)
+
#define GLI_MAX_TUNING_LOOP 40
/* Genesys Logic chipset */
@@ -753,6 +769,123 @@ static inline void gl9767_vhs_write(struct pci_dev *pdev)
pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
}
+static bool gl9767_ssc_enable(struct pci_dev *pdev)
+{
+ u32 value;
+ u8 enable;
+
+ gl9767_vhs_write(pdev);
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_COM_MAILBOX, &value);
+ enable = FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value);
+
+ gl9767_vhs_read(pdev);
+
+ return enable;
+}
+
+static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
+{
+ u32 pll;
+ u32 ssc;
+
+ gl9767_vhs_write(pdev);
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
+ pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc);
+ pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING |
+ PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);
+ ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM;
+ pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING, step) |
+ FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable);
+ ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm);
+ pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc);
+ pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
+
+ gl9767_vhs_read(pdev);
+}
+
+static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
+{
+ u32 pll;
+
+ gl9767_vhs_write(pdev);
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
+ pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV |
+ PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV |
+ PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN);
+ pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) |
+ FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV, pdiv) |
+ FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir);
+ pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
+
+ gl9767_vhs_read(pdev);
+
+ /* wait for pll stable */
+ mdelay(1);
+}
+
+static void gl9767_set_ssc_pll_205mhz(struct pci_dev *pdev)
+{
+ bool enable = gl9767_ssc_enable(pdev);
+
+ /* set pll to 205MHz and ssc */
+ gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3);
+ gl9767_set_pll(pdev, 0x1, 0x246, 0x0);
+}
+
+static void gl9767_disable_ssc_pll(struct pci_dev *pdev)
+{
+ u32 pll;
+
+ gl9767_vhs_write(pdev);
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
+ pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN | PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);
+ pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
+
+ gl9767_vhs_read(pdev);
+}
+
+static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+ struct sdhci_pci_slot *slot = sdhci_priv(host);
+ struct mmc_ios *ios = &host->mmc->ios;
+ struct pci_dev *pdev;
+ u32 value;
+ u16 clk;
+
+ pdev = slot->chip->pdev;
+ host->mmc->actual_clock = 0;
+
+ gl9767_vhs_write(pdev);
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
+ value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;
+ pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
+
+ gl9767_disable_ssc_pll(pdev);
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+
+ if (clock == 0)
+ return;
+
+ clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
+ if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
+ host->mmc->actual_clock = 205000000;
+ gl9767_set_ssc_pll_205mhz(pdev);
+ }
+
+ sdhci_enable_clk(host, clk);
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
+ value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF;
+ pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
+
+ gl9767_vhs_read(pdev);
+}
+
static void gli_set_9767(struct sdhci_host *host)
{
u32 value;
@@ -1293,7 +1426,7 @@ const struct sdhci_pci_fixes sdhci_gl9763e = {
};
static const struct sdhci_ops sdhci_gl9767_ops = {
- .set_clock = sdhci_set_clock,
+ .set_clock = sdhci_gl9767_set_clock,
.enable_dma = sdhci_pci_enable_dma,
.set_bus_width = sdhci_set_bus_width,
.reset = sdhci_gl9767_reset,
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH V2 2/3] mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz and enable SSC for GL9767
2023-05-30 9:53 ` [PATCH V2 2/3] mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz and enable SSC for GL9767 Victor Shih
@ 2023-05-31 7:01 ` Adrian Hunter
2023-05-31 9:45 ` Victor Shih
0 siblings, 1 reply; 9+ messages in thread
From: Adrian Hunter @ 2023-05-31 7:01 UTC (permalink / raw)
To: Victor Shih, ulf.hansson
Cc: linux-mmc, linux-kernel, benchuanggli, HL.Liu, Greg.tu,
Ben Chuang, Victor Shih
On 30/05/23 12:53, Victor Shih wrote:
> From: Victor Shih <victor.shih@genesyslogic.com.tw>
>
> Set GL9767 SDR104's clock to 205MHz and enable SSC feature
> depend on register 0x888 BIT(1).
>
> Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
> Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
> ---
> drivers/mmc/host/sdhci-pci-gli.c | 135 ++++++++++++++++++++++++++++++-
> 1 file changed, 134 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index 3ed207b89d1a..178253a7e86f 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -158,6 +158,12 @@
> #define GLI_9767_VHS_REV_M 0x1
> #define GLI_9767_VHS_REV_W 0x2
>
> +#define PCIE_GLI_9767_COM_MAILBOX 0x888
> +#define PCIE_GLI_9767_COM_MAILBOX_SSC_EN BIT(1)
> +
> +#define PCIE_GLI_9767_CFG 0x8A0
> +#define PCIE_GLI_9767_CFG_LOW_PWR_OFF BIT(12)
> +
> #define PCIE_GLI_9767_PWR_MACRO_CTL 0x8D0
> #define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0)
> #define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12)
> @@ -175,6 +181,16 @@
> #define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21)
> #define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30)
>
> +#define PCIE_GLI_9767_SD_PLL_CTL 0x938
> +#define PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV GENMASK(9, 0)
> +#define PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV GENMASK(15, 12)
> +#define PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN BIT(16)
> +#define PCIE_GLI_9767_SD_PLL_CTL_SSC_EN BIT(19)
> +#define PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING GENMASK(28, 24)
> +
> +#define PCIE_GLI_9767_SD_PLL_CTL2 0x93C
> +#define PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM GENMASK(31, 16)
> +
> #define GLI_MAX_TUNING_LOOP 40
>
> /* Genesys Logic chipset */
> @@ -753,6 +769,123 @@ static inline void gl9767_vhs_write(struct pci_dev *pdev)
> pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
> }
>
> +static bool gl9767_ssc_enable(struct pci_dev *pdev)
> +{
> + u32 value;
> + u8 enable;
> +
> + gl9767_vhs_write(pdev);
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_COM_MAILBOX, &value);
> + enable = FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value);
> +
> + gl9767_vhs_read(pdev);
> +
> + return enable;
> +}
> +
> +static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
> +{
> + u32 pll;
> + u32 ssc;
> +
> + gl9767_vhs_write(pdev);
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
> + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc);
> + pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING |
> + PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);
> + ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM;
> + pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING, step) |
> + FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable);
> + ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm);
> + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc);
> + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
> +
> + gl9767_vhs_read(pdev);
> +}
> +
> +static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
> +{
> + u32 pll;
> +
> + gl9767_vhs_write(pdev);
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
> + pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV |
> + PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV |
> + PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN);
> + pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) |
> + FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV, pdiv) |
> + FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir);
> + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
> +
> + gl9767_vhs_read(pdev);
> +
> + /* wait for pll stable */
> + mdelay(1);
So long as SDHCI_QUIRK_CLOCK_BEFORE_RESET is not used, it is OK
to sleep here, so msleep() or usleep_range()
> +}
> +
> +static void gl9767_set_ssc_pll_205mhz(struct pci_dev *pdev)
> +{
> + bool enable = gl9767_ssc_enable(pdev);
> +
> + /* set pll to 205MHz and ssc */
> + gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3);
> + gl9767_set_pll(pdev, 0x1, 0x246, 0x0);
> +}
> +
> +static void gl9767_disable_ssc_pll(struct pci_dev *pdev)
> +{
> + u32 pll;
> +
> + gl9767_vhs_write(pdev);
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
> + pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN | PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);
> + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
> +
> + gl9767_vhs_read(pdev);
> +}
> +
> +static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock)
> +{
> + struct sdhci_pci_slot *slot = sdhci_priv(host);
> + struct mmc_ios *ios = &host->mmc->ios;
> + struct pci_dev *pdev;
> + u32 value;
> + u16 clk;
> +
> + pdev = slot->chip->pdev;
> + host->mmc->actual_clock = 0;
> +
> + gl9767_vhs_write(pdev);
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
> + value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;
> + pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
> +
> + gl9767_disable_ssc_pll(pdev);
> + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
> +
> + if (clock == 0)
> + return;
> +
> + clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
> + if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
> + host->mmc->actual_clock = 205000000;
> + gl9767_set_ssc_pll_205mhz(pdev);
> + }
> +
> + sdhci_enable_clk(host, clk);
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
> + value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF;
> + pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
> +
> + gl9767_vhs_read(pdev);
> +}
> +
> static void gli_set_9767(struct sdhci_host *host)
> {
> u32 value;
> @@ -1293,7 +1426,7 @@ const struct sdhci_pci_fixes sdhci_gl9763e = {
> };
>
> static const struct sdhci_ops sdhci_gl9767_ops = {
> - .set_clock = sdhci_set_clock,
> + .set_clock = sdhci_gl9767_set_clock,
> .enable_dma = sdhci_pci_enable_dma,
> .set_bus_width = sdhci_set_bus_width,
> .reset = sdhci_gl9767_reset,
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH V2 2/3] mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz and enable SSC for GL9767
2023-05-31 7:01 ` Adrian Hunter
@ 2023-05-31 9:45 ` Victor Shih
0 siblings, 0 replies; 9+ messages in thread
From: Victor Shih @ 2023-05-31 9:45 UTC (permalink / raw)
To: Adrian Hunter
Cc: ulf.hansson, linux-mmc, linux-kernel, benchuanggli, HL.Liu,
Greg.tu, Ben Chuang, Victor Shih
Hi, Adrian
On Wed, May 31, 2023 at 3:01 PM Adrian Hunter <adrian.hunter@intel.com> wrote:
>
> On 30/05/23 12:53, Victor Shih wrote:
> > From: Victor Shih <victor.shih@genesyslogic.com.tw>
> >
> > Set GL9767 SDR104's clock to 205MHz and enable SSC feature
> > depend on register 0x888 BIT(1).
> >
> > Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
> > Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
> > ---
> > drivers/mmc/host/sdhci-pci-gli.c | 135 ++++++++++++++++++++++++++++++-
> > 1 file changed, 134 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> > index 3ed207b89d1a..178253a7e86f 100644
> > --- a/drivers/mmc/host/sdhci-pci-gli.c
> > +++ b/drivers/mmc/host/sdhci-pci-gli.c
> > @@ -158,6 +158,12 @@
> > #define GLI_9767_VHS_REV_M 0x1
> > #define GLI_9767_VHS_REV_W 0x2
> >
> > +#define PCIE_GLI_9767_COM_MAILBOX 0x888
> > +#define PCIE_GLI_9767_COM_MAILBOX_SSC_EN BIT(1)
> > +
> > +#define PCIE_GLI_9767_CFG 0x8A0
> > +#define PCIE_GLI_9767_CFG_LOW_PWR_OFF BIT(12)
> > +
> > #define PCIE_GLI_9767_PWR_MACRO_CTL 0x8D0
> > #define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0)
> > #define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12)
> > @@ -175,6 +181,16 @@
> > #define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21)
> > #define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30)
> >
> > +#define PCIE_GLI_9767_SD_PLL_CTL 0x938
> > +#define PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV GENMASK(9, 0)
> > +#define PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV GENMASK(15, 12)
> > +#define PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN BIT(16)
> > +#define PCIE_GLI_9767_SD_PLL_CTL_SSC_EN BIT(19)
> > +#define PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING GENMASK(28, 24)
> > +
> > +#define PCIE_GLI_9767_SD_PLL_CTL2 0x93C
> > +#define PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM GENMASK(31, 16)
> > +
> > #define GLI_MAX_TUNING_LOOP 40
> >
> > /* Genesys Logic chipset */
> > @@ -753,6 +769,123 @@ static inline void gl9767_vhs_write(struct pci_dev *pdev)
> > pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
> > }
> >
> > +static bool gl9767_ssc_enable(struct pci_dev *pdev)
> > +{
> > + u32 value;
> > + u8 enable;
> > +
> > + gl9767_vhs_write(pdev);
> > +
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_COM_MAILBOX, &value);
> > + enable = FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value);
> > +
> > + gl9767_vhs_read(pdev);
> > +
> > + return enable;
> > +}
> > +
> > +static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
> > +{
> > + u32 pll;
> > + u32 ssc;
> > +
> > + gl9767_vhs_write(pdev);
> > +
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc);
> > + pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING |
> > + PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);
> > + ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM;
> > + pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING, step) |
> > + FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable);
> > + ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm);
> > + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc);
> > + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
> > +
> > + gl9767_vhs_read(pdev);
> > +}
> > +
> > +static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
> > +{
> > + u32 pll;
> > +
> > + gl9767_vhs_write(pdev);
> > +
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
> > + pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV |
> > + PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV |
> > + PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN);
> > + pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) |
> > + FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV, pdiv) |
> > + FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir);
> > + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
> > +
> > + gl9767_vhs_read(pdev);
> > +
> > + /* wait for pll stable */
> > + mdelay(1);
>
> So long as SDHCI_QUIRK_CLOCK_BEFORE_RESET is not used, it is OK
> to sleep here, so msleep() or usleep_range()
>
I will update it in patch v3.
> > +}
> > +
> > +static void gl9767_set_ssc_pll_205mhz(struct pci_dev *pdev)
> > +{
> > + bool enable = gl9767_ssc_enable(pdev);
> > +
> > + /* set pll to 205MHz and ssc */
> > + gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3);
> > + gl9767_set_pll(pdev, 0x1, 0x246, 0x0);
> > +}
> > +
> > +static void gl9767_disable_ssc_pll(struct pci_dev *pdev)
> > +{
> > + u32 pll;
> > +
> > + gl9767_vhs_write(pdev);
> > +
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
> > + pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN | PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);
> > + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
> > +
> > + gl9767_vhs_read(pdev);
> > +}
> > +
> > +static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock)
> > +{
> > + struct sdhci_pci_slot *slot = sdhci_priv(host);
> > + struct mmc_ios *ios = &host->mmc->ios;
> > + struct pci_dev *pdev;
> > + u32 value;
> > + u16 clk;
> > +
> > + pdev = slot->chip->pdev;
> > + host->mmc->actual_clock = 0;
> > +
> > + gl9767_vhs_write(pdev);
> > +
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
> > + value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;
> > + pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
> > +
> > + gl9767_disable_ssc_pll(pdev);
> > + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
> > +
> > + if (clock == 0)
> > + return;
> > +
> > + clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
> > + if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
> > + host->mmc->actual_clock = 205000000;
> > + gl9767_set_ssc_pll_205mhz(pdev);
> > + }
> > +
> > + sdhci_enable_clk(host, clk);
> > +
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
> > + value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF;
> > + pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
> > +
> > + gl9767_vhs_read(pdev);
> > +}
> > +
> > static void gli_set_9767(struct sdhci_host *host)
> > {
> > u32 value;
> > @@ -1293,7 +1426,7 @@ const struct sdhci_pci_fixes sdhci_gl9763e = {
> > };
> >
> > static const struct sdhci_ops sdhci_gl9767_ops = {
> > - .set_clock = sdhci_set_clock,
> > + .set_clock = sdhci_gl9767_set_clock,
> > .enable_dma = sdhci_pci_enable_dma,
> > .set_bus_width = sdhci_set_bus_width,
> > .reset = sdhci_gl9767_reset,
>
Thanks, Victor Shih
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH V2 3/3] mmc: sdhci-pci-gli: Add support SD Express card for GL9767
2023-05-30 9:53 [PATCH V2 0/3] Add Genesys Logic GL9767 support Victor Shih
2023-05-30 9:53 ` [PATCH V2 1/3] mmc: sdhci-pci-gli: " Victor Shih
2023-05-30 9:53 ` [PATCH V2 2/3] mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz and enable SSC for GL9767 Victor Shih
@ 2023-05-30 9:53 ` Victor Shih
2023-05-31 7:14 ` Adrian Hunter
2 siblings, 1 reply; 9+ messages in thread
From: Victor Shih @ 2023-05-30 9:53 UTC (permalink / raw)
To: ulf.hansson, adrian.hunter
Cc: linux-mmc, linux-kernel, benchuanggli, HL.Liu, Greg.tu,
Victor Shih, Ben Chuang, Victor Shih
From: Victor Shih <victor.shih@genesyslogic.com.tw>
Add support SD Express card for GL9767. The workflow of the
SD Express card in GL9767 is as below.
1. GL9767 operates in SD mode and set MMC_CAP2_SD_EXP flag.
2. If card is inserted, Host send CMD8 to ask the capabilities
of the card.
3. If the card has PCIe capability, then init_sd_express()
will be invoked.
4. If the card has been put in write protect state then the
SD features supported by SD mode but not supported by
PCIe mode, therefore GL9767 switch to SD mode.
5. If the card has not been put in write protect state then
GL9767 switch from SD mode to PCIe/NVMe mode and mmc driver
handover control to NVMe driver.
6. If card is removed, GL9767 will return to SD mode.
Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
---
drivers/mmc/host/sdhci-pci-gli.c | 105 +++++++++++++++++++++++++++++++
1 file changed, 105 insertions(+)
diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index 178253a7e86f..c7fa92fdadcd 100644
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -164,6 +164,10 @@
#define PCIE_GLI_9767_CFG 0x8A0
#define PCIE_GLI_9767_CFG_LOW_PWR_OFF BIT(12)
+#define PCIE_GLI_9767_COMBO_MUX_CTL 0x8C8
+#define PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN BIT(6)
+#define PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN BIT(10)
+
#define PCIE_GLI_9767_PWR_MACRO_CTL 0x8D0
#define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0)
#define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12)
@@ -181,6 +185,26 @@
#define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21)
#define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30)
+#define PCIE_GLI_9767_SDHC_CAP 0x91C
+#define PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT BIT(5)
+
+#define PCIE_GLI_9767_SD_EXPRESS_CTL 0x940
+#define PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE BIT(0)
+#define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1)
+
+#define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944
+#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME GENMASK(23, 16)
+#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE 0x64
+
+#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2 0x950
+#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE BIT(0)
+
+#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2 0x954
+#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN BIT(0)
+
+#define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2 0x958
+#define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN BIT(0)
+
#define PCIE_GLI_9767_SD_PLL_CTL 0x938
#define PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV GENMASK(9, 0)
#define PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV GENMASK(15, 12)
@@ -935,6 +959,85 @@ static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask)
gli_set_9767(host);
}
+static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct sdhci_pci_slot *slot = sdhci_priv(host);
+ struct pci_dev *pdev;
+ u32 value;
+ int i;
+
+ pdev = slot->chip->pdev;
+
+ if (mmc->ops->get_ro(mmc)) {
+ mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);
+ return 0;
+ }
+
+ gl9767_vhs_write(pdev);
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, &value);
+ value &= ~(PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN | PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN);
+ pci_write_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, value);
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value);
+ value &= ~PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME;
+ value |= FIELD_PREP(PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME,
+ PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE);
+ pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value);
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);
+ value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE;
+ pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, value);
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, &value);
+ value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN;
+ pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, value);
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, &value);
+ value |= PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN;
+ pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, value);
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
+ value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;
+ pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
+
+ value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ value &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN);
+ sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);
+
+ value = sdhci_readb(host, SDHCI_POWER_CONTROL);
+ value |= ((SDHCI_POWER_180 | SDHCI_POWER_ON) << 4);
+ sdhci_writeb(host, value, SDHCI_POWER_CONTROL);
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
+ value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE;
+ pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
+
+ for (i = 0; i < 2; i++) {
+ msleep(10);
+ pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);
+ if (value & PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE) {
+ pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2,
+ value);
+ break;
+ }
+ }
+
+ pci_read_config_dword(pdev, PCIE_GLI_9767_SDHC_CAP, &value);
+ if ((value & PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT) == PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT) {
+ pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
+ value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE;
+ pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
+ } else {
+ mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);
+ }
+
+ gl9767_vhs_read(pdev);
+
+ return 0;
+}
+
static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
{
struct sdhci_host *host = slot->host;
@@ -967,6 +1070,8 @@ static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot)
gl9767_hw_setting(slot);
gli_pcie_enable_msi(slot);
slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
+ host->mmc->caps2 |= MMC_CAP2_SD_EXP;
+ host->mmc_host_ops.init_sd_express = gl9767_init_sd_express;
sdhci_enable_v4_mode(host);
return 0;
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH V2 3/3] mmc: sdhci-pci-gli: Add support SD Express card for GL9767
2023-05-30 9:53 ` [PATCH V2 3/3] mmc: sdhci-pci-gli: Add support SD Express card " Victor Shih
@ 2023-05-31 7:14 ` Adrian Hunter
2023-05-31 9:45 ` Victor Shih
0 siblings, 1 reply; 9+ messages in thread
From: Adrian Hunter @ 2023-05-31 7:14 UTC (permalink / raw)
To: Victor Shih, ulf.hansson
Cc: linux-mmc, linux-kernel, benchuanggli, HL.Liu, Greg.tu,
Ben Chuang, Victor Shih
On 30/05/23 12:53, Victor Shih wrote:
> From: Victor Shih <victor.shih@genesyslogic.com.tw>
>
> Add support SD Express card for GL9767. The workflow of the
> SD Express card in GL9767 is as below.
> 1. GL9767 operates in SD mode and set MMC_CAP2_SD_EXP flag.
> 2. If card is inserted, Host send CMD8 to ask the capabilities
> of the card.
> 3. If the card has PCIe capability, then init_sd_express()
> will be invoked.
> 4. If the card has been put in write protect state then the
> SD features supported by SD mode but not supported by
> PCIe mode, therefore GL9767 switch to SD mode.
> 5. If the card has not been put in write protect state then
> GL9767 switch from SD mode to PCIe/NVMe mode and mmc driver
> handover control to NVMe driver.
> 6. If card is removed, GL9767 will return to SD mode.
>
> Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
> Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
> drivers/mmc/host/sdhci-pci-gli.c | 105 +++++++++++++++++++++++++++++++
> 1 file changed, 105 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index 178253a7e86f..c7fa92fdadcd 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -164,6 +164,10 @@
> #define PCIE_GLI_9767_CFG 0x8A0
> #define PCIE_GLI_9767_CFG_LOW_PWR_OFF BIT(12)
>
> +#define PCIE_GLI_9767_COMBO_MUX_CTL 0x8C8
> +#define PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN BIT(6)
> +#define PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN BIT(10)
> +
> #define PCIE_GLI_9767_PWR_MACRO_CTL 0x8D0
> #define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0)
> #define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12)
> @@ -181,6 +185,26 @@
> #define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21)
> #define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30)
>
> +#define PCIE_GLI_9767_SDHC_CAP 0x91C
> +#define PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT BIT(5)
> +
> +#define PCIE_GLI_9767_SD_EXPRESS_CTL 0x940
> +#define PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE BIT(0)
> +#define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1)
> +
> +#define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944
> +#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME GENMASK(23, 16)
> +#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE 0x64
> +
> +#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2 0x950
> +#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE BIT(0)
> +
> +#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2 0x954
> +#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN BIT(0)
> +
> +#define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2 0x958
> +#define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN BIT(0)
> +
> #define PCIE_GLI_9767_SD_PLL_CTL 0x938
> #define PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV GENMASK(9, 0)
> #define PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV GENMASK(15, 12)
> @@ -935,6 +959,85 @@ static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask)
> gli_set_9767(host);
> }
>
> +static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios)
> +{
> + struct sdhci_host *host = mmc_priv(mmc);
> + struct sdhci_pci_slot *slot = sdhci_priv(host);
> + struct pci_dev *pdev;
> + u32 value;
> + int i;
> +
> + pdev = slot->chip->pdev;
> +
> + if (mmc->ops->get_ro(mmc)) {
> + mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);
> + return 0;
> + }
> +
> + gl9767_vhs_write(pdev);
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, &value);
> + value &= ~(PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN | PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN);
> + pci_write_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, value);
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value);
> + value &= ~PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME;
> + value |= FIELD_PREP(PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME,
> + PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE);
> + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value);
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);
> + value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE;
> + pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, value);
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, &value);
> + value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN;
> + pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, value);
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, &value);
> + value |= PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN;
> + pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, value);
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
> + value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;
> + pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
> +
> + value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> + value &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN);
> + sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);
> +
> + value = sdhci_readb(host, SDHCI_POWER_CONTROL);
> + value |= ((SDHCI_POWER_180 | SDHCI_POWER_ON) << 4);
> + sdhci_writeb(host, value, SDHCI_POWER_CONTROL);
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
> + value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE;
> + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
> +
> + for (i = 0; i < 2; i++) {
> + msleep(10);
> + pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);
> + if (value & PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE) {
> + pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2,
> + value);
> + break;
> + }
> + }
> +
> + pci_read_config_dword(pdev, PCIE_GLI_9767_SDHC_CAP, &value);
> + if ((value & PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT) == PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT) {
> + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
> + value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE;
> + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
> + } else {
> + mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);
> + }
> +
> + gl9767_vhs_read(pdev);
> +
> + return 0;
> +}
> +
> static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
> {
> struct sdhci_host *host = slot->host;
> @@ -967,6 +1070,8 @@ static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot)
> gl9767_hw_setting(slot);
> gli_pcie_enable_msi(slot);
> slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
> + host->mmc->caps2 |= MMC_CAP2_SD_EXP;
> + host->mmc_host_ops.init_sd_express = gl9767_init_sd_express;
> sdhci_enable_v4_mode(host);
>
> return 0;
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH V2 3/3] mmc: sdhci-pci-gli: Add support SD Express card for GL9767
2023-05-31 7:14 ` Adrian Hunter
@ 2023-05-31 9:45 ` Victor Shih
0 siblings, 0 replies; 9+ messages in thread
From: Victor Shih @ 2023-05-31 9:45 UTC (permalink / raw)
To: Adrian Hunter
Cc: ulf.hansson, linux-mmc, linux-kernel, benchuanggli, HL.Liu,
Greg.tu, Ben Chuang, Victor Shih
Hi, Adrian
On Wed, May 31, 2023 at 3:15 PM Adrian Hunter <adrian.hunter@intel.com> wrote:
>
> On 30/05/23 12:53, Victor Shih wrote:
> > From: Victor Shih <victor.shih@genesyslogic.com.tw>
> >
> > Add support SD Express card for GL9767. The workflow of the
> > SD Express card in GL9767 is as below.
> > 1. GL9767 operates in SD mode and set MMC_CAP2_SD_EXP flag.
> > 2. If card is inserted, Host send CMD8 to ask the capabilities
> > of the card.
> > 3. If the card has PCIe capability, then init_sd_express()
> > will be invoked.
> > 4. If the card has been put in write protect state then the
> > SD features supported by SD mode but not supported by
> > PCIe mode, therefore GL9767 switch to SD mode.
> > 5. If the card has not been put in write protect state then
> > GL9767 switch from SD mode to PCIe/NVMe mode and mmc driver
> > handover control to NVMe driver.
> > 6. If card is removed, GL9767 will return to SD mode.
> >
> > Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
> > Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
>
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
>
Excuse me, I will adjust the order of definitions and modify the
if-else condition
and content in gl9767_init_sd_express() function, please help to review
it once, thank you.
> > ---
> > drivers/mmc/host/sdhci-pci-gli.c | 105 +++++++++++++++++++++++++++++++
> > 1 file changed, 105 insertions(+)
> >
> > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> > index 178253a7e86f..c7fa92fdadcd 100644
> > --- a/drivers/mmc/host/sdhci-pci-gli.c
> > +++ b/drivers/mmc/host/sdhci-pci-gli.c
> > @@ -164,6 +164,10 @@
> > #define PCIE_GLI_9767_CFG 0x8A0
> > #define PCIE_GLI_9767_CFG_LOW_PWR_OFF BIT(12)
> >
> > +#define PCIE_GLI_9767_COMBO_MUX_CTL 0x8C8
> > +#define PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN BIT(6)
> > +#define PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN BIT(10)
> > +
> > #define PCIE_GLI_9767_PWR_MACRO_CTL 0x8D0
> > #define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0)
> > #define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12)
> > @@ -181,6 +185,26 @@
> > #define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21)
> > #define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30)
> >
> > +#define PCIE_GLI_9767_SDHC_CAP 0x91C
> > +#define PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT BIT(5)
> > +
> > +#define PCIE_GLI_9767_SD_EXPRESS_CTL 0x940
> > +#define PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE BIT(0)
> > +#define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1)
> > +
> > +#define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944
> > +#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME GENMASK(23, 16)
> > +#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE 0x64
> > +
> > +#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2 0x950
> > +#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE BIT(0)
> > +
> > +#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2 0x954
> > +#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN BIT(0)
> > +
> > +#define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2 0x958
> > +#define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN BIT(0)
> > +
> > #define PCIE_GLI_9767_SD_PLL_CTL 0x938
> > #define PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV GENMASK(9, 0)
> > #define PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV GENMASK(15, 12)
> > @@ -935,6 +959,85 @@ static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask)
> > gli_set_9767(host);
> > }
> >
> > +static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios)
> > +{
> > + struct sdhci_host *host = mmc_priv(mmc);
> > + struct sdhci_pci_slot *slot = sdhci_priv(host);
> > + struct pci_dev *pdev;
> > + u32 value;
> > + int i;
> > +
> > + pdev = slot->chip->pdev;
> > +
> > + if (mmc->ops->get_ro(mmc)) {
> > + mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);
> > + return 0;
> > + }
> > +
> > + gl9767_vhs_write(pdev);
> > +
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, &value);
> > + value &= ~(PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN | PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN);
> > + pci_write_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, value);
> > +
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value);
> > + value &= ~PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME;
> > + value |= FIELD_PREP(PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME,
> > + PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE);
> > + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value);
> > +
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);
> > + value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE;
> > + pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, value);
> > +
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, &value);
> > + value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN;
> > + pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, value);
> > +
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, &value);
> > + value |= PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN;
> > + pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, value);
> > +
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
> > + value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;
> > + pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
> > +
> > + value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
> > + value &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN);
> > + sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);
> > +
> > + value = sdhci_readb(host, SDHCI_POWER_CONTROL);
> > + value |= ((SDHCI_POWER_180 | SDHCI_POWER_ON) << 4);
> > + sdhci_writeb(host, value, SDHCI_POWER_CONTROL);
> > +
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
> > + value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE;
> > + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
> > +
> > + for (i = 0; i < 2; i++) {
> > + msleep(10);
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);
> > + if (value & PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE) {
> > + pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2,
> > + value);
> > + break;
> > + }
> > + }
> > +
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_SDHC_CAP, &value);
> > + if ((value & PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT) == PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT) {
> > + pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
> > + value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE;
> > + pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
> > + } else {
> > + mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);
> > + }
> > +
> > + gl9767_vhs_read(pdev);
> > +
> > + return 0;
> > +}
> > +
> > static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
> > {
> > struct sdhci_host *host = slot->host;
> > @@ -967,6 +1070,8 @@ static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot)
> > gl9767_hw_setting(slot);
> > gli_pcie_enable_msi(slot);
> > slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
> > + host->mmc->caps2 |= MMC_CAP2_SD_EXP;
> > + host->mmc_host_ops.init_sd_express = gl9767_init_sd_express;
> > sdhci_enable_v4_mode(host);
> >
> > return 0;
>
Thanks, Victor Shih
^ permalink raw reply [flat|nested] 9+ messages in thread