From: <Tudor.Ambarus@microchip.com>
To: <vigneshr@ti.com>, <boris.brezillon@collabora.com>,
<marek.vasut@gmail.com>, <miquel.raynal@bootlin.com>,
<richard@nod.at>, <linux-mtd@lists.infradead.org>
Cc: linux-aspeed@lists.ozlabs.org, andrew@aj.id.au,
linux-kernel@vger.kernel.org, vz@mleia.com,
linux-mediatek@lists.infradead.org, joel@jms.id.au,
matthias.bgg@gmail.com, computersforpeace@gmail.com,
dwmw2@infradead.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()
Date: Fri, 20 Sep 2019 05:23:26 +0000 [thread overview]
Message-ID: <06a6e4e8-6802-3f85-ec3c-6295cd703c85@microchip.com> (raw)
In-Reply-To: <dceca616-2b98-9bc8-73e4-32fb06fc753d@ti.com>
Hi, Vignesh,
On 09/19/2019 05:33 PM, Vignesh Raghavendra wrote:
> External E-Mail
>
>
> Hi Tudor
>
> [...]
>
> On 17-Sep-19 9:25 PM, Tudor.Ambarus@microchip.com wrote:
>> +static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 status_new,
>> + u8 mask)
>> +{
>> + int ret;
>> + u8 *sr_cr = nor->bouncebuf;
>> + u8 cr_written;
>> +
>> + /* Make sure we don't overwrite the contents of Status Register 2. */
>> + if (!(nor->flags & SNOR_F_NO_READ_CR)) {
>
> Assuming SNOR_F_NO_READ_CR is not set...
>
>> + ret = spi_nor_read_cr(nor, &sr_cr[1]);
>> + if (ret)
>> + return ret;
>> + } else if (nor->flash.quad_enable) {
>> + /*
>> + * If the Status Register 2 Read command (35h) is not
>> + * supported, we should at least be sure we don't
>> + * change the value of the SR2 Quad Enable bit.
>> + *
>> + * We can safely assume that when the Quad Enable method is
>> + * set, the value of the QE bit is one, as a consequence of the
>> + * nor->flash.quad_enable() call.
>> + *
>> + * We can safely assume that the Quad Enable bit is present in
>> + * the Status Register 2 at BIT(1). According to the JESD216
>> + * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit
>> + * Write Status (01h) command is available just for the cases
>> + * in which the QE bit is described in SR2 at BIT(1).
>> + */
>> + sr_cr[1] = CR_QUAD_EN_SPAN;
>> + } else {
>> + sr_cr[1] = 0;
>> + }
>> +
>
> CR_QUAD_EN_SPAN will not be in sr_cr[1] when we reach here. So code
> won't enable quad mode.
>
I get the problem now. spi_nor_write_16bit_sr_and_check() does not modify the
value of the QE bit, which is good in the lock/unlock() case. We want to
lock/unlock() without enabling or disabling the Quad Mode.
As you found, the problem comes later in spi_nor_sr2_bit1_quad_enable() because
I use there spi_nor_write_16bit_sr_and_check() which keeps the value of the QE
bit, without setting it to one, so the spi_nor_sr2_bit1_quad_enable() did not
enable the Quad Mode if not previously enabled.
What I'll do is to introduce a new argument to:
static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 status_new,
u8 mask, bool set_quad_enable)
and do a
if (set_quad_enable)
sr_cr[1] |= CR_QUAD_EN_SPAN;
after initializing sr_cr[1]
The lock/unlock() methods will call the function with set_quad_enable being
false (we don't want to modify the QE value), and the
spi_nor_sr2_bit1_quad_enable() will call it with set_quad_enable being true, we
want to set QE to one (we don't care of the QE bit previous value).
We'll avoid code duplication, lock/unlock() and spi_nor_sr2_bit1_quad_enable()
calling the same method.
Cheers,
ta
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next prev parent reply other threads:[~2019-09-20 5:24 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 01/23] mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignment Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 02/23] mtd: spi-nor: Introduce 'struct spi_nor_controller_ops' Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 03/23] mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definition Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 04/23] mtd: spi-nor: Rename nor->params to nor->flash Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 05/23] mtd: spi-nor: Rework read_sr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 06/23] mtd: spi-nor: Rework read_fsr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 07/23] mtd: spi-nor: Rework read_cr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 08/23] mtd: spi-nor: Rework write_enable/disable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 09/23] mtd: spi-nor: Fix retlen handling in sst_write() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 10/23] mtd: spi-nor: Rework write_sr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 11/23] mtd: spi-nor: Rework spi_nor_read/write_sr2() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 12/23] mtd: spi-nor: Report error in spi_nor_xread_sr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 13/23] mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 14/23] mtd: spi-nor: Drop duplicated new line Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 15/23] mtd: spi-nor: Drop spansion_quad_enable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 16/23] mtd: spi-nor: Fix errno on quad_enable methods Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Tudor.Ambarus
2019-09-19 14:33 ` Vignesh Raghavendra
2019-09-19 15:54 ` Tudor.Ambarus
2019-09-20 5:23 ` Tudor.Ambarus [this message]
2019-09-17 15:55 ` [PATCH 18/23] mtd: spi-nor: Rework macronix_quad_enable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 19/23] mtd: spi-nor: Rework spansion(_no)_read_cr_quad_enable() Tudor.Ambarus
2019-09-19 17:34 ` Vignesh Raghavendra
2019-09-20 4:42 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 20/23] mtd: spi-nor: Update sr2_bit7_quad_enable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 21/23] mtd: spi-nor: Rework the disabling of block write protection Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 22/23] mtd: spi-nor: Add Global Block Unlock support Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 23/23] mtd: spi-nor: Unlock global block protection on sst26vf064b Tudor.Ambarus
2019-09-19 14:37 ` [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Vignesh Raghavendra
2019-09-19 16:07 ` Tudor.Ambarus
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