From: Vignesh Raghavendra <vigneshr@ti.com>
To: <Tudor.Ambarus@microchip.com>, <boris.brezillon@collabora.com>,
<marek.vasut@gmail.com>, <miquel.raynal@bootlin.com>,
<richard@nod.at>, <linux-mtd@lists.infradead.org>
Cc: linux-aspeed@lists.ozlabs.org, andrew@aj.id.au,
linux-kernel@vger.kernel.org, vz@mleia.com,
linux-mediatek@lists.infradead.org, joel@jms.id.au,
matthias.bgg@gmail.com, computersforpeace@gmail.com,
dwmw2@infradead.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()
Date: Thu, 19 Sep 2019 20:03:34 +0530 [thread overview]
Message-ID: <dceca616-2b98-9bc8-73e4-32fb06fc753d@ti.com> (raw)
In-Reply-To: <20190917155426.7432-18-tudor.ambarus@microchip.com>
Hi Tudor
[...]
On 17-Sep-19 9:25 PM, Tudor.Ambarus@microchip.com wrote:
> +static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 status_new,
> + u8 mask)
> +{
> + int ret;
> + u8 *sr_cr = nor->bouncebuf;
> + u8 cr_written;
> +
> + /* Make sure we don't overwrite the contents of Status Register 2. */
> + if (!(nor->flags & SNOR_F_NO_READ_CR)) {
Assuming SNOR_F_NO_READ_CR is not set...
> + ret = spi_nor_read_cr(nor, &sr_cr[1]);
> + if (ret)
> + return ret;
> + } else if (nor->flash.quad_enable) {
> + /*
> + * If the Status Register 2 Read command (35h) is not
> + * supported, we should at least be sure we don't
> + * change the value of the SR2 Quad Enable bit.
> + *
> + * We can safely assume that when the Quad Enable method is
> + * set, the value of the QE bit is one, as a consequence of the
> + * nor->flash.quad_enable() call.
> + *
> + * We can safely assume that the Quad Enable bit is present in
> + * the Status Register 2 at BIT(1). According to the JESD216
> + * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit
> + * Write Status (01h) command is available just for the cases
> + * in which the QE bit is described in SR2 at BIT(1).
> + */
> + sr_cr[1] = CR_QUAD_EN_SPAN;
> + } else {
> + sr_cr[1] = 0;
> + }
> +
CR_QUAD_EN_SPAN will not be in sr_cr[1] when we reach here. So code
won't enable quad mode.
> + sr_cr[0] = status_new;
> +
> + ret = spi_nor_write_sr(nor, sr_cr, 2);
> + if (ret)
> + return ret;
> +
> + cr_written = sr_cr[1];
> +
> + ret = spi_nor_read_sr(nor, &sr_cr[0]);
> + if (ret)
> + return ret;
> +
> + if ((sr_cr[0] & mask) != (status_new & mask)) {
> + dev_err(nor->dev, "Read back test failed\n");
> + return -EIO;
> + }
> +
> + if (nor->flags & SNOR_F_NO_READ_CR)
> + return 0;
> +
> + ret = spi_nor_read_cr(nor, &sr_cr[1]);
> + if (ret)
> + return ret;
> +
> + if (cr_written != sr_cr[1]) {
> + dev_err(nor->dev, "Read back test failed\n");
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
Regards
Vignesh
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2019-09-19 14:34 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-17 15:54 [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 01/23] mtd: spi-nor: hisi-sfc: Drop nor->erase NULL assignment Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 02/23] mtd: spi-nor: Introduce 'struct spi_nor_controller_ops' Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 03/23] mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definition Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 04/23] mtd: spi-nor: Rename nor->params to nor->flash Tudor.Ambarus
2019-09-17 15:54 ` [PATCH 05/23] mtd: spi-nor: Rework read_sr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 06/23] mtd: spi-nor: Rework read_fsr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 07/23] mtd: spi-nor: Rework read_cr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 08/23] mtd: spi-nor: Rework write_enable/disable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 09/23] mtd: spi-nor: Fix retlen handling in sst_write() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 10/23] mtd: spi-nor: Rework write_sr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 11/23] mtd: spi-nor: Rework spi_nor_read/write_sr2() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 12/23] mtd: spi-nor: Report error in spi_nor_xread_sr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 13/23] mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 14/23] mtd: spi-nor: Drop duplicated new line Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 15/23] mtd: spi-nor: Drop spansion_quad_enable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 16/23] mtd: spi-nor: Fix errno on quad_enable methods Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 17/23] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Tudor.Ambarus
2019-09-19 14:33 ` Vignesh Raghavendra [this message]
2019-09-19 15:54 ` Tudor.Ambarus
2019-09-20 5:23 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 18/23] mtd: spi-nor: Rework macronix_quad_enable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 19/23] mtd: spi-nor: Rework spansion(_no)_read_cr_quad_enable() Tudor.Ambarus
2019-09-19 17:34 ` Vignesh Raghavendra
2019-09-20 4:42 ` Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 20/23] mtd: spi-nor: Update sr2_bit7_quad_enable() Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 21/23] mtd: spi-nor: Rework the disabling of block write protection Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 22/23] mtd: spi-nor: Add Global Block Unlock support Tudor.Ambarus
2019-09-17 15:55 ` [PATCH 23/23] mtd: spi-nor: Unlock global block protection on sst26vf064b Tudor.Ambarus
2019-09-19 14:37 ` [PATCH 00/23] mtd: spi-nor: Quad Enable and (un)lock methods Vignesh Raghavendra
2019-09-19 16:07 ` Tudor.Ambarus
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=dceca616-2b98-9bc8-73e4-32fb06fc753d@ti.com \
--to=vigneshr@ti.com \
--cc=Tudor.Ambarus@microchip.com \
--cc=andrew@aj.id.au \
--cc=boris.brezillon@collabora.com \
--cc=computersforpeace@gmail.com \
--cc=dwmw2@infradead.org \
--cc=joel@jms.id.au \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-aspeed@lists.ozlabs.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=linux-mtd@lists.infradead.org \
--cc=marek.vasut@gmail.com \
--cc=matthias.bgg@gmail.com \
--cc=miquel.raynal@bootlin.com \
--cc=richard@nod.at \
--cc=vz@mleia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).