From: Roman Yeryomin <roman@advem.lv>
To: Tudor.Ambarus@microchip.com
Cc: marek.vasut@gmail.com, linux-mtd@lists.infradead.org
Subject: Re: [PATCH 1/2] mtd: spi-nor: fix GigaDevice quad_enable
Date: Wed, 07 Aug 2019 23:10:57 +0300 [thread overview]
Message-ID: <08565a3d0816c8b52e2472718b755e41@advem.lv> (raw)
In-Reply-To: <c80dc6d3-d9de-7e95-f1e0-62dea07ef923@microchip.com>
On 2019-07-28 09:21, Tudor.Ambarus@microchip.com wrote:
> On 07/28/2019 08:48 AM, Tudor.Ambarus@microchip.com wrote:
>> External E-Mail
>>
>>
>> Hi, Roman,
>>
>> On 07/27/2019 12:08 AM, Roman Yeryomin wrote:
>>> External E-Mail
>>>
>>>
>>> According to datasheets all GD devices are capable of quad mode,
>>> which
>>
>> Does any of these flashes implement the Basic Flash Parameter Table?
>> Can't we
>> determine the QE Requirements by parsing BFPT?
>
> GD25Q256D can retrieve the QE requirements from BFPT dword 15. No need
> to set
> the quad_enable pointer when declaring this flash, it will be
> overwritten when
> parsing BFPT.
ok, I see, thanks for the pointer, didn't see that
> GD25Q256C implements JESD216A - just the first 9 dwords of BFPT, and it
> can't
> determine the QE Requirements by parsing the BFPT. That's way we
> explicitly set
> the quad_enable function pointer at flash declaration.
>
>>
>>> is enabled via Status Register-2, bit 1 (S9). This corresponds to
>>> Spansion SR/CR operations. Unfortunately only gd25q256 datasheet is
>>> clear about Quad Enable Requirements (QER), others have no such
>>> information in datasheets.
>>> So define quad_enable for all GD devices to be sure.
>>
>> Which flash did you test?
>
> What you can do is to check which of these flashes can't determine the
> QE
> requirements by parsing BFPT and set the quad_enable just for those who
> can't.
> And it would be preferable to do this just for the flashes that you can
> test.
Unfortunately I don't have the devices. I only studied the datasheets.
Though I do have gd25q512 (the second patch) somewhere. I used it on one
of embedded board prototypes.
I will try to find it and test the BFPT parsing.
>>
>> Cheers,
>> ta
>>
>>> Also gd25q256 is an exception. There are two versions: C and D.
>>> First one uses S6 bit (like described in e27072851bf7d) but the
>>> latter
>>> uses S9 bit like others. To add support for D this should be handled
>>> differently, so, to retain compatibility, leave gd25q256 quad_enable
>>> callback intact.
>>>
>>> Signed-off-by: Roman Yeryomin <roman@advem.lv>
>>> ---
>>> drivers/mtd/spi-nor/spi-nor.c | 6 ++++++
>>> 1 file changed, 6 insertions(+)
>>>
>> ______________________________________________________
>> Linux MTD discussion mailing list
>> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>>
>>
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next prev parent reply other threads:[~2019-08-07 20:11 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-26 21:08 [PATCH 1/2] mtd: spi-nor: fix GigaDevice quad_enable Roman Yeryomin
2019-07-28 5:48 ` Tudor.Ambarus
2019-07-28 6:21 ` Tudor.Ambarus
2019-08-07 20:10 ` Roman Yeryomin [this message]
2019-07-28 8:47 ` Sergei Shtylyov
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