* [PATCH V3 0/6] add the GPMI controller driver for IMX23/IMX28
@ 2011-03-30 8:40 Huang Shijie
2011-03-30 8:40 ` [PATCH V3 1/6] ARM: add GPMI support for imx23/imx28 Huang Shijie
` (5 more replies)
0 siblings, 6 replies; 31+ messages in thread
From: Huang Shijie @ 2011-03-30 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux, David.Woodhouse, dedekind1, Huang Shijie, linux-mtd,
ffainelli, shijie8
The general-purpose media interface(GPMI) controller is a flexible interface
to up to several NAND flashs.
The Bose Ray-Choudhury Hocquenghem(BCH) module is a hardware ECC accelerator.
With the help of BCH, the GPMI controller can choose to do the hardware ECC or
not.
This driver is based the Shawn Guo's DMA patches for IMX23/IMX28,
please refer to :
http://git.infradead.org/users/vkoul/slave-dma.git/commit/a580b8c5429a624d120cd603e1498bf676e2b4da
v2 --> v3:
[0] merge the imx23 and imx28 into one file(including the header file).
[1] remove the unuse registers in the headers.
[2] fix DMA bugs
[3] add bus width field to nand_attr{}
[4] others
v1 --> v2:
[0] merge the common files into the gpmi-nfc-main.c
[1] change the code to get the clock.
[2] remove the timing in the nand_device_info{}
[3] fix DMA errors
[4] add the nand_device_info.[ch] to generic code
[5] use the chip->onfi_version for the ONFI nand
[6] useless init
[7] others
Huang Shijie (6):
ARM: add GPMI support for imx23/imx28
dmaengine: change the flags of request_irq()
MTD : add the database for the NANDs
MTD : add the common code for GPMI controller driver
MTD: add support for imx23 and imx28
MTD : add GPMI driver in the config and Makefile
arch/arm/mach-mxs/Kconfig | 2 +
arch/arm/mach-mxs/clock-mx23.c | 3 +
arch/arm/mach-mxs/clock-mx28.c | 3 +
arch/arm/mach-mxs/devices-mx23.h | 3 +
arch/arm/mach-mxs/devices-mx28.h | 3 +
arch/arm/mach-mxs/devices/Kconfig | 3 +
arch/arm/mach-mxs/devices/Makefile | 1 +
arch/arm/mach-mxs/devices/platform-gpmi.c | 140 ++
arch/arm/mach-mxs/include/mach/devices-common.h | 4 +
arch/arm/mach-mxs/include/mach/gpmi-nfc.h | 62 +
arch/arm/mach-mxs/mach-mx23evk.c | 37 +
arch/arm/mach-mxs/mach-mx28evk.c | 37 +
drivers/dma/mxs-dma.c | 2 +-
drivers/mtd/nand/Kconfig | 10 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/gpmi-nfc/Makefile | 6 +
drivers/mtd/nand/gpmi-nfc/bch-mx23-mx28.h | 88 +
drivers/mtd/nand/gpmi-nfc/gpmi-mx23-mx28.h | 163 ++
drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c | 2451 +++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h | 549 +++++
drivers/mtd/nand/gpmi-nfc/hal-mx23-mx28.c | 562 ++++++
drivers/mtd/nand/gpmi-nfc/rom-mx23.c | 300 +++
drivers/mtd/nand/gpmi-nfc/rom-mx28.c | 66 +
drivers/mtd/nand/nand_device_info.c | 157 ++
drivers/mtd/nand/nand_device_info.h | 88 +
25 files changed, 4740 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-mxs/devices/platform-gpmi.c
create mode 100644 arch/arm/mach-mxs/include/mach/gpmi-nfc.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/Makefile
create mode 100644 drivers/mtd/nand/gpmi-nfc/bch-mx23-mx28.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-mx23-mx28.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-mx23-mx28.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-mx23.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-mx28.c
create mode 100644 drivers/mtd/nand/nand_device_info.c
create mode 100644 drivers/mtd/nand/nand_device_info.h
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH V3 1/6] ARM: add GPMI support for imx23/imx28
2011-03-30 8:40 [PATCH V3 0/6] add the GPMI controller driver for IMX23/IMX28 Huang Shijie
@ 2011-03-30 8:40 ` Huang Shijie
2011-03-30 8:40 ` [PATCH V3 2/6] dmaengine: change the flags of request_irq() Huang Shijie
` (4 subsequent siblings)
5 siblings, 0 replies; 31+ messages in thread
From: Huang Shijie @ 2011-03-30 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux, David.Woodhouse, dedekind1, Huang Shijie, linux-mtd,
ffainelli, shijie8
add the clock and iomux initialization for GPMI in the imx23 and imx28.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
arch/arm/mach-mxs/Kconfig | 2 +
arch/arm/mach-mxs/clock-mx23.c | 3 +
arch/arm/mach-mxs/clock-mx28.c | 3 +
arch/arm/mach-mxs/devices-mx23.h | 3 +
arch/arm/mach-mxs/devices-mx28.h | 3 +
arch/arm/mach-mxs/devices/Kconfig | 3 +
arch/arm/mach-mxs/devices/Makefile | 1 +
arch/arm/mach-mxs/devices/platform-gpmi.c | 140 +++++++++++++++++++++++
arch/arm/mach-mxs/include/mach/devices-common.h | 4 +
arch/arm/mach-mxs/include/mach/gpmi-nfc.h | 62 ++++++++++
arch/arm/mach-mxs/mach-mx23evk.c | 37 ++++++
arch/arm/mach-mxs/mach-mx28evk.c | 37 ++++++
12 files changed, 298 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-mxs/devices/platform-gpmi.c
create mode 100644 arch/arm/mach-mxs/include/mach/gpmi-nfc.h
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 4f6f174..e034666 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -22,6 +22,7 @@ config MACH_MX23EVK
select SOC_IMX23
select MXS_HAVE_AMBA_DUART
select MXS_HAVE_PLATFORM_AUART
+ select MXS_HAVE_PLATFORM_GPMI
select MXS_HAVE_PLATFORM_MXSFB
default y
help
@@ -35,6 +36,7 @@ config MACH_MX28EVK
select MXS_HAVE_PLATFORM_AUART
select MXS_HAVE_PLATFORM_FEC
select MXS_HAVE_PLATFORM_FLEXCAN
+ select MXS_HAVE_PLATFORM_GPMI
select MXS_HAVE_PLATFORM_MXSFB
select MXS_OCOTP
default y
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index d133c7f..e99af2f 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -29,6 +29,7 @@
#include <mach/mx23.h>
#include <mach/common.h>
#include <mach/clock.h>
+#include <mach/gpmi-nfc.h>
#include "regs-clkctrl-mx23.h"
@@ -442,6 +443,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
/* for amba-pl011 driver */
_REGISTER_CLOCK("duart", NULL, uart_clk)
+ _REGISTER_CLOCK(GPMI_NFC_DRIVER_NAME, NULL, gpmi_clk)
_REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
_REGISTER_CLOCK("rtc", NULL, rtc_clk)
_REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
@@ -533,6 +535,7 @@ int __init mx23_clocks_init(void)
clk_enable(&xbus_clk);
clk_enable(&emi_clk);
clk_enable(&uart_clk);
+ clk_enable(&gpmi_clk);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 5e489a2..3e8bba7 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -29,6 +29,7 @@
#include <mach/mx28.h>
#include <mach/common.h>
#include <mach/clock.h>
+#include <mach/gpmi-nfc.h>
#include "regs-clkctrl-mx28.h"
@@ -607,6 +608,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
/* for amba-pl011 driver */
_REGISTER_CLOCK("duart", NULL, uart_clk)
+ _REGISTER_CLOCK(GPMI_NFC_DRIVER_NAME, NULL, gpmi_clk)
_REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
_REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
_REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
@@ -749,6 +751,7 @@ int __init mx28_clocks_init(void)
clk_enable(&xbus_clk);
clk_enable(&emi_clk);
clk_enable(&uart_clk);
+ clk_enable(&gpmi_clk);
clk_set_parent(&lcdif_clk, &ref_pix_clk);
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index c7e14f4..349fb1d 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -16,6 +16,9 @@ extern const struct amba_device mx23_duart_device __initconst;
#define mx23_add_duart() \
mxs_add_duart(&mx23_duart_device)
+extern const struct gpmi_nfc_platform_data gpmi_platform_data_imx23 __initconst;
+#define mx23_add_gpmi() mxs_add_gpmi(&gpmi_platform_data_imx23)
+
extern const struct mxs_auart_data mx23_auart_data[] __initconst;
#define mx23_add_auart(id) mxs_add_auart(&mx23_auart_data[id])
#define mx23_add_auart0() mx23_add_auart(0)
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 9d08555..ed6427b 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -16,6 +16,9 @@ extern const struct amba_device mx28_duart_device __initconst;
#define mx28_add_duart() \
mxs_add_duart(&mx28_duart_device)
+extern const struct gpmi_nfc_platform_data gpmi_platform_data_imx28 __initconst;
+#define mx28_add_gpmi() mxs_add_gpmi(&gpmi_platform_data_imx28)
+
extern const struct mxs_auart_data mx28_auart_data[] __initconst;
#define mx28_add_auart(id) mxs_add_auart(&mx28_auart_data[id])
#define mx28_add_auart0() mx28_add_auart(0)
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index 1451ad0..81e99ce 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -5,6 +5,9 @@ config MXS_HAVE_AMBA_DUART
config MXS_HAVE_PLATFORM_AUART
bool
+config MXS_HAVE_PLATFORM_GPMI
+ bool
+
config MXS_HAVE_PLATFORM_FEC
bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
index 0d9bea3..8a7c2c8 100644
--- a/arch/arm/mach-mxs/devices/Makefile
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
obj-y += platform-dma.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_GPMI) += platform-gpmi.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
diff --git a/arch/arm/mach-mxs/devices/platform-gpmi.c b/arch/arm/mach-mxs/devices/platform-gpmi.c
new file mode 100644
index 0000000..2de0dcd
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-gpmi.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <asm/sizes.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/gpmi-nfc.h>
+#include <mach/devices-common.h>
+
+#ifdef CONFIG_SOC_IMX23
+const struct gpmi_nfc_platform_data gpmi_platform_data_imx23 __initconst = {
+ .min_prop_delay_in_ns = 5,
+ .max_prop_delay_in_ns = 9,
+ .max_chip_count = 1,
+ .boot_area_size_in_bytes = 20 * SZ_1M,
+};
+
+const struct resource res_imx23[] __initconst = {
+ { /* GPMI */
+ .start = MX23_GPMI_BASE_ADDR,
+ .end = MX23_GPMI_BASE_ADDR + SZ_8K - 1,
+ .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX23_INT_GPMI_ATTENTION,
+ .end = MX23_INT_GPMI_ATTENTION,
+ .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ }, { /* BCH */
+ .start = MX23_BCH_BASE_ADDR,
+ .end = MX23_BCH_BASE_ADDR + SZ_8K - 1,
+ .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX23_INT_BCH,
+ .end = MX23_INT_BCH,
+ .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ }, { /* DMA */
+ .start = MX23_DMA_GPMI0,
+ .end = MX23_DMA_GPMI3,
+ .name = GPMI_NFC_DMA_CHANNELS_RES_NAME,
+ .flags = IORESOURCE_DMA,
+ }, {
+ .start = MX23_INT_GPMI_DMA,
+ .end = MX23_INT_GPMI_DMA,
+ .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+#endif
+
+#ifdef CONFIG_SOC_IMX28
+const struct gpmi_nfc_platform_data gpmi_platform_data_imx28 __initconst = {
+ .min_prop_delay_in_ns = 5,
+ .max_prop_delay_in_ns = 9,
+ .max_chip_count = 1,
+ .boot_area_size_in_bytes = 20 * SZ_1M,
+};
+
+const struct resource res_imx28[] __initconst = {
+ { /* GPMI */
+ .start = MX28_GPMI_BASE_ADDR,
+ .end = MX28_GPMI_BASE_ADDR + SZ_8K - 1,
+ .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX28_INT_GPMI,
+ .end = MX28_INT_GPMI,
+ .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ }, { /* BCH */
+ .start = MX28_BCH_BASE_ADDR,
+ .end = MX28_BCH_BASE_ADDR + SZ_8K - 1,
+ .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX28_INT_BCH,
+ .end = MX28_INT_BCH,
+ .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ }, { /* DMA */
+ .start = MX28_DMA_GPMI0,
+ .end = MX28_DMA_GPMI7,
+ .name = GPMI_NFC_DMA_CHANNELS_RES_NAME,
+ .flags = IORESOURCE_DMA,
+ }, {
+ .start = MX28_INT_GPMI_DMA,
+ .end = MX28_INT_GPMI_DMA,
+ .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+#endif
+
+static struct resource *__init get_res(int *res_size)
+{
+#ifdef CONFIG_SOC_IMX23
+ if (cpu_is_mx23()) {
+ *res_size = ARRAY_SIZE(res_imx23);
+ return (struct resource *)res_imx23;
+ }
+#endif
+
+#ifdef CONFIG_SOC_IMX28
+ if (cpu_is_mx28()) {
+ *res_size = ARRAY_SIZE(res_imx28);
+ return (struct resource *)res_imx28;
+ }
+#endif
+ BUG();
+ return NULL;
+}
+
+struct platform_device *__init
+mxs_add_gpmi(const struct gpmi_nfc_platform_data *data)
+{
+ struct resource *res;
+ int res_size;
+
+ res = get_res(&res_size);
+
+ return mxs_add_platform_device_dmamask(GPMI_NFC_DRIVER_NAME, -1,
+ res, res_size,
+ data, sizeof(*data), DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index 71f2448..1f05503 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -30,6 +30,10 @@ int __init mxs_add_amba_device(const struct amba_device *dev);
/* duart */
int __init mxs_add_duart(const struct amba_device *dev);
+/* GPMI */
+#include <mach/gpmi-nfc.h>
+struct platform_device *__init mxs_add_gpmi(
+ const struct gpmi_nfc_platform_data *data);
/* auart */
struct mxs_auart_data {
int id;
diff --git a/arch/arm/mach-mxs/include/mach/gpmi-nfc.h b/arch/arm/mach-mxs/include/mach/gpmi-nfc.h
new file mode 100644
index 0000000..271d032
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/gpmi-nfc.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __INCLUDE_LINUX_DEVICE_H
+#define __INCLUDE_LINUX_DEVICE_H
+
+#define GPMI_NFC_DRIVER_NAME "gpmi-nfc"
+
+/* Resource names for the GPMI NFC driver. */
+#define GPMI_NFC_GPMI_REGS_ADDR_RES_NAME "GPMI NFC GPMI Registers"
+#define GPMI_NFC_GPMI_INTERRUPT_RES_NAME "GPMI NFC GPMI Interrupt"
+#define GPMI_NFC_BCH_REGS_ADDR_RES_NAME "GPMI NFC BCH Registers"
+#define GPMI_NFC_BCH_INTERRUPT_RES_NAME "GPMI NFC BCH Interrupt"
+#define GPMI_NFC_DMA_CHANNELS_RES_NAME "GPMI NFC DMA Channels"
+#define GPMI_NFC_DMA_INTERRUPT_RES_NAME "GPMI NFC DMA Interrupt"
+
+/**
+ * struct gpmi_nfc_platform_data - GPMI NFC driver platform data.
+ *
+ * This structure communicates platform-specific information to the GPMI NFC
+ * driver that can't be expressed as resources.
+ *
+ * @min_prop_delay_in_ns: Minimum propagation delay of GPMI signals to and
+ * from the NAND Flash device, in nanoseconds.
+ * @max_prop_delay_in_ns: Maximum propagation delay of GPMI signals to and
+ * from the NAND Flash device, in nanoseconds.
+ * @max_chip_count: The maximum number of chips for which the driver
+ * should configure the hardware. This value most
+ * likely reflects the number of pins that are
+ * connected to a NAND Flash device. If this is
+ * greater than the SoC hardware can support, the
+ * driver will print a message and fail to initialize.
+ * @boot_area_size_in_bytes: The amount of space reserved for each boot area.
+ * Note that some Boot ROMs call for multiple boot
+ * areas. If this value is zero, the driver will not
+ * construct special partitions for boot areas.
+ */
+struct gpmi_nfc_platform_data {
+ /* NAND Flash information. */
+ unsigned int min_prop_delay_in_ns;
+ unsigned int max_prop_delay_in_ns;
+ unsigned int max_chip_count;
+
+ /* boot area */
+ uint32_t boot_area_size_in_bytes;
+};
+#endif
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index a66994f..db715f9 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -34,6 +34,42 @@ static const iomux_cfg_t mx23evk_pads[] __initconst = {
MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
+ /* gpmi */
+ MX23_PAD_GPMI_D00__GPMI_D00 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D01__GPMI_D01 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D02__GPMI_D02 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D03__GPMI_D03 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D04__GPMI_D04 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D05__GPMI_D05 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D06__GPMI_D06 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D07__GPMI_D07 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_CLE__GPMI_CLE |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_ALE__GPMI_ALE |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_WPN__GPMI_WPN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_WRN__GPMI_WRN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_RDN__GPMI_RDN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_RDY0__GPMI_RDY0 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_RDY1__GPMI_RDY1 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_CE0N__GPMI_CE0N |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_CE1N__GPMI_CE1N |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
/* auart */
MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
@@ -108,6 +144,7 @@ static void __init mx23evk_init(void)
mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
mx23_add_duart();
+ mx23_add_gpmi();
mx23_add_auart0();
ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index 08002d0..cf8ddcb 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -39,6 +39,42 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = {
MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
+ /* gpmi */
+ MX28_PAD_GPMI_D00__GPMI_D0 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D01__GPMI_D1 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D02__GPMI_D2 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D03__GPMI_D3 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D04__GPMI_D4 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D05__GPMI_D5 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D06__GPMI_D6 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D07__GPMI_D7 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_CE0N__GPMI_CE0N |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_CE1N__GPMI_CE1N |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_RDY0__GPMI_READY0 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_RDY1__GPMI_READY1 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_RDN__GPMI_RDN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_WRN__GPMI_WRN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_ALE__GPMI_ALE |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_CLE__GPMI_CLE |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
/* auart0 */
MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
@@ -265,6 +301,7 @@ static void __init mx28evk_init(void)
mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
mx28_add_duart();
+ mx28_add_gpmi();
mx28_add_auart0();
mx28_add_auart3();
--
1.7.0.4
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH V3 2/6] dmaengine: change the flags of request_irq()
2011-03-30 8:40 [PATCH V3 0/6] add the GPMI controller driver for IMX23/IMX28 Huang Shijie
2011-03-30 8:40 ` [PATCH V3 1/6] ARM: add GPMI support for imx23/imx28 Huang Shijie
@ 2011-03-30 8:40 ` Huang Shijie
2011-03-30 9:03 ` Lothar Waßmann
2011-03-30 8:40 ` [PATCH V3 3/6] MTD : add the database for the NANDs Huang Shijie
` (3 subsequent siblings)
5 siblings, 1 reply; 31+ messages in thread
From: Huang Shijie @ 2011-03-30 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux, David.Woodhouse, dedekind1, Huang Shijie, linux-mtd,
ffainelli, shijie8
The GPMI may have many DMA channels, such as the imx23 has
four DMA channels. All these DMA channels share the same interrupt.
So change the flags from '0' to IRQF_SHARED, else there will be
an EBUSY error returns.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/dma/mxs-dma.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index 88aad4f..0ee5b52 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -328,7 +328,7 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
memset(mxs_chan->ccw, 0, PAGE_SIZE);
ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
- 0, "mxs-dma", mxs_dma);
+ IRQF_SHARED, "mxs-dma", mxs_dma);
if (ret)
goto err_irq;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH V3 3/6] MTD : add the database for the NANDs
2011-03-30 8:40 [PATCH V3 0/6] add the GPMI controller driver for IMX23/IMX28 Huang Shijie
2011-03-30 8:40 ` [PATCH V3 1/6] ARM: add GPMI support for imx23/imx28 Huang Shijie
2011-03-30 8:40 ` [PATCH V3 2/6] dmaengine: change the flags of request_irq() Huang Shijie
@ 2011-03-30 8:40 ` Huang Shijie
2011-03-30 8:46 ` Florian Fainelli
2011-03-30 8:40 ` [PATCH V3 4/6] MTD : add the common code for GPMI controller driver Huang Shijie
` (2 subsequent siblings)
5 siblings, 1 reply; 31+ messages in thread
From: Huang Shijie @ 2011-03-30 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux, David.Woodhouse, dedekind1, Huang Shijie, linux-mtd,
ffainelli, shijie8
This is a new database for the NANDs which is searched by the id_bytes.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/nand/nand_device_info.c | 157 +++++++++++++++++++++++++++++++++++
drivers/mtd/nand/nand_device_info.h | 88 +++++++++++++++++++
2 files changed, 245 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/nand_device_info.c
create mode 100644 drivers/mtd/nand/nand_device_info.h
diff --git a/drivers/mtd/nand/nand_device_info.c b/drivers/mtd/nand/nand_device_info.c
new file mode 100644
index 0000000..757ed89
--- /dev/null
+++ b/drivers/mtd/nand/nand_device_info.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <asm/sizes.h>
+#include <linux/mtd/nand.h>
+
+#include "nand_device_info.h"
+
+static const struct nand_device_info samsung_nand[] = {
+ {
+ .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
+ .id_len = 8,
+ .desc = "K9G8G08U0M, K9HAG08U1M",
+ .attr = ATTR(MLC, NAND_BUSWIDTH_8, 1LL * SZ_1G, 128,
+ 2 * SZ_1K + 64, 8, 512),
+ }, {
+ .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
+ .id_len = 8,
+ .desc = "K9LBG08U0D",
+ .attr = ATTR(MLC, NAND_BUSWIDTH_8, 4LL * SZ_1G, 128,
+ 4 * SZ_1K + 218, 16, 512),
+ }, {
+ .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
+ .id_len = 8,
+ .desc = "K9GAG08U0M",
+ .attr = ATTR(MLC, NAND_BUSWIDTH_8, 2LL * SZ_1G, 128,
+ 4 * SZ_1K + 218, 16, 512),
+ }, {
+ /* end of the table. */
+ .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ },
+};
+
+/* macro to get the id bytes */
+#define ID_GET_MFR_CODE(id) ((id)[0])
+
+void nand_device_print_info(struct nand_device_info *info)
+{
+ unsigned i;
+ const char *mfr_name;
+ const char *cell_technology_name;
+ uint64_t chip_size;
+ const char *chip_size_units;
+ unsigned page_size;
+ unsigned oob_size;
+ struct nand_attr *attr = &info->attr;
+
+ /* Prepare the manufacturer name. */
+ mfr_name = "Unknown";
+ for (i = 0; nand_manuf_ids[i].id; i++) {
+ if (nand_manuf_ids[i].id == ID_GET_MFR_CODE(info->id)) {
+ mfr_name = nand_manuf_ids[i].name;
+ break;
+ }
+ }
+
+ /* Prepare the name of the cell technology. */
+ switch (attr->cell_technology) {
+ case SLC:
+ cell_technology_name = "SLC";
+ break;
+ case MLC:
+ cell_technology_name = "MLC";
+ break;
+ default:
+ cell_technology_name = "Unknown";
+ break;
+ }
+
+ /* Prepare the chip size. */
+ if ((attr->chip_size_in_bytes >= SZ_1G) &&
+ !(attr->chip_size_in_bytes % SZ_1G)) {
+ chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1G);
+ chip_size_units = "GiB";
+ } else if ((attr->chip_size_in_bytes >= SZ_1M) &&
+ !(attr->chip_size_in_bytes % SZ_1M)) {
+ chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1M);
+ chip_size_units = "MiB";
+ } else {
+ chip_size = attr->chip_size_in_bytes;
+ chip_size_units = "B";
+ }
+
+ /* Prepare the page geometry. */
+ page_size = (1 << (fls(attr->page_total_size_in_bytes) - 1));
+ oob_size = attr->page_total_size_in_bytes - page_size;
+
+ /* Print the infomation. */
+ pr_info("--------------------------------------\n");
+ pr_info(" NAND device infomation (RAW)\n");
+ pr_info("--------------------------------------\n");
+ pr_info("Manufacturer : %s (0x%02x)\n", mfr_name, info->id[0]);
+ pr_info("Device Code : 0x%02x\n", info->id[1]);
+ pr_info("Cell Technology : %s\n", cell_technology_name);
+ pr_info("Chip Size : %llu %s\n", chip_size, chip_size_units);
+ pr_info("Pages per Block : %u\n", attr->block_size_in_pages);
+ pr_info("Page Geometry : %u+%u\n", page_size, oob_size);
+ pr_info("ECC Strength : %u bits\n", attr->ecc_strength_in_bits);
+ pr_info("ECC Size : %u B\n", attr->ecc_size_in_bytes);
+ pr_info("Description : %s\n", info->desc);
+}
+
+static struct nand_device_info * __init
+search_table(const struct nand_device_info *table, const uint8_t id[])
+{
+ struct nand_device_info *info = (struct nand_device_info *)table;
+
+ while (ID_GET_MFR_CODE(info->id)) {
+ int i;
+
+ /* match all the valid id bytes. Is it too strict? */
+ for (i = 0; i < info->id_len; i++)
+ if (info->id[i] != id[i])
+ break;
+
+ /* found it */
+ if (i == info->id_len)
+ return info;
+ info++;
+ }
+ return NULL;
+}
+
+struct nand_device_mfr_info {
+ uint8_t id;
+ const struct nand_device_info *table;
+};
+
+static const struct nand_device_mfr_info nand_device_mfr_directory[] = {
+ { NAND_MFR_SAMSUNG, samsung_nand },
+ { 0, NULL },
+};
+
+struct nand_device_info *nand_device_get_info(const uint8_t id[])
+{
+ uint8_t mfr_id = ID_GET_MFR_CODE(id);
+ unsigned i;
+
+ for (i = 0; nand_device_mfr_directory[i].id; i++) {
+ if (nand_device_mfr_directory[i].id == mfr_id) {
+ const struct nand_device_info *table;
+
+ table = nand_device_mfr_directory[i].table;
+ return search_table(table, id);
+ }
+ }
+ return NULL;
+}
diff --git a/drivers/mtd/nand/nand_device_info.h b/drivers/mtd/nand/nand_device_info.h
new file mode 100644
index 0000000..15f688d
--- /dev/null
+++ b/drivers/mtd/nand/nand_device_info.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __DRIVERS_NAND_DEVICE_INFO_H
+#define __DRIVERS_NAND_DEVICE_INFO_H
+
+enum nand_device_cell_technology {
+ SLC = 0,
+ MLC = 1,
+};
+
+/**
+ * @cell_technology: The storage cell technology.
+ * @busw: The bus width of the NAND.
+ * @chip_size_in_bytes: The total size of the storage behind a single
+ * chip select, in bytes. Notice that this is *not*
+ * necessarily the total size of the storage in a
+ * *package*, which may contain several chips.
+ * @block_size_in_pages: The number of pages in a block.
+ * @page_total_size_in_bytes: The total size of a page, in bytes, including
+ * both the data and the OOB.
+ * @ecc_strength_in_bits: The strength of the ECC called for by the
+ * manufacturer, in number of correctable bits.
+ * @ecc_size_in_bytes: The size of the data block over which the
+ * manufacturer calls for the given ECC algorithm
+ * and strength.
+ */
+struct nand_attr {
+ /* Technology */
+ enum nand_device_cell_technology cell_technology;
+
+ /* bus width */
+#define NAND_BUSWIDTH_8 0
+ uint32_t busw;
+
+ /* Geometry */
+ uint64_t chip_size_in_bytes;
+ uint32_t block_size_in_pages;
+ uint32_t page_total_size_in_bytes;
+
+ /* ECC */
+ uint16_t ecc_strength_in_bits;
+ uint16_t ecc_size_in_bytes;
+};
+
+#define ID_BYTES (8)
+/*
+ * struct nand_device_info - Information about a single NAND Flash device.
+ *
+ * This structure contains all the *essential* information about a NAND Flash
+ * device, derived from the device's data sheet.
+ */
+struct nand_device_info {
+ /* id */
+ uint8_t id[ID_BYTES];
+ unsigned int id_len;
+
+ /* Description */
+ const char *desc;
+
+ /* attribute*/
+ struct nand_attr attr;
+};
+
+/* macro for the NAND attribute */
+#define ATTR(_a, _b, _c, _d, _e, _f, _g) \
+ { \
+ .cell_technology = (_a), \
+ .busw = (_b), \
+ .chip_size_in_bytes = (_c), \
+ .block_size_in_pages = (_d), \
+ .page_total_size_in_bytes = (_e), \
+ .ecc_strength_in_bits = (_f), \
+ .ecc_size_in_bytes = (_g), \
+ }
+
+struct nand_device_info *nand_device_get_info(const uint8_t id_bytes[]);
+void nand_device_print_info(struct nand_device_info *info);
+#endif
--
1.7.0.4
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH V3 4/6] MTD : add the common code for GPMI controller driver
2011-03-30 8:40 [PATCH V3 0/6] add the GPMI controller driver for IMX23/IMX28 Huang Shijie
` (2 preceding siblings ...)
2011-03-30 8:40 ` [PATCH V3 3/6] MTD : add the database for the NANDs Huang Shijie
@ 2011-03-30 8:40 ` Huang Shijie
2011-03-30 8:40 ` [PATCH V3 5/6] MTD: add support for imx23 and imx28 Huang Shijie
2011-03-30 8:40 ` [PATCH V3 6/6] MTD : add GPMI driver in the config and Makefile Huang Shijie
5 siblings, 0 replies; 31+ messages in thread
From: Huang Shijie @ 2011-03-30 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux, David.Woodhouse, dedekind1, Huang Shijie, linux-mtd,
ffainelli, shijie8
These files contain the common code for the GPMI driver.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c | 2451 +++++++++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h | 549 +++++++
2 files changed, 3000 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
new file mode 100644
index 0000000..ea7dfa7
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
@@ -0,0 +1,2451 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <linux/slab.h>
+#include "gpmi-nfc.h"
+
+/* add our owner bbt descriptor */
+static uint8_t scan_ff_pattern[] = { 0xff };
+static struct nand_bbt_descr gpmi_bbt_descr = {
+ .options = 0,
+ .offs = 0,
+ .len = 1,
+ .pattern = scan_ff_pattern
+};
+
+/* debug control */
+int gpmi_debug;
+
+static ssize_t show_gpmi_debug(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", gpmi_debug);
+}
+
+static ssize_t
+store_gpmi_debug(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ const char *p = buf;
+ unsigned long v;
+
+ if (strict_strtoul(p, 0, &v) < 0)
+ return size;
+
+ gpmi_debug = v;
+ return size;
+}
+
+static ssize_t show_ignorebad(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct gpmi_nfc_data *this = dev_get_drvdata(dev);
+ struct mil *mil = &this->mil;
+
+ return sprintf(buf, "%d\n", mil->ignore_bad_block_marks);
+}
+
+/* Sets the value of the 'ignorebad' flag. */
+static ssize_t
+store_ignorebad(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ struct gpmi_nfc_data *this = dev_get_drvdata(dev);
+ struct mil *mil = &this->mil;
+ const char *p = buf;
+ unsigned long v;
+
+ /* Try to make sense of what arrived from user space. */
+ if (strict_strtoul(p, 0, &v) < 0)
+ return size;
+
+ if (v > 0)
+ v = 1;
+
+ if (v != mil->ignore_bad_block_marks) {
+ if (v) {
+ /*
+ * If control arrives here, we want to begin ignoring
+ * bad block marks. Reach into the NAND Flash MTD data
+ * structures and set the in-memory BBT pointer to NULL.
+ * This will cause the NAND Flash MTD code to believe
+ * that it never created a BBT and force it to call our
+ * block_bad function.
+ *
+ * See mil_block_bad for more details.
+ */
+ mil->saved_bbt = mil->nand.bbt;
+ mil->nand.bbt = 0;
+ } else {
+ /*
+ * If control arrives here, we want to stop ignoring
+ * bad block marks. Restore the NAND Flash MTD's pointer
+ * to its in-memory BBT.
+ */
+ mil->nand.bbt = mil->saved_bbt;
+ }
+ mil->ignore_bad_block_marks = v;
+ }
+ return size;
+}
+
+/* Device attributes that appear in sysfs. */
+static DEVICE_ATTR(ignorebad, 0644, show_ignorebad, store_ignorebad);
+static DEVICE_ATTR(gpmi_debug, 0644, show_gpmi_debug, store_gpmi_debug);
+static struct device_attribute *device_attributes[] = {
+ &dev_attr_ignorebad,
+ &dev_attr_gpmi_debug,
+};
+
+irqreturn_t bch_irq(int irq, void *cookie)
+{
+ struct gpmi_nfc_data *this = cookie;
+ struct nfc_hal *nfc = this->nfc;
+
+ /* Clear the BCH interrupt */
+ nfc->clear_bch(this);
+
+ complete(&nfc->bch_done);
+ return IRQ_HANDLED;
+}
+
+/* get the ECC strength */
+static inline int get_ecc_strength(struct gpmi_nfc_data *this)
+{
+ return this->device_info.attr.ecc_strength_in_bits;
+}
+
+static inline int get_ecc_chunk_size(struct gpmi_nfc_data *this)
+{
+ return this->device_info.attr.ecc_size_in_bytes;
+}
+
+static inline bool is_ddr_nand(struct nand_chip *chip)
+{
+ return chip->onfi_version != 0;
+}
+
+int common_nfc_set_geometry(struct gpmi_nfc_data *this)
+{
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ struct boot_rom_helper *rom = this->rom;
+ struct mtd_info *mtd = &this->mil.mtd;
+ struct nand_chip *chip = &this->mil.nand;
+ unsigned int metadata_size;
+ unsigned int status_size;
+ unsigned int chunk_data_size_in_bits;
+ unsigned int chunk_ecc_size_in_bits;
+ unsigned int chunk_total_size_in_bits;
+ unsigned int block_mark_chunk_number;
+ unsigned int block_mark_chunk_bit_offset;
+ unsigned int block_mark_bit_offset;
+
+ /* We only support BCH now. */
+ geo->ecc_algorithm = "BCH";
+
+ /*
+ * We always choose a metadata size of 10. Don't try to make sense of
+ * it -- this is really only for historical compatibility.
+ */
+ geo->metadata_size_in_bytes = 10;
+
+ /* ECC chunks */
+ geo->ecc_chunk_size_in_bytes = get_ecc_chunk_size(this);
+
+ /*
+ * Compute the total number of ECC chunks in a page. This includes the
+ * slightly larger chunk at the beginning of the page, which contains
+ * both data and metadata.
+ */
+ geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size_in_bytes;
+
+ /*
+ * We use the same ECC strength for all chunks, including the first one.
+ */
+ geo->ecc_strength = get_ecc_strength(this);
+ if (!geo->ecc_strength) {
+ log("Unsupported page geometry.");
+ return -EINVAL;
+ }
+
+ /* Compute the page size, include page and oob. */
+ geo->page_size_in_bytes = mtd->writesize + mtd->oobsize;
+
+ /*
+ * ONFI/TOGGLE nand needs GF14, so re-culculate DMA page size.
+ * The ONFI nand must do the reculation,
+ * else it will fail in DMA in some platform(such as imx50).
+ */
+ if (is_ddr_nand(chip))
+ geo->page_size_in_bytes = mtd->writesize +
+ geo->metadata_size_in_bytes +
+ (geo->ecc_strength * 14 * 8 / geo->ecc_chunk_count);
+
+ /*
+ * The payload buffer contains the data area of a page. The ECC engine
+ * only needs what's required to hold the data.
+ */
+ geo->payload_size_in_bytes = mtd->writesize;
+
+ /*
+ * In principle, computing the auxiliary buffer geometry is NFC
+ * version-specific. However, at this writing, all versions share the
+ * same model, so this code can also be shared.
+ *
+ * The auxiliary buffer contains the metadata and the ECC status. The
+ * metadata is padded to the nearest 32-bit boundary. The ECC status
+ * contains one byte for every ECC chunk, and is also padded to the
+ * nearest 32-bit boundary.
+ */
+ metadata_size = (geo->metadata_size_in_bytes + 0x3) & ~0x3;
+ status_size = (geo->ecc_chunk_count + 0x3) & ~0x3;
+
+ geo->auxiliary_size_in_bytes = metadata_size + status_size;
+ geo->auxiliary_status_offset = metadata_size;
+
+ /* Check if we're going to do block mark swapping. */
+ if (!rom->swap_block_mark)
+ return 0;
+
+ /*
+ * If control arrives here, we're doing block mark swapping, so we need
+ * to compute the byte and bit offsets of the physical block mark within
+ * the ECC-based view of the page data. In principle, this isn't a
+ * difficult computation -- but it's very important and it's easy to get
+ * it wrong, so we do it carefully.
+ *
+ * Note that this calculation is simpler because we use the same ECC
+ * strength for all chunks, including the zero'th one, which contains
+ * the metadata. The calculation would be slightly more complicated
+ * otherwise.
+ *
+ * We start by computing the physical bit offset of the block mark. We
+ * then subtract the number of metadata and ECC bits appearing before
+ * the mark to arrive at its bit offset within the data alone.
+ */
+
+ /* Compute some important facts about chunk geometry. */
+ chunk_data_size_in_bits = geo->ecc_chunk_size_in_bytes * 8;
+
+ /* ONFI/TOGGLE nand needs GF14 */
+ if (is_ddr_nand(chip))
+ chunk_ecc_size_in_bits = geo->ecc_strength * 14;
+ else
+ chunk_ecc_size_in_bits = geo->ecc_strength * 13;
+
+ chunk_total_size_in_bits =
+ chunk_data_size_in_bits + chunk_ecc_size_in_bits;
+
+ /* Compute the bit offset of the block mark within the physical page. */
+ block_mark_bit_offset = mtd->writesize * 8;
+
+ /* Subtract the metadata bits. */
+ block_mark_bit_offset -= geo->metadata_size_in_bytes * 8;
+
+ /*
+ * Compute the chunk number (starting at zero) in which the block mark
+ * appears.
+ */
+ block_mark_chunk_number =
+ block_mark_bit_offset / chunk_total_size_in_bits;
+
+ /*
+ * Compute the bit offset of the block mark within its chunk, and
+ * validate it.
+ */
+ block_mark_chunk_bit_offset =
+ block_mark_bit_offset -
+ (block_mark_chunk_number * chunk_total_size_in_bits);
+
+ if (block_mark_chunk_bit_offset > chunk_data_size_in_bits) {
+ /*
+ * If control arrives here, the block mark actually appears in
+ * the ECC bits of this chunk. This wont' work.
+ */
+ log("Unsupported page geometry (block mark in ECC): %u:%u",
+ mtd->writesize, mtd->oobsize);
+ return !0;
+ }
+
+ /*
+ * Now that we know the chunk number in which the block mark appears,
+ * we can subtract all the ECC bits that appear before it.
+ */
+ block_mark_bit_offset -=
+ block_mark_chunk_number * chunk_ecc_size_in_bits;
+
+ /*
+ * We now know the absolute bit offset of the block mark within the
+ * ECC-based data. We can now compute the byte offset and the bit
+ * offset within the byte.
+ */
+ geo->block_mark_byte_offset = block_mark_bit_offset / 8;
+ geo->block_mark_bit_offset = block_mark_bit_offset % 8;
+
+ return 0;
+}
+
+struct dma_chan *get_dma_chan(struct gpmi_nfc_data *this)
+{
+ int chip = this->mil.current_chip;
+
+ BUG_ON(chip < 0);
+ return this->dma_chans[chip];
+}
+
+/* Can we use the upper's buffer directly for DMA? */
+void prepare_data_dma(struct gpmi_nfc_data *this, enum dma_data_direction dr)
+{
+ struct mil *mil = &this->mil;
+ struct scatterlist *sgl = &mil->data_sgl;
+ int ret;
+
+ mil->direct_dma_map_ok = true;
+
+ /* first try to map the upper buffer directly */
+ sg_init_one(sgl, mil->upper_buf, mil->upper_len);
+ ret = dma_map_sg(this->dev, sgl, 1, dr);
+ if (ret == 0) {
+ /* We have to use our own DMA buffer. */
+ sg_init_one(sgl, mil->data_buffer_dma, PAGE_SIZE);
+
+ if (dr == DMA_TO_DEVICE)
+ memcpy(mil->data_buffer_dma, mil->upper_buf,
+ mil->upper_len);
+
+ ret = dma_map_sg(this->dev, sgl, 1, dr);
+ BUG_ON(ret == 0);
+
+ mil->direct_dma_map_ok = false;
+ }
+}
+
+/* This will be called after the DMA operation is finished. */
+static void dma_irq_callback(void *param)
+{
+ struct gpmi_nfc_data *this = param;
+ struct nfc_hal *nfc = this->nfc;
+ struct mil *mil = &this->mil;
+
+ complete(&nfc->dma_done);
+
+ switch (this->dma_type) {
+ case DMA_FOR_COMMAND:
+ dma_unmap_sg(this->dev, &mil->cmd_sgl, 1, DMA_TO_DEVICE);
+ break;
+
+ case DMA_FOR_READ_DATA:
+ dma_unmap_sg(this->dev, &mil->data_sgl, 1, DMA_FROM_DEVICE);
+ if (mil->direct_dma_map_ok == false)
+ memcpy(mil->upper_buf, (char *)mil->data_buffer_dma,
+ mil->upper_len);
+ break;
+
+ case DMA_FOR_WRITE_DATA:
+ dma_unmap_sg(this->dev, &mil->data_sgl, 1, DMA_TO_DEVICE);
+ break;
+
+ case DMA_FOR_READ_ECC_PAGE:
+ case DMA_FOR_WRITE_ECC_PAGE:
+ /* We have to wait the BCH interrupt to finish. */
+ break;
+
+ default:
+ BUG();
+ }
+}
+
+int start_dma_without_bch_irq(struct gpmi_nfc_data *this,
+ struct dma_async_tx_descriptor *desc)
+{
+ struct nfc_hal *nfc = this->nfc;
+ int err;
+
+ init_completion(&nfc->dma_done);
+
+ desc->callback = dma_irq_callback;
+ desc->callback_param = this;
+ dmaengine_submit(desc);
+
+ /* Wait for the interrupt from the DMA block. */
+ err = wait_for_completion_timeout(&nfc->dma_done,
+ msecs_to_jiffies(1000));
+ err = (!err) ? -ETIMEDOUT : 0;
+ if (err)
+ log("DMA timeout!!!");
+ return err;
+}
+
+/*
+ * This function is used in BCH reading or BCH writing pages.
+ * It will wait for the BCH interrupt as long as ONE second.
+ * Actually, we must wait for two interrupts :
+ * [1] firstly the DMA interrupt and
+ * [2] secondly the BCH interrupt.
+ *
+ * @this: Per-device data structure.
+ * @desc: DMA channel
+ */
+int start_dma_with_bch_irq(struct gpmi_nfc_data *this,
+ struct dma_async_tx_descriptor *desc)
+{
+ struct nfc_hal *nfc = this->nfc;
+ int err;
+
+ /* Prepare to receive an interrupt from the BCH block. */
+ init_completion(&nfc->bch_done);
+
+ /* start the DMA */
+ start_dma_without_bch_irq(this, desc);
+
+ /* Wait for the interrupt from the BCH block. */
+ err = wait_for_completion_timeout(&nfc->bch_done,
+ msecs_to_jiffies(1000));
+ err = (!err) ? -ETIMEDOUT : 0;
+ if (err)
+ log("bch timeout!!!");
+ return err;
+}
+
+/**
+ * ns_to_cycles - Converts time in nanoseconds to cycles.
+ *
+ * @ntime: The time, in nanoseconds.
+ * @period: The cycle period, in nanoseconds.
+ * @min: The minimum allowable number of cycles.
+ */
+static unsigned int ns_to_cycles(unsigned int time,
+ unsigned int period, unsigned int min)
+{
+ unsigned int k;
+
+ /*
+ * Compute the minimum number of cycles that entirely contain the
+ * given time.
+ */
+ k = (time + period - 1) / period;
+ return max(k, min);
+}
+
+/**
+ * gpmi_compute_hardware_timing - Apply timing to current hardware conditions.
+ *
+ * @this: Per-device data.
+ * @hardware_timing: A pointer to a hardware timing structure that will receive
+ * the results of our calculations.
+ */
+int gpmi_nfc_compute_hardware_timing(struct gpmi_nfc_data *this,
+ struct gpmi_nfc_hardware_timing *hw)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct nfc_hal *nfc = this->nfc;
+ struct nand_chip *nand = &this->mil.nand;
+ struct nand_timing target = nfc->timing;
+ bool improved_timing_is_available;
+ unsigned long clock_frequency_in_hz;
+ unsigned int clock_period_in_ns;
+ bool dll_use_half_periods;
+ unsigned int dll_delay_shift;
+ unsigned int max_sample_delay_in_ns;
+ unsigned int address_setup_in_cycles;
+ unsigned int data_setup_in_ns;
+ unsigned int data_setup_in_cycles;
+ unsigned int data_hold_in_cycles;
+ int ideal_sample_delay_in_ns;
+ unsigned int sample_delay_factor;
+ int tEYE;
+ unsigned int min_prop_delay_in_ns = pdata->min_prop_delay_in_ns;
+ unsigned int max_prop_delay_in_ns = pdata->max_prop_delay_in_ns;
+
+ /*
+ * If there are multiple chips, we need to relax the timings to allow
+ * for signal distortion due to higher capacitance.
+ */
+ if (nand->numchips > 2) {
+ target.data_setup_in_ns += 10;
+ target.data_hold_in_ns += 10;
+ target.address_setup_in_ns += 10;
+ } else if (nand->numchips > 1) {
+ target.data_setup_in_ns += 5;
+ target.data_hold_in_ns += 5;
+ target.address_setup_in_ns += 5;
+ }
+
+ /* Check if improved timing information is available. */
+ improved_timing_is_available =
+ (target.tREA_in_ns >= 0) &&
+ (target.tRLOH_in_ns >= 0) &&
+ (target.tRHOH_in_ns >= 0) ;
+
+ /* Inspect the clock. */
+ clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+ clock_period_in_ns = 1000000000 / clock_frequency_in_hz;
+
+ /*
+ * The NFC quantizes setup and hold parameters in terms of clock cycles.
+ * Here, we quantize the setup and hold timing parameters to the
+ * next-highest clock period to make sure we apply at least the
+ * specified times.
+ *
+ * For data setup and data hold, the hardware interprets a value of zero
+ * as the largest possible delay. This is not what's intended by a zero
+ * in the input parameter, so we impose a minimum of one cycle.
+ */
+ data_setup_in_cycles = ns_to_cycles(target.data_setup_in_ns,
+ clock_period_in_ns, 1);
+ data_hold_in_cycles = ns_to_cycles(target.data_hold_in_ns,
+ clock_period_in_ns, 1);
+ address_setup_in_cycles = ns_to_cycles(target.address_setup_in_ns,
+ clock_period_in_ns, 0);
+
+ /*
+ * The clock's period affects the sample delay in a number of ways:
+ *
+ * (1) The NFC HAL tells us the maximum clock period the sample delay
+ * DLL can tolerate. If the clock period is greater than half that
+ * maximum, we must configure the DLL to be driven by half periods.
+ *
+ * (2) We need to convert from an ideal sample delay, in ns, to a
+ * "sample delay factor," which the NFC uses. This factor depends on
+ * whether we're driving the DLL with full or half periods.
+ * Paraphrasing the reference manual:
+ *
+ * AD = SDF x 0.125 x RP
+ *
+ * where:
+ *
+ * AD is the applied delay, in ns.
+ * SDF is the sample delay factor, which is dimensionless.
+ * RP is the reference period, in ns, which is a full clock period
+ * if the DLL is being driven by full periods, or half that if
+ * the DLL is being driven by half periods.
+ *
+ * Let's re-arrange this in a way that's more useful to us:
+ *
+ * 8
+ * SDF = AD x ----
+ * RP
+ *
+ * The reference period is either the clock period or half that, so this
+ * is:
+ *
+ * 8 AD x DDF
+ * SDF = AD x ----- = --------
+ * f x P P
+ *
+ * where:
+ *
+ * f is 1 or 1/2, depending on how we're driving the DLL.
+ * P is the clock period.
+ * DDF is the DLL Delay Factor, a dimensionless value that
+ * incorporates all the constants in the conversion.
+ *
+ * DDF will be either 8 or 16, both of which are powers of two. We can
+ * reduce the cost of this conversion by using bit shifts instead of
+ * multiplication or division. Thus:
+ *
+ * AD << DDS
+ * SDF = ---------
+ * P
+ *
+ * or
+ *
+ * AD = (SDF >> DDS) x P
+ *
+ * where:
+ *
+ * DDS is the DLL Delay Shift, the logarithm to base 2 of the DDF.
+ */
+ if (clock_period_in_ns > (nfc->max_dll_clock_period_in_ns >> 1)) {
+ dll_use_half_periods = true;
+ dll_delay_shift = 3 + 1;
+ } else {
+ dll_use_half_periods = false;
+ dll_delay_shift = 3;
+ }
+
+ /*
+ * Compute the maximum sample delay the NFC allows, under current
+ * conditions. If the clock is running too slowly, no sample delay is
+ * possible.
+ */
+ if (clock_period_in_ns > nfc->max_dll_clock_period_in_ns)
+ max_sample_delay_in_ns = 0;
+ else {
+ /*
+ * Compute the delay implied by the largest sample delay factor
+ * the NFC allows.
+ */
+ max_sample_delay_in_ns =
+ (nfc->max_sample_delay_factor * clock_period_in_ns) >>
+ dll_delay_shift;
+
+ /*
+ * Check if the implied sample delay larger than the NFC
+ * actually allows.
+ */
+ if (max_sample_delay_in_ns > nfc->max_dll_delay_in_ns)
+ max_sample_delay_in_ns = nfc->max_dll_delay_in_ns;
+ }
+
+ /*
+ * Check if improved timing information is available. If not, we have to
+ * use a less-sophisticated algorithm.
+ */
+ if (!improved_timing_is_available) {
+ /*
+ * Fold the read setup time required by the NFC into the ideal
+ * sample delay.
+ */
+ ideal_sample_delay_in_ns = target.gpmi_sample_delay_in_ns +
+ nfc->internal_data_setup_in_ns;
+
+ /*
+ * The ideal sample delay may be greater than the maximum
+ * allowed by the NFC. If so, we can trade off sample delay time
+ * for more data setup time.
+ *
+ * In each iteration of the following loop, we add a cycle to
+ * the data setup time and subtract a corresponding amount from
+ * the sample delay until we've satisified the constraints or
+ * can't do any better.
+ */
+ while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
+ (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+
+ data_setup_in_cycles++;
+ ideal_sample_delay_in_ns -= clock_period_in_ns;
+
+ if (ideal_sample_delay_in_ns < 0)
+ ideal_sample_delay_in_ns = 0;
+
+ }
+
+ /*
+ * Compute the sample delay factor that corresponds most closely
+ * to the ideal sample delay. If the result is too large for the
+ * NFC, use the maximum value.
+ *
+ * Notice that we use the ns_to_cycles function to compute the
+ * sample delay factor. We do this because the form of the
+ * computation is the same as that for calculating cycles.
+ */
+ sample_delay_factor =
+ ns_to_cycles(
+ ideal_sample_delay_in_ns << dll_delay_shift,
+ clock_period_in_ns, 0);
+
+ if (sample_delay_factor > nfc->max_sample_delay_factor)
+ sample_delay_factor = nfc->max_sample_delay_factor;
+
+ /* Skip to the part where we return our results. */
+ goto return_results;
+ }
+
+ /*
+ * If control arrives here, we have more detailed timing information,
+ * so we can use a better algorithm.
+ */
+
+ /*
+ * Fold the read setup time required by the NFC into the maximum
+ * propagation delay.
+ */
+ max_prop_delay_in_ns += nfc->internal_data_setup_in_ns;
+
+ /*
+ * Earlier, we computed the number of clock cycles required to satisfy
+ * the data setup time. Now, we need to know the actual nanoseconds.
+ */
+ data_setup_in_ns = clock_period_in_ns * data_setup_in_cycles;
+
+ /*
+ * Compute tEYE, the width of the data eye when reading from the NAND
+ * Flash. The eye width is fundamentally determined by the data setup
+ * time, perturbed by propagation delays and some characteristics of the
+ * NAND Flash device.
+ *
+ * start of the eye = max_prop_delay + tREA
+ * end of the eye = min_prop_delay + tRHOH + data_setup
+ */
+ tEYE = (int)min_prop_delay_in_ns + (int)target.tRHOH_in_ns +
+ (int)data_setup_in_ns;
+
+ tEYE -= (int)max_prop_delay_in_ns + (int)target.tREA_in_ns;
+
+ /*
+ * The eye must be open. If it's not, we can try to open it by
+ * increasing its main forcer, the data setup time.
+ *
+ * In each iteration of the following loop, we increase the data setup
+ * time by a single clock cycle. We do this until either the eye is
+ * open or we run into NFC limits.
+ */
+ while ((tEYE <= 0) &&
+ (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+ /* Give a cycle to data setup. */
+ data_setup_in_cycles++;
+ /* Synchronize the data setup time with the cycles. */
+ data_setup_in_ns += clock_period_in_ns;
+ /* Adjust tEYE accordingly. */
+ tEYE += clock_period_in_ns;
+ }
+
+ /*
+ * When control arrives here, the eye is open. The ideal time to sample
+ * the data is in the center of the eye:
+ *
+ * end of the eye + start of the eye
+ * --------------------------------- - data_setup
+ * 2
+ *
+ * After some algebra, this simplifies to the code immediately below.
+ */
+ ideal_sample_delay_in_ns =
+ ((int)max_prop_delay_in_ns +
+ (int)target.tREA_in_ns +
+ (int)min_prop_delay_in_ns +
+ (int)target.tRHOH_in_ns -
+ (int)data_setup_in_ns) >> 1;
+
+ /*
+ * The following figure illustrates some aspects of a NAND Flash read:
+ *
+ *
+ * __ _____________________________________
+ * RDN \_________________/
+ *
+ * <---- tEYE ----->
+ * /-----------------\
+ * Read Data ----------------------------< >---------
+ * \-----------------/
+ * ^ ^ ^ ^
+ * | | | |
+ * |<--Data Setup -->|<--Delay Time -->| |
+ * | | | |
+ * | | |
+ * | |<-- Quantized Delay Time -->|
+ * | | |
+ *
+ *
+ * We have some issues we must now address:
+ *
+ * (1) The *ideal* sample delay time must not be negative. If it is, we
+ * jam it to zero.
+ *
+ * (2) The *ideal* sample delay time must not be greater than that
+ * allowed by the NFC. If it is, we can increase the data setup
+ * time, which will reduce the delay between the end of the data
+ * setup and the center of the eye. It will also make the eye
+ * larger, which might help with the next issue...
+ *
+ * (3) The *quantized* sample delay time must not fall either before the
+ * eye opens or after it closes (the latter is the problem
+ * illustrated in the above figure).
+ */
+
+ /* Jam a negative ideal sample delay to zero. */
+ if (ideal_sample_delay_in_ns < 0)
+ ideal_sample_delay_in_ns = 0;
+
+ /*
+ * Extend the data setup as needed to reduce the ideal sample delay
+ * below the maximum permitted by the NFC.
+ */
+ while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
+ (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+
+ /* Give a cycle to data setup. */
+ data_setup_in_cycles++;
+ /* Synchronize the data setup time with the cycles. */
+ data_setup_in_ns += clock_period_in_ns;
+ /* Adjust tEYE accordingly. */
+ tEYE += clock_period_in_ns;
+
+ /*
+ * Decrease the ideal sample delay by one half cycle, to keep it
+ * in the middle of the eye.
+ */
+ ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
+
+ /* Jam a negative ideal sample delay to zero. */
+ if (ideal_sample_delay_in_ns < 0)
+ ideal_sample_delay_in_ns = 0;
+ }
+
+ /*
+ * Compute the sample delay factor that corresponds to the ideal sample
+ * delay. If the result is too large, then use the maximum allowed
+ * value.
+ *
+ * Notice that we use the ns_to_cycles function to compute the sample
+ * delay factor. We do this because the form of the computation is the
+ * same as that for calculating cycles.
+ */
+ sample_delay_factor =
+ ns_to_cycles(ideal_sample_delay_in_ns << dll_delay_shift,
+ clock_period_in_ns, 0);
+
+ if (sample_delay_factor > nfc->max_sample_delay_factor)
+ sample_delay_factor = nfc->max_sample_delay_factor;
+
+ /*
+ * These macros conveniently encapsulate a computation we'll use to
+ * continuously evaluate whether or not the data sample delay is inside
+ * the eye.
+ */
+ #define IDEAL_DELAY ((int) ideal_sample_delay_in_ns)
+
+ #define QUANTIZED_DELAY \
+ ((int) ((sample_delay_factor * clock_period_in_ns) >> \
+ dll_delay_shift))
+
+ #define DELAY_ERROR (abs(QUANTIZED_DELAY - IDEAL_DELAY))
+
+ #define SAMPLE_IS_NOT_WITHIN_THE_EYE (DELAY_ERROR > (tEYE >> 1))
+
+ /*
+ * While the quantized sample time falls outside the eye, reduce the
+ * sample delay or extend the data setup to move the sampling point back
+ * toward the eye. Do not allow the number of data setup cycles to
+ * exceed the maximum allowed by the NFC.
+ */
+ while (SAMPLE_IS_NOT_WITHIN_THE_EYE &&
+ (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+ /*
+ * If control arrives here, the quantized sample delay falls
+ * outside the eye. Check if it's before the eye opens, or after
+ * the eye closes.
+ */
+ if (QUANTIZED_DELAY > IDEAL_DELAY) {
+ /*
+ * If control arrives here, the quantized sample delay
+ * falls after the eye closes. Decrease the quantized
+ * delay time and then go back to re-evaluate.
+ */
+ if (sample_delay_factor != 0)
+ sample_delay_factor--;
+ continue;
+ }
+
+ /*
+ * If control arrives here, the quantized sample delay falls
+ * before the eye opens. Shift the sample point by increasing
+ * data setup time. This will also make the eye larger.
+ */
+
+ /* Give a cycle to data setup. */
+ data_setup_in_cycles++;
+ /* Synchronize the data setup time with the cycles. */
+ data_setup_in_ns += clock_period_in_ns;
+ /* Adjust tEYE accordingly. */
+ tEYE += clock_period_in_ns;
+
+ /*
+ * Decrease the ideal sample delay by one half cycle, to keep it
+ * in the middle of the eye.
+ */
+ ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
+
+ /* ...and one less period for the delay time. */
+ ideal_sample_delay_in_ns -= clock_period_in_ns;
+
+ /* Jam a negative ideal sample delay to zero. */
+ if (ideal_sample_delay_in_ns < 0)
+ ideal_sample_delay_in_ns = 0;
+
+ /*
+ * We have a new ideal sample delay, so re-compute the quantized
+ * delay.
+ */
+ sample_delay_factor =
+ ns_to_cycles(
+ ideal_sample_delay_in_ns << dll_delay_shift,
+ clock_period_in_ns, 0);
+
+ if (sample_delay_factor > nfc->max_sample_delay_factor)
+ sample_delay_factor = nfc->max_sample_delay_factor;
+ }
+
+ /* Control arrives here when we're ready to return our results. */
+return_results:
+ hw->data_setup_in_cycles = data_setup_in_cycles;
+ hw->data_hold_in_cycles = data_hold_in_cycles;
+ hw->address_setup_in_cycles = address_setup_in_cycles;
+ hw->use_half_periods = dll_use_half_periods;
+ hw->sample_delay_factor = sample_delay_factor;
+
+ /* Return success. */
+ return 0;
+}
+
+int gpmi_nfc_rom_helper_set_geometry(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_geometry *geometry = &this->rom_geometry;
+
+ /*
+ * Set the boot block stride size.
+ *
+ * In principle, we should be reading this from the OTP bits, since
+ * that's where the ROM is going to get it. In fact, we don't have any
+ * way to read the OTP bits, so we go with the default and hope for the
+ * best.
+ */
+ geometry->stride_size_in_pages = 64;
+
+ /*
+ * Set the search area stride exponent.
+ *
+ * In principle, we should be reading this from the OTP bits, since
+ * that's where the ROM is going to get it. In fact, we don't have any
+ * way to read the OTP bits, so we go with the default and hope for the
+ * best.
+ */
+ geometry->search_area_stride_exponent = 2;
+
+ return 0;
+}
+
+static int acquire_register_block(struct gpmi_nfc_data *this,
+ const char *resource_name, void **reg_block_base)
+{
+ struct platform_device *pdev = this->pdev;
+ struct resource *r;
+ void *p;
+
+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, resource_name);
+ if (!r) {
+ log("Can't get resource information for '%s'", resource_name);
+ return -ENXIO;
+ }
+
+ /* remap the register block */
+ p = ioremap(r->start, resource_size(r));
+ if (!p) {
+ log("Can't remap %s", resource_name);
+ return -ENOMEM;
+ }
+
+ *reg_block_base = p;
+ return 0;
+}
+
+static void release_register_block(struct gpmi_nfc_data *this,
+ void *reg_block_base)
+{
+ iounmap(reg_block_base);
+}
+
+static int acquire_interrupt(struct gpmi_nfc_data *this,
+ const char *resource_name,
+ irq_handler_t interrupt_handler, int *lno, int *hno)
+{
+ struct platform_device *pdev = this->pdev;
+ struct resource *r;
+ int err;
+
+ r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, resource_name);
+ if (!r) {
+ log("Can't get resource information for '%s'", resource_name);
+ return -ENXIO;
+ }
+
+ BUG_ON(r->start != r->end);
+ err = request_irq(r->start, interrupt_handler, 0, resource_name, this);
+ if (err) {
+ log("Can't own %s", resource_name);
+ return err;
+ }
+
+ *lno = r->start;
+ *hno = r->end;
+ return 0;
+}
+
+static void release_interrupt(struct gpmi_nfc_data *this,
+ int low_interrupt_number, int high_interrupt_number)
+{
+ int i;
+ for (i = low_interrupt_number; i <= high_interrupt_number; i++)
+ free_irq(i, this);
+}
+
+static bool gpmi_dma_filter(struct dma_chan *chan, void *param)
+{
+ struct gpmi_nfc_data *this = param;
+ struct resource *r = this->private;
+
+ if (!mxs_dma_is_apbh(chan))
+ return false;
+ /*
+ * only catch the GPMI dma channels :
+ * for mx23 : MX23_DMA_GPMI0 ~ MX23_DMA_GPMI3
+ * (These four channels share the same IRQ!)
+ *
+ * for mx28 : MX28_DMA_GPMI0 ~ MX28_DMA_GPMI7
+ * (These eight channels share the same IRQ!)
+ */
+ if (r->start <= chan->chan_id && chan->chan_id <= r->end) {
+ chan->private = &this->dma_data;
+ return true;
+ }
+ return false;
+}
+
+static void release_dma_channels(struct gpmi_nfc_data *this)
+{
+ unsigned int i;
+ for (i = 0; i < DMA_CHANS; i++)
+ if (this->dma_chans[i]) {
+ dma_release_channel(this->dma_chans[i]);
+ this->dma_chans[i] = NULL;
+ }
+}
+
+static int acquire_dma_channels(struct gpmi_nfc_data *this,
+ const char *resource_name,
+ unsigned *low_channel, unsigned *high_channel)
+{
+ struct platform_device *pdev = this->pdev;
+ struct resource *r, *r_dma;
+ unsigned int i;
+
+ r = platform_get_resource_byname(pdev, IORESOURCE_DMA, resource_name);
+ r_dma = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
+ GPMI_NFC_DMA_INTERRUPT_RES_NAME);
+ if (!r || !r_dma) {
+ log("Can't get resource for DMA");
+ return -ENXIO;
+ }
+
+ /* get the DMA interrupt */
+ BUG_ON(r_dma->start != r_dma->end);
+ this->dma_data.chan_irq = r_dma->start;
+
+ /* used in gpmi_dma_filter() */
+ this->private = r;
+
+ for (i = r->start; i <= r->end; i++) {
+ dma_cap_mask_t mask;
+ struct dma_chan *dma_chan;
+
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+
+ dma_chan = dma_request_channel(mask, gpmi_dma_filter, this);
+ if (!dma_chan)
+ goto acquire_err;
+ /* fill the first empty item */
+ this->dma_chans[i - r->start] = dma_chan;
+ }
+
+ *low_channel = r->start;
+ *high_channel = r->end;
+ return 0;
+
+acquire_err:
+ log("Can't acquire DMA channel %u", i);
+ release_dma_channels(this);
+ return -EINVAL;
+}
+
+static inline int acquire_clock(struct gpmi_nfc_data *this, struct clk **clock)
+{
+ struct clk *c;
+
+ c = clk_get(&this->pdev->dev, NULL);
+ if (IS_ERR(c)) {
+ log("Can't own clock");
+ return PTR_ERR(c);
+ }
+ *clock = c;
+ return 0;
+}
+
+static void release_clock(struct gpmi_nfc_data *this, struct clk *clock)
+{
+ clk_put(clock);
+}
+
+static int acquire_resources(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ int error;
+
+ /* Attempt to acquire the GPMI register block. */
+ error = acquire_register_block(this,
+ GPMI_NFC_GPMI_REGS_ADDR_RES_NAME,
+ &resources->gpmi_regs);
+ if (error)
+ goto exit_gpmi_regs;
+
+ /* Attempt to acquire the BCH register block. */
+ error = acquire_register_block(this,
+ GPMI_NFC_BCH_REGS_ADDR_RES_NAME,
+ &resources->bch_regs);
+ if (error)
+ goto exit_bch_regs;
+
+ /* Attempt to acquire the BCH interrupt. */
+ error = acquire_interrupt(this,
+ GPMI_NFC_BCH_INTERRUPT_RES_NAME,
+ bch_irq,
+ &resources->bch_low_interrupt,
+ &resources->bch_high_interrupt);
+ if (error)
+ goto exit_bch_interrupt;
+
+ /* Attempt to acquire the DMA channels. */
+ error = acquire_dma_channels(this,
+ GPMI_NFC_DMA_CHANNELS_RES_NAME,
+ &resources->dma_low_channel,
+ &resources->dma_high_channel);
+ if (error)
+ goto exit_dma_channels;
+
+ /* Attempt to acquire our clock. */
+ error = acquire_clock(this, &resources->clock);
+ if (error)
+ goto exit_clock;
+ return 0;
+
+exit_clock:
+ release_dma_channels(this);
+exit_dma_channels:
+ release_interrupt(this, resources->bch_low_interrupt,
+ resources->bch_high_interrupt);
+exit_bch_interrupt:
+ release_register_block(this, resources->bch_regs);
+exit_bch_regs:
+ release_register_block(this, resources->gpmi_regs);
+exit_gpmi_regs:
+ return error;
+}
+
+static void release_resources(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+
+ release_clock(this, resources->clock);
+ release_register_block(this, resources->gpmi_regs);
+ release_register_block(this, resources->bch_regs);
+ release_interrupt(this, resources->bch_low_interrupt,
+ resources->bch_low_interrupt);
+ release_dma_channels(this);
+}
+
+static void exit_nfc_hal(struct gpmi_nfc_data *this)
+{
+ if (this->nfc)
+ this->nfc->exit(this);
+}
+
+static int set_up_nfc_hal(struct gpmi_nfc_data *this)
+{
+ struct nfc_hal *nfc = NULL;
+ int error;
+
+ /*
+ * This structure contains the "safe" GPMI timing that should succeed
+ * with any NAND Flash device
+ * (although, with less-than-optimal performance).
+ */
+ static struct nand_timing safe_timing = {
+ .data_setup_in_ns = 80,
+ .data_hold_in_ns = 60,
+ .address_setup_in_ns = 25,
+ .gpmi_sample_delay_in_ns = 6,
+ .tREA_in_ns = -1,
+ .tRLOH_in_ns = -1,
+ .tRHOH_in_ns = -1,
+ };
+
+ if (cpu_is_mx23() || cpu_is_mx28())
+ nfc = &gpmi_nfc_hal_imx23_imx28;
+
+ BUG_ON(nfc == NULL);
+ this->nfc = nfc;
+
+ /* Initialize the NFC HAL. */
+ error = nfc->init(this);
+ if (error)
+ return error;
+
+ /* Set up safe timing. */
+ nfc->set_timing(this, &safe_timing);
+ return 0;
+}
+
+static int set_up_boot_rom_helper(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_helper *rom = NULL;
+
+ if (cpu_is_mx23())
+ rom = &gpmi_nfc_boot_rom_imx23;
+ if (cpu_is_mx28())
+ rom = &gpmi_nfc_boot_rom_imx28;
+
+ BUG_ON(rom == NULL);
+
+ pr_info("Boot ROM: Version %u, %s\n", rom->version, rom->description);
+ this->rom = rom;
+ return 0;
+}
+
+/* Creates/Removes sysfs files for this device.*/
+static void manage_sysfs_files(struct gpmi_nfc_data *this, int create)
+{
+ struct device *dev = this->dev;
+ int error;
+ unsigned int i;
+ struct device_attribute **attr;
+
+ for (i = 0, attr = device_attributes;
+ i < ARRAY_SIZE(device_attributes); i++, attr++) {
+
+ if (create) {
+ error = device_create_file(dev, *attr);
+ if (error) {
+ while (--attr >= device_attributes)
+ device_remove_file(dev, *attr);
+ return;
+ }
+ } else {
+ device_remove_file(dev, *attr);
+ }
+ }
+}
+
+static int read_page_prepare(struct gpmi_nfc_data *this,
+ void *destination, unsigned length,
+ void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+ void **use_virt, dma_addr_t *use_phys)
+{
+ struct device *dev = this->dev;
+ dma_addr_t destination_phys = ~0;
+
+ if (virt_addr_valid(destination))
+ destination_phys = dma_map_single(dev, (void *)destination,
+ length, DMA_FROM_DEVICE);
+
+ if (dma_mapping_error(dev, destination_phys)) {
+ if (alt_size < length) {
+ log("Alternate buffer is too small for incoming I/O.");
+ return -ENOMEM;
+ }
+
+ *use_virt = alt_virt;
+ *use_phys = alt_phys;
+ } else {
+ *use_virt = destination;
+ *use_phys = destination_phys;
+ }
+ return 0;
+}
+
+static void read_page_end(struct gpmi_nfc_data *this,
+ void *destination, unsigned length,
+ void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+ void *used_virt, dma_addr_t used_phys)
+{
+ struct device *dev = this->dev;
+
+ if (used_virt == destination)
+ dma_unmap_single(dev, used_phys, length, DMA_FROM_DEVICE);
+ else
+ memcpy(destination, alt_virt, length);
+}
+
+static int send_page_prepare(struct gpmi_nfc_data *this,
+ const void *source, unsigned length,
+ void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+ const void **use_virt, dma_addr_t *use_phys)
+{
+ dma_addr_t source_phys = ~0;
+ struct device *dev = this->dev;
+
+ if (virt_addr_valid(source))
+ source_phys = dma_map_single(dev,
+ (void *)source, length, DMA_TO_DEVICE);
+
+ if (dma_mapping_error(dev, source_phys)) {
+ if (alt_size < length) {
+ log("Alternate buffer is too small for outgoing I/O");
+ return -ENOMEM;
+ }
+
+ /*
+ * Copy the contents of the source buffer into the alternate
+ * buffer and set up the return values accordingly.
+ */
+ memcpy(alt_virt, source, length);
+
+ *use_virt = alt_virt;
+ *use_phys = alt_phys;
+ } else {
+ *use_virt = source;
+ *use_phys = source_phys;
+ }
+ return 0;
+}
+
+static void send_page_end(struct gpmi_nfc_data *this,
+ const void *source, unsigned length,
+ void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+ const void *used_virt, dma_addr_t used_phys)
+{
+ struct device *dev = this->dev;
+ if (used_virt == source)
+ dma_unmap_single(dev, used_phys, length, DMA_TO_DEVICE);
+}
+
+static void mil_free_dma_buffer(struct gpmi_nfc_data *this)
+{
+ struct device *dev = this->dev;
+ struct mil *mil = &this->mil;
+
+ if (mil->page_buffer_virt && virt_addr_valid(mil->page_buffer_virt))
+ dma_free_coherent(dev, mil->page_buffer_size,
+ mil->page_buffer_virt,
+ mil->page_buffer_phys);
+ kfree(mil->cmd_buffer);
+ kfree(mil->data_buffer_dma);
+
+ mil->cmd_buffer = NULL;
+ mil->data_buffer_dma = NULL;
+ mil->page_buffer_virt = NULL;
+ mil->page_buffer_size = 0;
+ mil->page_buffer_phys = ~0;
+}
+
+/* Allocate the DMA buffers */
+static int mil_alloc_dma_buffer(struct gpmi_nfc_data *this)
+{
+ struct device *dev = this->dev;
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ struct mil *mil = &this->mil;
+
+ /* [1] Allocate a command buffer. PAGE_SIZE is enough. */
+ mil->cmd_buffer = kzalloc(PAGE_SIZE, GFP_DMA);
+ if (mil->cmd_buffer == NULL)
+ goto error_alloc;
+
+ /* [2] Allocate a read/write data buffer. PAGE_SIZE is enough. */
+ mil->data_buffer_dma = kzalloc(PAGE_SIZE, GFP_DMA);
+ if (mil->data_buffer_dma == NULL)
+ goto error_alloc;
+
+ /*
+ * [3] Allocate the page buffer.
+ *
+ * Both the payload buffer and the auxiliary buffer must appear on
+ * 32-bit boundaries. We presume the size of the payload buffer is a
+ * power of two and is much larger than four, which guarantees the
+ * auxiliary buffer will appear on a 32-bit boundary.
+ */
+ mil->page_buffer_size = geo->payload_size_in_bytes +
+ geo->auxiliary_size_in_bytes;
+
+ mil->page_buffer_virt = dma_alloc_coherent(dev, mil->page_buffer_size,
+ &mil->page_buffer_phys, GFP_DMA);
+ if (!mil->page_buffer_virt)
+ goto error_alloc;
+
+
+ /* Slice up the page buffer. */
+ mil->payload_virt = mil->page_buffer_virt;
+ mil->payload_phys = mil->page_buffer_phys;
+ mil->auxiliary_virt = ((char *) mil->payload_virt) +
+ geo->payload_size_in_bytes;
+ mil->auxiliary_phys = mil->payload_phys +
+ geo->payload_size_in_bytes;
+ return 0;
+
+error_alloc:
+ mil_free_dma_buffer(this);
+ log("allocate DMA buffer error!!");
+ return -ENOMEM;
+}
+
+static void mil_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ struct mil *mil = &this->mil;
+ struct nfc_hal *nfc = this->nfc;
+ int error;
+
+ /*
+ * Every operation begins with a command byte and a series of zero or
+ * more address bytes. These are distinguished by either the Address
+ * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
+ * asserted. When MTD is ready to execute the command, it will deassert
+ * both latch enables.
+ *
+ * Rather than run a separate DMA operation for every single byte, we
+ * queue them up and run a single DMA operation for the entire series
+ * of command and data bytes. NAND_CMD_NONE means the END of the queue.
+ */
+ if ((ctrl & (NAND_ALE | NAND_CLE))) {
+ if (data != NAND_CMD_NONE)
+ mil->cmd_buffer[mil->command_length++] = data;
+ return;
+ }
+
+ if (!mil->command_length)
+ return;
+
+ error = nfc->send_command(this);
+ if (error)
+ log("Chip: %u, Error %d", mil->current_chip, error);
+
+ mil->command_length = 0;
+}
+
+static int mil_dev_ready(struct mtd_info *mtd)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct mil *mil = &this->mil;
+
+ return nfc->is_ready(this, mil->current_chip);
+}
+
+static void mil_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ struct mil *mil = &this->mil;
+ struct nfc_hal *nfc = this->nfc;
+
+ if ((mil->current_chip < 0) && (chip >= 0))
+ nfc->begin(this);
+ else if ((mil->current_chip >= 0) && (chip < 0))
+ nfc->end(this);
+ else
+ ;
+
+ mil->current_chip = chip;
+}
+
+static void mil_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct mil *mil = &this->mil;
+
+ logio(GPMI_DEBUG_READ);
+ /* save the info in mil{} for future */
+ mil->upper_buf = buf;
+ mil->upper_len = len;
+
+ nfc->read_data(this);
+}
+
+static void mil_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct mil *mil = &this->mil;
+
+ logio(GPMI_DEBUG_WRITE);
+ /* save the info in mil{} for future */
+ mil->upper_buf = (uint8_t *)buf;
+ mil->upper_len = len;
+
+ nfc->send_data(this);
+}
+
+static uint8_t mil_read_byte(struct mtd_info *mtd)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ struct mil *mil = &this->mil;
+ uint8_t *buf = mil->data_buffer_dma;
+
+ mil_read_buf(mtd, buf, 1);
+ return buf[0];
+}
+
+/**
+ * mil_handle_block_mark_swapping() - Handles block mark swapping.
+ *
+ * Note that, when this function is called, it doesn't know whether it's
+ * swapping the block mark, or swapping it *back* -- but it doesn't matter
+ * because the the operation is the same.
+ *
+ * @this: Per-device data.
+ * @payload: A pointer to the payload buffer.
+ * @auxiliary: A pointer to the auxiliary buffer.
+ */
+static void mil_handle_block_mark_swapping(struct gpmi_nfc_data *this,
+ void *payload, void *auxiliary)
+{
+ struct nfc_geometry *nfc_geo = &this->nfc_geometry;
+ struct boot_rom_helper *rom = this->rom;
+ unsigned char *p;
+ unsigned char *a;
+ unsigned int bit;
+ unsigned char mask;
+ unsigned char from_data;
+ unsigned char from_oob;
+
+ /* Check if we're doing block mark swapping. */
+ if (!rom->swap_block_mark)
+ return;
+
+ /*
+ * If control arrives here, we're swapping. Make some convenience
+ * variables.
+ */
+ bit = nfc_geo->block_mark_bit_offset;
+ p = payload + nfc_geo->block_mark_byte_offset;
+ a = auxiliary;
+
+ /*
+ * Get the byte from the data area that overlays the block mark. Since
+ * the ECC engine applies its own view to the bits in the page, the
+ * physical block mark won't (in general) appear on a byte boundary in
+ * the data.
+ */
+ from_data = (p[0] >> bit) | (p[1] << (8 - bit));
+
+ /* Get the byte from the OOB. */
+ from_oob = a[0];
+
+ /* Swap them. */
+ a[0] = from_data;
+
+ mask = (0x1 << bit) - 1;
+ p[0] = (p[0] & mask) | (from_oob << bit);
+
+ mask = ~0 << bit;
+ p[1] = (p[1] & mask) | (from_oob >> (8 - bit));
+}
+
+static int mil_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
+ uint8_t *buf, int page)
+{
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct nfc_geometry *nfc_geo = &this->nfc_geometry;
+ struct mil *mil = &this->mil;
+ void *payload_virt;
+ dma_addr_t payload_phys;
+ void *auxiliary_virt;
+ dma_addr_t auxiliary_phys;
+ unsigned int i;
+ unsigned char *status;
+ unsigned int failed;
+ unsigned int corrected;
+ int error;
+
+ logio(GPMI_DEBUG_ECC_READ);
+ error = read_page_prepare(this, buf, mtd->writesize,
+ mil->payload_virt, mil->payload_phys,
+ nfc_geo->payload_size_in_bytes,
+ &payload_virt, &payload_phys);
+ if (error) {
+ log("Inadequate DMA buffer");
+ error = -ENOMEM;
+ return error;
+ }
+ auxiliary_virt = mil->auxiliary_virt;
+ auxiliary_phys = mil->auxiliary_phys;
+
+ /* ask the NFC */
+ error = nfc->read_page(this, payload_phys, auxiliary_phys);
+ if (error) {
+ log("Error in ECC-based read: %d", error);
+ goto exit_nfc;
+ }
+
+ /* handle the block mark swapping */
+ mil_handle_block_mark_swapping(this, payload_virt, auxiliary_virt);
+
+ /* Loop over status bytes, accumulating ECC status. */
+ failed = 0;
+ corrected = 0;
+ status = auxiliary_virt + nfc_geo->auxiliary_status_offset;
+
+ for (i = 0; i < nfc_geo->ecc_chunk_count; i++, status++) {
+ if ((*status == STATUS_GOOD) || (*status == STATUS_ERASED))
+ continue;
+
+ if (*status == STATUS_UNCORRECTABLE) {
+ failed++;
+ continue;
+ }
+ corrected += *status;
+ }
+
+ /*
+ * Propagate ECC status to the owning MTD only when failed or
+ * corrected times nearly reaches our ECC correction threshold.
+ */
+ if (failed || corrected >= (nfc_geo->ecc_strength - 1)) {
+ mtd->ecc_stats.failed += failed;
+ mtd->ecc_stats.corrected += corrected;
+ }
+
+ /*
+ * It's time to deliver the OOB bytes. See mil_ecc_read_oob() for
+ * details about our policy for delivering the OOB.
+ *
+ * We fill the caller's buffer with set bits, and then copy the block
+ * mark to th caller's buffer. Note that, if block mark swapping was
+ * necessary, it has already been done, so we can rely on the first
+ * byte of the auxiliary buffer to contain the block mark.
+ */
+ memset(nand->oob_poi, ~0, mtd->oobsize);
+ nand->oob_poi[0] = ((uint8_t *) auxiliary_virt)[0];
+
+exit_nfc:
+ read_page_end(this, buf, mtd->writesize,
+ mil->payload_virt, mil->payload_phys,
+ nfc_geo->payload_size_in_bytes,
+ payload_virt, payload_phys);
+ return error;
+}
+
+static void mil_ecc_write_page(struct mtd_info *mtd,
+ struct nand_chip *nand, const uint8_t *buf)
+{
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct nfc_geometry *nfc_geo = &this->nfc_geometry;
+ struct boot_rom_helper *rom = this->rom;
+ struct mil *mil = &this->mil;
+ const void *payload_virt;
+ dma_addr_t payload_phys;
+ const void *auxiliary_virt;
+ dma_addr_t auxiliary_phys;
+ int error;
+
+ logio(GPMI_DEBUG_ECC_WRITE);
+ if (rom->swap_block_mark) {
+ /*
+ * If control arrives here, we're doing block mark swapping.
+ * Since we can't modify the caller's buffers, we must copy them
+ * into our own.
+ */
+ memcpy(mil->payload_virt, buf, mtd->writesize);
+ payload_virt = mil->payload_virt;
+ payload_phys = mil->payload_phys;
+
+ memcpy(mil->auxiliary_virt, nand->oob_poi,
+ nfc_geo->auxiliary_size_in_bytes);
+ auxiliary_virt = mil->auxiliary_virt;
+ auxiliary_phys = mil->auxiliary_phys;
+
+ /* Handle block mark swapping. */
+ mil_handle_block_mark_swapping(this,
+ (void *) payload_virt, (void *) auxiliary_virt);
+ } else {
+ /*
+ * If control arrives here, we're not doing block mark swapping,
+ * so we can to try and use the caller's buffers.
+ */
+ error = send_page_prepare(this,
+ buf, mtd->writesize,
+ mil->payload_virt, mil->payload_phys,
+ nfc_geo->payload_size_in_bytes,
+ &payload_virt, &payload_phys);
+ if (error) {
+ log("Inadequate payload DMA buffer");
+ return;
+ }
+
+ error = send_page_prepare(this,
+ nand->oob_poi, mtd->oobsize,
+ mil->auxiliary_virt, mil->auxiliary_phys,
+ nfc_geo->auxiliary_size_in_bytes,
+ &auxiliary_virt, &auxiliary_phys);
+ if (error) {
+ log("Inadequate auxiliary DMA buffer");
+ goto exit_auxiliary;
+ }
+ }
+
+ /* Ask the NFC. */
+ error = nfc->send_page(this, payload_phys, auxiliary_phys);
+ if (error)
+ log("Error in ECC-based write: %d", error);
+
+ if (!rom->swap_block_mark) {
+ send_page_end(this, nand->oob_poi, mtd->oobsize,
+ mil->auxiliary_virt, mil->auxiliary_phys,
+ nfc_geo->auxiliary_size_in_bytes,
+ auxiliary_virt, auxiliary_phys);
+exit_auxiliary:
+ send_page_end(this, buf, mtd->writesize,
+ mil->payload_virt, mil->payload_phys,
+ nfc_geo->payload_size_in_bytes,
+ payload_virt, payload_phys);
+ }
+}
+
+/**
+ * mil_hook_block_markbad() - Hooked MTD Interface block_markbad().
+ *
+ * This function is a veneer that replaces the function originally installed by
+ * the NAND Flash MTD code. See the description of the marking_a_bad_block field
+ * in struct mil for more information about this.
+ *
+ * @mtd: A pointer to the MTD.
+ * @ofs: Byte address of the block to mark.
+ */
+static int mil_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+ register struct nand_chip *chip = mtd->priv;
+ struct gpmi_nfc_data *this = chip->priv;
+ struct mil *mil = &this->mil;
+ int ret;
+
+ mil->marking_a_bad_block = true;
+ ret = mil->hooked_block_markbad(mtd, ofs);
+ mil->marking_a_bad_block = false;
+ return ret;
+}
+
+/**
+ * mil_ecc_read_oob() - MTD Interface ecc.read_oob().
+ *
+ * There are several places in this driver where we have to handle the OOB and
+ * block marks. This is the function where things are the most complicated, so
+ * this is where we try to explain it all. All the other places refer back to
+ * here.
+ *
+ * These are the rules, in order of decreasing importance:
+ *
+ * 1) Nothing the caller does can be allowed to imperil the block mark, so all
+ * write operations take measures to protect it.
+ *
+ * 2) In read operations, the first byte of the OOB we return must reflect the
+ * true state of the block mark, no matter where that block mark appears in
+ * the physical page.
+ *
+ * 3) ECC-based read operations return an OOB full of set bits (since we never
+ * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
+ * return).
+ *
+ * 4) "Raw" read operations return a direct view of the physical bytes in the
+ * page, using the conventional definition of which bytes are data and which
+ * are OOB. This gives the caller a way to see the actual, physical bytes
+ * in the page, without the distortions applied by our ECC engine.
+ *
+ *
+ * What we do for this specific read operation depends on two questions:
+ *
+ * 1) Are we doing a "raw" read, or an ECC-based read?
+ *
+ * 2) Are we using block mark swapping or transcription?
+ *
+ * There are four cases, illustrated by the following Karnaugh map:
+ *
+ * | Raw | ECC-based |
+ * -------------+-------------------------+-------------------------+
+ * | Read the conventional | |
+ * | OOB at the end of the | |
+ * Swapping | page and return it. It | |
+ * | contains exactly what | |
+ * | we want. | Read the block mark and |
+ * -------------+-------------------------+ return it in a buffer |
+ * | Read the conventional | full of set bits. |
+ * | OOB at the end of the | |
+ * | page and also the block | |
+ * Transcribing | mark in the metadata. | |
+ * | Copy the block mark | |
+ * | into the first byte of | |
+ * | the OOB. | |
+ * -------------+-------------------------+-------------------------+
+ *
+ * Note that we break rule #4 in the Transcribing/Raw case because we're not
+ * giving an accurate view of the actual, physical bytes in the page (we're
+ * overwriting the block mark). That's OK because it's more important to follow
+ * rule #2.
+ *
+ * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
+ * easy. When reading a page, for example, the NAND Flash MTD code calls our
+ * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
+ * ECC-based or raw view of the page is implicit in which function it calls
+ * (there is a similar pair of ECC-based/raw functions for writing).
+ *
+ * Since MTD assumes the OOB is not covered by ECC, there is no pair of
+ * ECC-based/raw functions for reading or or writing the OOB. The fact that the
+ * caller wants an ECC-based or raw view of the page is not propagated down to
+ * this driver.
+ *
+ * @mtd: A pointer to the owning MTD.
+ * @nand: A pointer to the owning NAND Flash MTD.
+ * @page: The page number to read.
+ * @sndcmd: Indicates this function should send a command to the chip before
+ * reading the out-of-band bytes. This is only false for small page
+ * chips that support auto-increment.
+ */
+static int mil_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
+ int page, int sndcmd)
+{
+ struct gpmi_nfc_data *this = nand->priv;
+ struct boot_rom_helper *rom = this->rom;
+
+ /* clear the OOB buffer */
+ memset(nand->oob_poi, ~0, mtd->oobsize);
+
+ /* Read out the conventional OOB. */
+ nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
+ nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
+
+ /*
+ * Now, we want to make sure the block mark is correct. In the
+ * Swapping/Raw case, we already have it. Otherwise, we need to
+ * explicitly read it.
+ */
+ if (!rom->swap_block_mark) {
+ /* Read the block mark into the first byte of the OOB buffer. */
+ nand->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+ nand->oob_poi[0] = nand->read_byte(mtd);
+ }
+
+ /*
+ * Return true, indicating that the next call to this function must send
+ * a command.
+ */
+ return true;
+}
+
+static int mil_ecc_write_oob(struct mtd_info *mtd,
+ struct nand_chip *nand, int page)
+{
+ struct gpmi_nfc_data *this = nand->priv;
+ struct device *dev = this->dev;
+ struct mil *mil = &this->mil;
+ struct boot_rom_helper *rom = this->rom;
+ uint8_t *block_mark;
+ int block_mark_column;
+ int status;
+ int error = 0;
+
+ /*
+ * There are fundamental incompatibilities between the i.MX GPMI NFC and
+ * the NAND Flash MTD model that make it essentially impossible to write
+ * the out-of-band bytes.
+ *
+ * We permit *ONE* exception. If the *intent* of writing the OOB is to
+ * mark a block bad, we can do that.
+ */
+ if (!mil->marking_a_bad_block) {
+ dev_emerg(dev, "This driver doesn't support writing the OOB\n");
+ WARN_ON(1);
+ error = -EIO;
+ goto exit;
+ }
+
+ /*
+ * If control arrives here, we're marking a block bad. First, figure out
+ * where the block mark is.
+ *
+ * If we're using swapping, the block mark is in the conventional
+ * location. Otherwise, we're using transcription, and the block mark
+ * appears in the first byte of the page.
+ */
+ if (rom->swap_block_mark)
+ block_mark_column = mtd->writesize;
+ else
+ block_mark_column = 0;
+
+ /* Write the block mark. */
+ block_mark = mil->data_buffer_dma;
+ block_mark[0] = 0; /* bad block marker */
+
+ nand->cmdfunc(mtd, NAND_CMD_SEQIN, block_mark_column, page);
+ nand->write_buf(mtd, block_mark, 1);
+ nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ status = nand->waitfunc(mtd, nand);
+
+ /* Check if it worked. */
+ if (status & NAND_STATUS_FAIL)
+ error = -EIO;
+exit:
+ return error;
+}
+
+/**
+ * mil_block_bad - Claims all blocks are good.
+ *
+ * In principle, this function is *only* called when the NAND Flash MTD system
+ * isn't allowed to keep an in-memory bad block table, so it is forced to ask
+ * the driver for bad block information.
+ *
+ * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
+ * this function is *only* called when we take it away.
+ *
+ * We take away the in-memory BBT when the user sets the "ignorebad" parameter,
+ * which indicates that all blocks should be reported good.
+ *
+ * Thus, this function is only called when we want *all* blocks to look good,
+ * so it *always* return success.
+ *
+ * @mtd: Ignored.
+ * @ofs: Ignored.
+ * @getchip: Ignored.
+ */
+static int mil_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+{
+ return 0;
+}
+
+static void show_rom_geometry(struct boot_rom_geometry *geo)
+{
+ pr_info("--------------------------------------------\n");
+ pr_info(" Boot ROM Geometry\n");
+ pr_info("--------------------------------------------\n");
+ pr_info("Boot Area Count : %u\n", geo->boot_area_count);
+ pr_info("Boot Area Size in Bytes : %u (0x%x)\n",
+ geo->boot_area_size_in_bytes,
+ geo->boot_area_size_in_bytes);
+ pr_info("Stride Size in Pages : %u\n", geo->stride_size_in_pages);
+ pr_info("Search Area Stride Exponent: %u\n",
+ geo->search_area_stride_exponent);
+}
+
+/* Set up the Boot ROM Helper geometry. */
+static int mil_set_boot_rom_helper_geometry(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_helper *rom = this->rom;
+ struct boot_rom_geometry *geo = &this->rom_geometry;
+ int error;
+
+ error = rom->set_geometry(this);
+ if (error)
+ return error;
+
+ if (gpmi_debug & GPMI_DEBUG_INIT)
+ show_rom_geometry(geo);
+
+ return 0;
+}
+
+static void show_nfc_geometry(struct nfc_geometry *geo)
+{
+ pr_info("---------------------------------------\n");
+ pr_info(" NFC Geometry (used by BCH)\n");
+ pr_info("---------------------------------------\n");
+ pr_info("ECC Algorithm : %s\n", geo->ecc_algorithm);
+ pr_info("ECC Strength : %u\n", geo->ecc_strength);
+ pr_info("Page Size in Bytes : %u\n", geo->page_size_in_bytes);
+ pr_info("Metadata Size in Bytes : %u\n", geo->metadata_size_in_bytes);
+ pr_info("ECC Chunk Size in Bytes: %u\n", geo->ecc_chunk_size_in_bytes);
+ pr_info("ECC Chunk Count : %u\n", geo->ecc_chunk_count);
+ pr_info("Payload Size in Bytes : %u\n", geo->payload_size_in_bytes);
+ pr_info("Auxiliary Size in Bytes: %u\n", geo->auxiliary_size_in_bytes);
+ pr_info("Auxiliary Status Offset: %u\n", geo->auxiliary_status_offset);
+ pr_info("Block Mark Byte Offset : %u\n", geo->block_mark_byte_offset);
+ pr_info("Block Mark Bit Offset : %u\n", geo->block_mark_bit_offset);
+}
+
+static int mil_set_geometry(struct gpmi_nfc_data *this)
+{
+ struct nfc_hal *nfc = this->nfc;
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ int error;
+
+ /* Free the temporary DMA memory for read ID case */
+ mil_free_dma_buffer(this);
+
+ /* Set up the NFC geometry which is used by BCH. */
+ error = nfc->set_geometry(this);
+ if (error != 0) {
+ log("NFC set geometry error : %d", error);
+ return error;
+ }
+ if (gpmi_debug & GPMI_DEBUG_INIT)
+ show_nfc_geometry(geo);
+
+ /* Alloc the new DMA buffers according to the pagesize and oobsize */
+ return mil_alloc_dma_buffer(this);
+}
+
+static int mil_pre_bbt_scan(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_helper *rom = this->rom;
+ int error;
+
+ error = mil_set_boot_rom_helper_geometry(this);
+ if (error)
+ return error;
+
+ /* This is ROM arch-specific initilization before the BBT scanning. */
+ if (rom->rom_extra_init)
+ error = rom->rom_extra_init(this);
+ return error;
+}
+
+static int mil_scan_bbt(struct mtd_info *mtd)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ int error;
+
+ /* Prepare for the BBT scan. */
+ error = mil_pre_bbt_scan(this);
+ if (error)
+ return error;
+
+ /* use the default BBT implementation */
+ return nand_default_bbt(mtd);
+}
+
+static int mil_boot_areas_init(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_geometry *rom = &this->rom_geometry;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+
+ if (rom->boot_area_count == 0) {
+ mil->general_use_mtd = &mil->mtd;
+ pr_info("There is no Boot area.\n");
+ } else if (rom->boot_area_count == 1) {
+ static char *chip_0_boot_name = "gpmi-nfc-0-boot";
+ static char *general_use_name = "gpmi-nfc-general-use";
+ struct mtd_partition partitions[2];
+
+ pr_info("Boot area protection is enabled.\n");
+ /*
+ * We partition the medium like so:
+ *
+ * +------+----------------------------------------------------+
+ * | Boot | General Use |
+ * +------+----------------------------------------------------+
+ */
+
+ /* Chip 0 Boot */
+ partitions[0].name = chip_0_boot_name;
+ partitions[0].offset = 0;
+ partitions[0].size = rom->boot_area_size_in_bytes;
+ partitions[0].mask_flags = 0;
+
+ /* General Use */
+ partitions[1].name = general_use_name;
+ partitions[1].offset = rom->boot_area_size_in_bytes;
+ partitions[1].size = MTDPART_SIZ_FULL;
+ partitions[1].mask_flags = 0;
+
+ /* Construct and register the partitions. */
+ add_mtd_partitions(mtd, partitions, 2);
+
+ /* Find the general use MTD. */
+ mil->general_use_mtd = get_mtd_device_nm(general_use_name);
+ if (IS_ERR(mil->general_use_mtd)) {
+ log("Can't find general use MTD");
+ BUG();
+ }
+ } else {
+ log("Boot area count greater than one is unimplemented.");
+ return -ENXIO;
+ }
+ return 0;
+}
+
+static void mil_boot_areas_exit(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_geometry *rom = &this->rom_geometry;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+
+ if (!rom->boot_area_count) {
+ mil->general_use_mtd = NULL;
+ return;
+ }
+ del_mtd_partitions(mtd);
+ mil->general_use_mtd = NULL;
+}
+
+static int construct_general_use_partitions(struct gpmi_nfc_data *this)
+{
+ struct mil *mil = &this->mil;
+ unsigned int partition_count;
+ struct mtd_partition *partitions;
+ unsigned int name_size;
+ char *names;
+ unsigned int size;
+ unsigned int i;
+ static const char *name_prefix = "gpmi-nfc-ubi-";
+
+ /* Only handle the MTD which is larger than 2GiB. */
+ if (mil->general_use_mtd->size <= SZ_2G)
+ return 0;
+
+ /* Split it by 2G for historical reason*/
+ partition_count = mil->general_use_mtd->size >> 31;
+ if (mil->general_use_mtd->size & ((1 << 30) - 1))
+ partition_count++;
+
+ /* construct the partitions */
+ name_size = strlen(name_prefix) + 4;
+ size = (sizeof(*partitions) + name_size) * partition_count;
+ partitions = kzalloc(size, GFP_KERNEL);
+ if (!partitions) {
+ log("Could not allocate memory for UBI partitions.");
+ return -ENOMEM;
+ }
+
+ names = (char *)(partitions + partition_count);
+ for (i = 0; i < partition_count; i++) {
+ partitions[i].name = names;
+ partitions[i].size = SZ_2G;
+ partitions[i].offset = MTDPART_OFS_NXTBLK;
+
+ sprintf(names, "%s%u", name_prefix, i);
+ names += name_size;
+ }
+ /* Adjust the last partition to take up the remainder. */
+ partitions[i - 1].size = MTDPART_SIZ_FULL;
+
+ mil->partitions = partitions;
+ mil->partition_count = partition_count;
+ return 0;
+}
+
+static int mil_partitions_init(struct gpmi_nfc_data *this)
+{
+ struct mil *mil = &this->mil;
+ int error;
+
+ error = mil_boot_areas_init(this);
+ if (error)
+ return error;
+
+ /* Construct partitions */
+ error = construct_general_use_partitions(this);
+ if (error) {
+ log("error : %d", error);
+ return error;
+ }
+ if (mil->partition_count)
+ add_mtd_partitions(mil->general_use_mtd, mil->partitions,
+ mil->partition_count);
+ return 0;
+}
+
+static void mil_partitions_exit(struct gpmi_nfc_data *this)
+{
+ struct mil *mil = &this->mil;
+
+ if (mil->partition_count) {
+ del_mtd_partitions(mil->general_use_mtd);
+ kfree(mil->partitions);
+ mil->partition_count = 0;
+ }
+ mil_boot_areas_exit(this);
+}
+
+/*
+ * This function is used to set the mtd->pagesize, mtd->oobsize,
+ * mtd->erasesize. Yes, we also do some initialization.
+ *
+ * Return with the bus width. 0 for 8-bit, -1 for error.
+ */
+static int gpmi_init_size(struct mtd_info *mtd, struct nand_chip *nand,
+ u8 *id_bytes)
+{
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct mil *mil = &this->mil;
+ struct nand_ecclayout *layout = &mil->oob_layout;
+ struct nand_device_info *info;
+ struct nand_attr *attr;
+ int error;
+
+ /* Look up this device in our own database. */
+ info = nand_device_get_info(id_bytes);
+ if (!info) {
+ pr_err("Unrecognized NAND Flash device.\n");
+ return -EINVAL;
+ } else if (gpmi_debug & GPMI_DEBUG_INIT)
+ nand_device_print_info(info);
+ else
+ pr_info("We found nand : [ %s ]\n", info->desc);
+
+ attr = &info->attr;
+ /*
+ * Init the right NAND/MTD parameters which will be used
+ * in the following mil_set_geometry().
+ */
+ mtd->writesize = 1 << (fls(attr->page_total_size_in_bytes) - 1);
+ mtd->erasesize = mtd->writesize * attr->block_size_in_pages;
+ mtd->oobsize = attr->page_total_size_in_bytes - mtd->writesize;
+ nand->chipsize = attr->chip_size_in_bytes;
+
+ /* Configure the struct nand_ecclayout. */
+ layout->eccbytes = 0;
+ layout->oobavail = mtd->oobsize;
+ layout->oobfree[0].offset = 0;
+ layout->oobfree[0].length = mtd->oobsize;
+
+ nand->ecc.layout = layout;
+
+ /* copy it. */
+ this->device_info = *info;
+ this->device_info.desc = kstrdup(info->desc, GFP_KERNEL);
+
+ /* Set up the medium geometry */
+ error = mil_set_geometry(this);
+ if (error)
+ return error;
+
+ /* extra init */
+ if (nfc->extra_init) {
+ error = nfc->extra_init(this);
+ if (error != 0)
+ return error;
+ }
+
+ /* We only use 8-bit bus now, not 16-bit. */
+ return 0;
+}
+
+/* Initializes the MTD Interface Layer */
+int gpmi_nfc_mil_init(struct gpmi_nfc_data *this)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+ struct nand_chip *nand = &mil->nand;
+ int error;
+
+ /* Initialize MIL data */
+ mil->current_chip = -1;
+ mil->command_length = 0;
+ mil->page_buffer_virt = 0;
+ mil->page_buffer_phys = ~0;
+ mil->page_buffer_size = 0;
+
+ /* Initialize the MTD data structures */
+ mtd->priv = nand;
+ mtd->name = "gpmi-nfc-main";
+ mtd->owner = THIS_MODULE;
+ nand->priv = this;
+
+ /* Controls */
+ nand->select_chip = mil_select_chip;
+ nand->cmd_ctrl = mil_cmd_ctrl;
+ nand->dev_ready = mil_dev_ready;
+
+ /*
+ * Low-level I/O :
+ * We don't support a 16-bit NAND Flash bus,
+ * so we don't implement read_word.
+ */
+ nand->read_byte = mil_read_byte;
+ nand->read_buf = mil_read_buf;
+ nand->write_buf = mil_write_buf;
+
+ /* ECC-aware I/O */
+ nand->ecc.read_page = mil_ecc_read_page;
+ nand->ecc.write_page = mil_ecc_write_page;
+
+ /* High-level I/O */
+ nand->ecc.read_oob = mil_ecc_read_oob;
+ nand->ecc.write_oob = mil_ecc_write_oob;
+
+ /* Bad Block Management */
+ nand->block_bad = mil_block_bad;
+ nand->scan_bbt = mil_scan_bbt;
+ nand->init_size = gpmi_init_size;
+ nand->badblock_pattern = &gpmi_bbt_descr;
+
+ /* Disallow partial page writes */
+ nand->options |= NAND_NO_SUBPAGE_WRITE;
+
+ /*
+ * Tell the NAND Flash MTD system that we'll be handling ECC with our
+ * own hardware. It turns out that we still have to fill in the ECC size
+ * because the MTD code will divide by it -- even though it doesn't
+ * actually care.
+ */
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.size = 1;
+
+ /* Allocate a temporary DMA buffer for reading ID in the nand_scan() */
+ this->nfc_geometry.payload_size_in_bytes = 1024;
+ this->nfc_geometry.auxiliary_size_in_bytes = 128;
+ error = mil_alloc_dma_buffer(this);
+ if (error)
+ goto exit_dma_allocation;
+
+ pr_info("Scanning for NAND Flash chips...\n");
+ error = nand_scan(mtd, pdata->max_chip_count);
+ if (error) {
+ log("Chip scan failed");
+ goto exit_nand_scan;
+ }
+
+ /* Take over the management of the OOB */
+ mil->hooked_block_markbad = mtd->block_markbad;
+ mtd->block_markbad = mil_hook_block_markbad;
+
+ /* Construct partitions as necessary. */
+ error = mil_partitions_init(this);
+ if (error)
+ goto exit_partitions;
+ return 0;
+
+exit_partitions:
+ nand_release(&mil->mtd);
+exit_nand_scan:
+ mil_free_dma_buffer(this);
+exit_dma_allocation:
+ return error;
+}
+
+void gpmi_nfc_mil_exit(struct gpmi_nfc_data *this)
+{
+ struct mil *mil = &this->mil;
+
+ mil_partitions_exit(this);
+ nand_release(&mil->mtd);
+ mil_free_dma_buffer(this);
+}
+static int gpmi_nfc_probe(struct platform_device *pdev)
+{
+ struct gpmi_nfc_platform_data *pdata = pdev->dev.platform_data;
+ struct gpmi_nfc_data *this;
+ int error;
+
+ this = kzalloc(sizeof(*this), GFP_KERNEL);
+ if (!this) {
+ log("Failed to allocate per-device memory\n");
+ return -ENOMEM;
+ }
+
+ /* Set up our data structures. */
+ platform_set_drvdata(pdev, this);
+ this->pdev = pdev;
+ this->dev = &pdev->dev;
+ this->pdata = pdata;
+
+ /* Acquire the resources we need. */
+ error = acquire_resources(this);
+ if (error)
+ goto exit_acquire_resources;
+
+ /* Set up the NFC. */
+ error = set_up_nfc_hal(this);
+ if (error)
+ goto exit_nfc_init;
+
+ /* Set up the Boot ROM Helper. */
+ error = set_up_boot_rom_helper(this);
+ if (error)
+ goto exit_boot_rom_helper_init;
+
+ /* Initialize the MTD Interface Layer. */
+ error = gpmi_nfc_mil_init(this);
+ if (error)
+ goto exit_mil_init;
+
+ manage_sysfs_files(this, true);
+ return 0;
+
+exit_mil_init:
+exit_boot_rom_helper_init:
+ exit_nfc_hal(this);
+exit_nfc_init:
+ release_resources(this);
+exit_acquire_resources:
+ platform_set_drvdata(pdev, NULL);
+ kfree(this);
+ return error;
+}
+
+static int __exit gpmi_nfc_remove(struct platform_device *pdev)
+{
+ struct gpmi_nfc_data *this = platform_get_drvdata(pdev);
+
+ manage_sysfs_files(this, false);
+ gpmi_nfc_mil_exit(this);
+ exit_nfc_hal(this);
+ release_resources(this);
+ platform_set_drvdata(pdev, NULL);
+ kfree(this);
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int gpmi_nfc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ return 0;
+}
+
+static int gpmi_nfc_resume(struct platform_device *pdev)
+{
+ return 0;
+}
+#else
+#define suspend NULL
+#define resume NULL
+#endif
+
+/* This structure represents this driver to the platform management system. */
+static struct platform_driver gpmi_nfc_driver = {
+ .driver = {
+ .name = GPMI_NFC_DRIVER_NAME,
+ },
+ .probe = gpmi_nfc_probe,
+ .remove = __exit_p(gpmi_nfc_remove),
+ .suspend = gpmi_nfc_suspend,
+ .resume = gpmi_nfc_resume,
+};
+
+static int __init gpmi_nfc_init(void)
+{
+ int err;
+
+ err = platform_driver_register(&gpmi_nfc_driver);
+ if (err == 0)
+ printk(KERN_INFO "GPMI NFC driver registered. (IMX)\n");
+ else
+ pr_err("i.MX GPMI NFC driver registration failed\n");
+ return err;
+}
+
+static void __exit gpmi_nfc_exit(void)
+{
+ platform_driver_unregister(&gpmi_nfc_driver);
+}
+
+static int __init gpmi_debug_setup(char *__unused)
+{
+ gpmi_debug = GPMI_DEBUG_INIT;
+ return 1;
+}
+__setup("gpmi_debug_init", gpmi_debug_setup);
+
+module_init(gpmi_nfc_init);
+module_exit(gpmi_nfc_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("i.MX GPMI NAND Flash Controller Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
new file mode 100644
index 0000000..d81262b
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
@@ -0,0 +1,549 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __DRIVERS_MTD_NAND_GPMI_NFC_H
+#define __DRIVERS_MTD_NAND_GPMI_NFC_H
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/concat.h>
+#include <linux/dmaengine.h>
+#include <asm/sizes.h>
+
+#include <mach/mxs.h>
+#include <mach/common.h>
+#include <mach/dma.h>
+#include <mach/gpmi-nfc.h>
+#include <mach/system.h>
+#include <mach/clock.h>
+
+#include "../nand_device_info.h"
+
+/**
+ * struct resources - The collection of resources the driver needs.
+ *
+ * @gpmi_regs: A pointer to the GPMI registers.
+ * @bch_regs: A pointer to the BCH registers.
+ * @bch_interrupt: The BCH interrupt number.
+ * @dma_low_channel: The low DMA channel.
+ * @dma_high_channel: The high DMA channel.
+ * @clock: A pointer to the struct clk for the NFC's clock.
+ */
+struct resources {
+ void *gpmi_regs;
+ void *bch_regs;
+ unsigned int bch_low_interrupt;
+ unsigned int bch_high_interrupt;
+ unsigned int dma_low_channel;
+ unsigned int dma_high_channel;
+ struct clk *clock;
+};
+
+/**
+ * struct mil - State for the MTD Interface Layer.
+ *
+ * @nand: The NAND Flash MTD data structure that represents
+ * the NAND Flash medium.
+ * @mtd: The MTD data structure that represents the NAND
+ * Flash medium.
+ * @oob_layout: A structure that describes how bytes are laid out
+ * in the OOB.
+ * @general_use_mtd: A pointer to an MTD we export for general use.
+ * This *may* simply be a pointer to the mtd field, if
+ * we've been instructed NOT to protect the boot
+ * areas.
+ * @partitions: A pointer to a set of partitions applied to the
+ * general use MTD.
+ * @partition_count: The number of partitions.
+ * @current_chip: The chip currently selected by the NAND Fash MTD
+ * code. A negative value indicates that no chip is
+ * selected.
+ * @command_length: The length of the command that appears in the
+ * command buffer (see cmd_virt, below).
+ * @ignore_bad_block_marks: Indicates we are ignoring bad block marks.
+ * @saved_bbt: A saved pointer to the in-memory NAND Flash MTD bad
+ * block table. See show_device_ignorebad() for more
+ * details.
+ * @marking_a_bad_block: Indicates the caller is marking a bad block. See
+ * mil_ecc_write_oob() for details.
+ * @hooked_block_markbad: A pointer to the block_markbad() function we
+ * we "hooked." See mil_ecc_write_oob() for details.
+ * @upper_buf: The buffer passed from upper layer.
+ * @upper_len: The buffer len passed from upper layer.
+ * @direct_dma_map_ok: Is the direct DMA map is good for the upper_buf?
+ * @cmd_sgl/cmd_buffer: For NAND command.
+ * @data_sgl/data_buffer_dma:For NAND DATA ops.
+ * @page_buffer_virt: A pointer to a DMA-coherent buffer we use for
+ * reading and writing pages. This buffer includes
+ * space for both the payload data and the auxiliary
+ * data (including status bytes, but not syndrome
+ * bytes).
+ * @page_buffer_phys: The physical address for the page_buffer_virt
+ * buffer.
+ * @page_buffer_size: The size of the page buffer.
+ * @payload_virt: A pointer to a location in the page buffer used
+ * for payload bytes. The size of this buffer is
+ * determined by struct nfc_geometry.
+ * @payload_phys: The physical address for payload_virt.
+ * @auxiliary_virt: A pointer to a location in the page buffer used
+ * for auxiliary bytes. The size of this buffer is
+ * determined by struct nfc_geometry.
+ * @auxiliary_phys: The physical address for auxiliary_virt.
+ */
+struct mil {
+ /* MTD Data Structures */
+ struct nand_chip nand;
+ struct mtd_info mtd;
+ struct nand_ecclayout oob_layout;
+
+ /* Partitioning and Boot Area Protection */
+ struct mtd_info *general_use_mtd;
+ struct mtd_partition *partitions;
+ unsigned int partition_count;
+
+ /* General-use Variables */
+ int current_chip;
+ unsigned int command_length;
+ int ignore_bad_block_marks;
+ void *saved_bbt;
+
+ /* MTD Function Pointer Hooks */
+ int marking_a_bad_block;
+ int (*hooked_block_markbad)(struct mtd_info *mtd,
+ loff_t ofs);
+
+ /* from upper layer */
+ uint8_t *upper_buf;
+ int upper_len;
+
+ /* DMA */
+ bool direct_dma_map_ok;
+
+ struct scatterlist cmd_sgl;
+ char *cmd_buffer;
+
+ struct scatterlist data_sgl;
+ char *data_buffer_dma;
+
+ void *page_buffer_virt;
+ dma_addr_t page_buffer_phys;
+ unsigned int page_buffer_size;
+
+ void *payload_virt;
+ dma_addr_t payload_phys;
+
+ void *auxiliary_virt;
+ dma_addr_t auxiliary_phys;
+};
+
+/**
+ * struct nfc_geometry - NFC geometry description.
+ *
+ * This structure describes the NFC's view of the medium geometry.
+ *
+ * @ecc_algorithm: The human-readable name of the ECC algorithm
+ * (e.g., "Reed-Solomon" or "BCH").
+ * @ecc_strength: A number that describes the strength of the ECC
+ * algorithm.
+ * @page_size_in_bytes: The size, in bytes, of a physical page, including
+ * both data and OOB.
+ * @metadata_size_in_bytes: The size, in bytes, of the metadata.
+ * @ecc_chunk_size_in_bytes: The size, in bytes, of a single ECC chunk. Note
+ * the first chunk in the page includes both data and
+ * metadata, so it's a bit larger than this value.
+ * @ecc_chunk_count: The number of ECC chunks in the page,
+ * @payload_size_in_bytes: The size, in bytes, of the payload buffer.
+ * @auxiliary_size_in_bytes: The size, in bytes, of the auxiliary buffer.
+ * @auxiliary_status_offset: The offset into the auxiliary buffer at which
+ * the ECC status appears.
+ * @block_mark_byte_offset: The byte offset in the ECC-based page view at
+ * which the underlying physical block mark appears.
+ * @block_mark_bit_offset: The bit offset into the ECC-based page view at
+ * which the underlying physical block mark appears.
+ */
+struct nfc_geometry {
+ char *ecc_algorithm;
+ unsigned int ecc_strength;
+ unsigned int page_size_in_bytes;
+ unsigned int metadata_size_in_bytes;
+ unsigned int ecc_chunk_size_in_bytes;
+ unsigned int ecc_chunk_count;
+ unsigned int payload_size_in_bytes;
+ unsigned int auxiliary_size_in_bytes;
+ unsigned int auxiliary_status_offset;
+ unsigned int block_mark_byte_offset;
+ unsigned int block_mark_bit_offset;
+};
+
+/**
+ * struct boot_rom_geometry - Boot ROM geometry description.
+ *
+ * This structure encapsulates decisions made by the Boot ROM Helper.
+ *
+ * @boot_area_count: The number of boot areas. The first boot area
+ * appears at the beginning of chip 0, the next
+ * at the beginning of chip 1, etc.
+ * @boot_area_size_in_bytes: The size, in bytes, of each boot area.
+ * @stride_size_in_pages: The size of a boot block stride, in pages.
+ * @search_area_stride_exponent: The logarithm to base 2 of the size of a
+ * search area in boot block strides.
+ */
+struct boot_rom_geometry {
+ unsigned int boot_area_count;
+ unsigned int boot_area_size_in_bytes;
+ unsigned int stride_size_in_pages;
+ unsigned int search_area_stride_exponent;
+};
+
+/* DMA operations types */
+enum dma_ops_type {
+ DMA_FOR_COMMAND = 1,
+ DMA_FOR_READ_DATA,
+ DMA_FOR_WRITE_DATA,
+ DMA_FOR_READ_ECC_PAGE,
+ DMA_FOR_WRITE_ECC_PAGE
+};
+
+/**
+ * This structure contains the fundamental timing attributes for NAND.
+ *
+ * @data_setup_in_ns: The data setup time, in nanoseconds. Usually the
+ * maximum of tDS and tWP. A negative value
+ * indicates this characteristic isn't known.
+ * @data_hold_in_ns: The data hold time, in nanoseconds. Usually the
+ * maximum of tDH, tWH and tREH. A negative value
+ * indicates this characteristic isn't known.
+ * @address_setup_in_ns: The address setup time, in nanoseconds. Usually
+ * the maximum of tCLS, tCS and tALS. A negative
+ * value indicates this characteristic isn't known.
+ * @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative value
+ * indicates this characteristic isn't known.
+ * @tREA_in_ns: tREA, in nanoseconds, from the data sheet. A
+ * negative value indicates this characteristic isn't
+ * known.
+ * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet. A
+ * negative value indicates this characteristic isn't
+ * known.
+ * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet. A
+ * negative value indicates this characteristic isn't
+ * known.
+ */
+struct nand_timing {
+ int8_t data_setup_in_ns;
+ int8_t data_hold_in_ns;
+ int8_t address_setup_in_ns;
+ int8_t gpmi_sample_delay_in_ns;
+ int8_t tREA_in_ns;
+ int8_t tRLOH_in_ns;
+ int8_t tRHOH_in_ns;
+};
+
+/**
+ * struct gpmi_nfc_data - i.MX NFC per-device data.
+ *
+ * Note that the "device" managed by this driver represents the NAND Flash
+ * controller *and* the NAND Flash medium behind it. Thus, the per-device data
+ * structure has information about the controller, the chips to which it is
+ * connected, and properties of the medium as a whole.
+ *
+ * @dev: A pointer to the owning struct device.
+ * @pdev: A pointer to the owning struct platform_device.
+ * @pdata: A pointer to the device's platform data.
+ * @resources: Information about system resources used by this driver.
+ * @device_info: A structure that contains detailed information about
+ * the NAND Flash device.
+ * @nfc: A pointer to a structure that represents the underlying
+ * NFC hardware.
+ * @nfc_geometry: A description of the medium geometry as viewed by the
+ * NFC.
+ * @rom: A pointer to a structure that represents the underlying
+ * Boot ROM.
+ * @rom_geometry: A description of the medium geometry as viewed by the
+ * Boot ROM.
+ * @mil: A collection of information used by the MTD Interface
+ * Layer.
+ */
+struct gpmi_nfc_data {
+ /* System Interface */
+ struct device *dev;
+ struct platform_device *pdev;
+ struct gpmi_nfc_platform_data *pdata;
+
+ /* Resources */
+ struct resources resources;
+
+ /* Flash Hardware */
+ struct nand_device_info device_info;
+ struct nand_timing timing;
+
+ /* NFC HAL */
+ struct nfc_hal *nfc;
+ struct nfc_geometry nfc_geometry;
+
+ /* Boot ROM Helper */
+ struct boot_rom_helper *rom;
+ struct boot_rom_geometry rom_geometry;
+
+ /* MTD Interface Layer */
+ struct mil mil;
+
+ /* DMA channels */
+#define DMA_CHANS 8
+ struct dma_chan *dma_chans[DMA_CHANS];
+ struct mxs_dma_data dma_data;
+ enum dma_ops_type dma_type;
+
+ /* private */
+ void *private;
+};
+
+/**
+ * struct gpmi_nfc_hardware_timing - GPMI NFC hardware timing parameters.
+ *
+ * This structure contains timing information expressed in a form directly
+ * usable by the GPMI NFC hardware.
+ *
+ * @data_setup_in_cycles: The data setup time, in cycles.
+ * @data_hold_in_cycles: The data hold time, in cycles.
+ * @address_setup_in_cycles: The address setup time, in cycles.
+ * @use_half_periods: Indicates the clock is running slowly, so the
+ * NFC DLL should use half-periods.
+ * @sample_delay_factor: The sample delay factor.
+ */
+struct gpmi_nfc_hardware_timing {
+ uint8_t data_setup_in_cycles;
+ uint8_t data_hold_in_cycles;
+ uint8_t address_setup_in_cycles;
+ bool use_half_periods;
+ uint8_t sample_delay_factor;
+};
+
+/**
+ * struct nfc_hal - GPMI NFC HAL
+ *
+ * This structure embodies an abstract interface to the underlying NFC hardware.
+ *
+ * @version: The NFC hardware version.
+ * @description: A pointer to a human-readable description of
+ * the NFC hardware.
+ * @max_chip_count: The maximum number of chips the NFC can
+ * possibly support (this value is a constant for
+ * each NFC version). This may *not* be the actual
+ * number of chips connected.
+ * @max_data_setup_cycles: The maximum number of data setup cycles that
+ * can be expressed in the hardware.
+ * @internal_data_setup_in_ns: The time, in ns, that the NFC hardware requires
+ * for data read internal setup. In the Reference
+ * Manual, see the chapter "High-Speed NAND
+ * Timing" for more details.
+ * @max_sample_delay_factor: The maximum sample delay factor that can be
+ * expressed in the hardware.
+ * @max_dll_clock_period_in_ns: The maximum period of the GPMI clock that the
+ * sample delay DLL hardware can possibly work
+ * with (the DLL is unusable with longer periods).
+ * If the full-cycle period is greater than HALF
+ * this value, the DLL must be configured to use
+ * half-periods.
+ * @max_dll_delay_in_ns: The maximum amount of delay, in ns, that the
+ * DLL can implement.
+ * @dma_descriptors: A pool of DMA descriptors.
+ * @isr_dma_channel: The DMA channel with which the NFC HAL is
+ * working. We record this here so the ISR knows
+ * which DMA channel to acknowledge.
+ * @dma_done: The completion structure used for DMA
+ * interrupts.
+ * @bch_done: The completion structure used for BCH
+ * interrupts.
+ * @timing: The current timing configuration.
+ * @clock_frequency_in_hz: The clock frequency, in Hz, during the current
+ * I/O transaction. If no I/O transaction is in
+ * progress, this is the clock frequency during
+ * the most recent I/O transaction.
+ * @hardware_timing: The hardware timing configuration in effect
+ * during the current I/O transaction. If no I/O
+ * transaction is in progress, this is the
+ * hardware timing configuration during the most
+ * recent I/O transaction.
+ * @init: Initializes the NFC hardware and data
+ * structures. This function will be called after
+ * everything has been set up for communication
+ * with the NFC itself, but before the platform
+ * has set up off-chip communication. Thus, this
+ * function must not attempt to communicate with
+ * the NAND Flash hardware.
+ * @set_geometry: Configures the NFC hardware and data structures
+ * to match the physical NAND Flash geometry.
+ * @set_geometry: Configures the NFC hardware and data structures
+ * to match the physical NAND Flash geometry.
+ * @set_timing: Configures the NFC hardware and data structures
+ * to match the given NAND Flash bus timing.
+ * @get_timing: Returns the the clock frequency, in Hz, and
+ * the hardware timing configuration during the
+ * current I/O transaction. If no I/O transaction
+ * is in progress, this is the timing state during
+ * the most recent I/O transaction.
+ * @exit: Shuts down the NFC hardware and data
+ * structures. This function will be called after
+ * the platform has shut down off-chip
+ * communication but while communication with the
+ * NFC itself still works.
+ * @clear_bch: Clears a BCH interrupt (intended to be called
+ * by a more general interrupt handler to do
+ * device-specific clearing).
+ * @is_ready: Returns true if the given chip is ready.
+ * @begin: Begins an interaction with the NFC. This
+ * function must be called before *any* of the
+ * following functions so the NFC can prepare
+ * itself.
+ * @end: Ends interaction with the NFC. This function
+ * should be called to give the NFC a chance to,
+ * among other things, enter a lower-power state.
+ * @send_command: Sends the given buffer of command bytes.
+ * @send_data: Sends the given buffer of data bytes.
+ * @read_data: Reads data bytes into the given buffer.
+ * @send_page: Sends the given given data and OOB bytes,
+ * using the ECC engine.
+ * @read_page: Reads a page through the ECC engine and
+ * delivers the data and OOB bytes to the given
+ * buffers.
+ */
+struct nfc_hal {
+ /* Hardware attributes. */
+ const unsigned int version;
+ const char *description;
+ const unsigned int max_chip_count;
+ const unsigned int max_data_setup_cycles;
+ const unsigned int internal_data_setup_in_ns;
+ const unsigned int max_sample_delay_factor;
+ const unsigned int max_dll_clock_period_in_ns;
+ const unsigned int max_dll_delay_in_ns;
+
+ int isr_dma_channel;
+ struct completion dma_done;
+ struct completion bch_done;
+ struct nand_timing timing;
+ unsigned long clock_frequency_in_hz;
+
+ /* Configuration functions. */
+ int (*init) (struct gpmi_nfc_data *);
+ int (*extra_init) (struct gpmi_nfc_data *);
+ int (*set_geometry)(struct gpmi_nfc_data *);
+ int (*set_timing) (struct gpmi_nfc_data *,
+ const struct nand_timing *);
+ void (*get_timing) (struct gpmi_nfc_data *,
+ unsigned long *clock_frequency_in_hz,
+ struct gpmi_nfc_hardware_timing *);
+ void (*exit) (struct gpmi_nfc_data *);
+
+ /* Call these functions to begin and end I/O. */
+ void (*begin) (struct gpmi_nfc_data *);
+ void (*end) (struct gpmi_nfc_data *);
+
+ /* Call these I/O functions only between begin() and end(). */
+ void (*clear_bch) (struct gpmi_nfc_data *);
+ int (*is_ready) (struct gpmi_nfc_data *, unsigned chip);
+ int (*send_command)(struct gpmi_nfc_data *);
+ int (*send_data) (struct gpmi_nfc_data *);
+ int (*read_data) (struct gpmi_nfc_data *);
+ int (*send_page) (struct gpmi_nfc_data *,
+ dma_addr_t payload, dma_addr_t auxiliary);
+ int (*read_page) (struct gpmi_nfc_data *,
+ dma_addr_t payload, dma_addr_t auxiliary);
+};
+
+/**
+ * struct boot_rom_helper - Boot ROM Helper
+ *
+ * This structure embodies the interface to an object that assists the driver
+ * in making decisions that relate to the Boot ROM.
+ *
+ * @version: The Boot ROM version.
+ * @description: A pointer to a human-readable description of the
+ * Boot ROM.
+ * @swap_block_mark: Indicates that the Boot ROM will swap the block
+ * mark with the first byte of the OOB.
+ * @set_geometry: Configures the Boot ROM geometry.
+ * @rom_extra_init: Arch-specific init.
+ */
+struct boot_rom_helper {
+ const unsigned int version;
+ const char *description;
+ const int swap_block_mark;
+ int (*set_geometry) (struct gpmi_nfc_data *);
+ int (*rom_extra_init) (struct gpmi_nfc_data *);
+};
+
+/* NFC HAL Common Services */
+extern int common_nfc_set_geometry(struct gpmi_nfc_data *this);
+extern int gpmi_nfc_compute_hardware_timing(struct gpmi_nfc_data *this,
+ struct gpmi_nfc_hardware_timing *hw);
+extern struct dma_chan *get_dma_chan(struct gpmi_nfc_data *this);
+extern void prepare_data_dma(struct gpmi_nfc_data *this,
+ enum dma_data_direction dr);
+extern int start_dma_without_bch_irq(struct gpmi_nfc_data *this,
+ struct dma_async_tx_descriptor *desc);
+extern int start_dma_with_bch_irq(struct gpmi_nfc_data *this,
+ struct dma_async_tx_descriptor *desc);
+/* NFC HAL Structures */
+extern struct nfc_hal gpmi_nfc_hal_imx23_imx28;
+
+/* Boot ROM Helper Common Services */
+extern int gpmi_nfc_rom_helper_set_geometry(struct gpmi_nfc_data *this);
+
+/* Boot ROM Helper Structures */
+extern struct boot_rom_helper gpmi_nfc_boot_rom_imx23;
+extern struct boot_rom_helper gpmi_nfc_boot_rom_imx28;
+
+/* MTD Interface Layer */
+extern int gpmi_nfc_mil_init(struct gpmi_nfc_data *this);
+extern void gpmi_nfc_mil_exit(struct gpmi_nfc_data *this);
+
+/* for log */
+extern int gpmi_debug;
+#define GPMI_DEBUG_INIT 0x0001
+#define GPMI_DEBUG_READ 0x0002
+#define GPMI_DEBUG_WRITE 0x0004
+#define GPMI_DEBUG_ECC_READ 0x0008
+#define GPMI_DEBUG_ECC_WRITE 0x0010
+
+#define log(a, ...) printk(KERN_INFO "[ %s : %.3d ] "a"\n", \
+ __func__, __LINE__, ## __VA_ARGS__)
+#define logio(level) \
+ do { \
+ if (gpmi_debug & level) \
+ log(); \
+ } while (0)
+
+/* BCH : Status Block Completion Codes */
+#define STATUS_GOOD 0x00
+#define STATUS_ERASED 0xff
+#define STATUS_UNCORRECTABLE 0xfe
+
+#endif
--
1.7.0.4
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH V3 5/6] MTD: add support for imx23 and imx28
2011-03-30 8:40 [PATCH V3 0/6] add the GPMI controller driver for IMX23/IMX28 Huang Shijie
` (3 preceding siblings ...)
2011-03-30 8:40 ` [PATCH V3 4/6] MTD : add the common code for GPMI controller driver Huang Shijie
@ 2011-03-30 8:40 ` Huang Shijie
2011-03-30 8:40 ` [PATCH V3 6/6] MTD : add GPMI driver in the config and Makefile Huang Shijie
5 siblings, 0 replies; 31+ messages in thread
From: Huang Shijie @ 2011-03-30 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux, David.Woodhouse, dedekind1, Huang Shijie, linux-mtd,
ffainelli, shijie8
Add the code for imx23 and imx28.
The imx23 and imx28 share most of the same code.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/nand/gpmi-nfc/bch-mx23-mx28.h | 88 +++++
drivers/mtd/nand/gpmi-nfc/gpmi-mx23-mx28.h | 163 ++++++++
drivers/mtd/nand/gpmi-nfc/hal-mx23-mx28.c | 562 ++++++++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/rom-mx23.c | 300 +++++++++++++++
drivers/mtd/nand/gpmi-nfc/rom-mx28.c | 66 ++++
5 files changed, 1179 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/gpmi-nfc/bch-mx23-mx28.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-mx23-mx28.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-mx23-mx28.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-mx23.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-mx28.c
diff --git a/drivers/mtd/nand/gpmi-nfc/bch-mx23-mx28.h b/drivers/mtd/nand/gpmi-nfc/bch-mx23-mx28.h
new file mode 100644
index 0000000..90af8cf
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/bch-mx23-mx28.h
@@ -0,0 +1,88 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __GPMI_NFC_BCH_REGS_H
+#define __GPMI_NFC_BCH_REGS_H
+
+/*============================================================================*/
+#define HW_BCH_CTRL 0x00000000
+#define HW_BCH_CTRL_SET 0x00000004
+#define HW_BCH_CTRL_CLR 0x00000008
+#define HW_BCH_CTRL_TOG 0x0000000c
+
+#define BM_BCH_CTRL_COMPLETE_IRQ_EN (1 << 8)
+#define BM_BCH_CTRL_COMPLETE_IRQ (1 << 0)
+
+/*============================================================================*/
+#define HW_BCH_STATUS0 0x00000010
+#define HW_BCH_MODE 0x00000020
+#define HW_BCH_ENCODEPTR 0x00000030
+#define HW_BCH_DATAPTR 0x00000040
+#define HW_BCH_METAPTR 0x00000050
+#define HW_BCH_LAYOUTSELECT 0x00000070
+
+/*============================================================================*/
+#define HW_BCH_FLASH0LAYOUT0 0x00000080
+
+#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH0LAYOUT0_NBLOCKS (0xff << BP_BCH_FLASH0LAYOUT0_NBLOCKS)
+#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \
+ (((v) << BP_BCH_FLASH0LAYOUT0_NBLOCKS) & BM_BCH_FLASH0LAYOUT0_NBLOCKS)
+
+#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH0LAYOUT0_META_SIZE (0xff << BP_BCH_FLASH0LAYOUT0_META_SIZE)
+#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \
+ (((v) << BP_BCH_FLASH0LAYOUT0_META_SIZE)\
+ & BM_BCH_FLASH0LAYOUT0_META_SIZE)
+
+#define BP_BCH_FLASH0LAYOUT0_ECC0 12
+#define BM_BCH_FLASH0LAYOUT0_ECC0 (0xf << BP_BCH_FLASH0LAYOUT0_ECC0)
+#define BF_BCH_FLASH0LAYOUT0_ECC0(v) \
+ (((v) << BP_BCH_FLASH0LAYOUT0_ECC0) & BM_BCH_FLASH0LAYOUT0_ECC0)
+
+#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE \
+ (0xfff << BP_BCH_FLASH0LAYOUT0_DATA0_SIZE)
+#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) \
+ (((v) << BP_BCH_FLASH0LAYOUT0_DATA0_SIZE)\
+ & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+#define HW_BCH_FLASH0LAYOUT1 0x00000090
+
+#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE \
+ (0xffff << BP_BCH_FLASH0LAYOUT1_PAGE_SIZE)
+#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \
+ (((v) << BP_BCH_FLASH0LAYOUT1_PAGE_SIZE) \
+ & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE)
+
+#define BP_BCH_FLASH0LAYOUT1_ECCN 12
+#define BM_BCH_FLASH0LAYOUT1_ECCN (0xf << BP_BCH_FLASH0LAYOUT1_ECCN)
+#define BF_BCH_FLASH0LAYOUT1_ECCN(v) \
+ (((v) << BP_BCH_FLASH0LAYOUT1_ECCN) & BM_BCH_FLASH0LAYOUT1_ECCN)
+
+#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE \
+ (0xfff << BP_BCH_FLASH0LAYOUT1_DATAN_SIZE)
+#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) \
+ (((v) << BP_BCH_FLASH0LAYOUT1_DATAN_SIZE) \
+ & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE)
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-mx23-mx28.h b/drivers/mtd/nand/gpmi-nfc/gpmi-mx23-mx28.h
new file mode 100644
index 0000000..7d7f144
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-mx23-mx28.h
@@ -0,0 +1,163 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __GPMI_NFC_GPMI_REGS_H
+#define __GPMI_NFC_GPMI_REGS_H
+
+/*============================================================================*/
+#define HW_GPMI_CTRL0 0x00000000
+#define HW_GPMI_CTRL0_SET 0x00000004
+#define HW_GPMI_CTRL0_CLR 0x00000008
+#define HW_GPMI_CTRL0_TOG 0x0000000c
+
+#define BP_GPMI_CTRL0_COMMAND_MODE 24
+#define BM_GPMI_CTRL0_COMMAND_MODE (3 << BP_GPMI_CTRL0_COMMAND_MODE)
+#define BF_GPMI_CTRL0_COMMAND_MODE(v) \
+ (((v) << BP_GPMI_CTRL0_COMMAND_MODE) & BM_GPMI_CTRL0_COMMAND_MODE)
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
+
+#define BM_GPMI_CTRL0_WORD_LENGTH (1 << 23)
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1
+
+/* different in CS between imx23 and imx28 */
+#define BP_GPMI_CTRL0_CS 20
+#define MX23_BM_GPMI_CTRL0_CS (3 << BP_GPMI_CTRL0_CS)
+#define MX28_BM_GPMI_CTRL0_CS (7 << BP_GPMI_CTRL0_CS)
+#define BF_GPMI_CTRL0_CS(v) \
+ (((v) << 20) & \
+ (cpu_is_mx23() ? MX23_BM_GPMI_CTRL0_CS : MX28_BM_GPMI_CTRL0_CS))
+
+#define BP_GPMI_CTRL0_ADDRESS 17
+#define BM_GPMI_CTRL0_ADDRESS (3 << BP_GPMI_CTRL0_ADDRESS)
+#define BF_GPMI_CTRL0_ADDRESS(v) \
+ (((v) << BP_GPMI_CTRL0_ADDRESS) & BM_GPMI_CTRL0_ADDRESS)
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
+
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16)
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1
+
+#define BP_GPMI_CTRL0_XFER_COUNT 0
+#define BM_GPMI_CTRL0_XFER_COUNT (0xffff << BP_GPMI_CTRL0_XFER_COUNT)
+#define BF_GPMI_CTRL0_XFER_COUNT(v) \
+ (((v) << BP_GPMI_CTRL0_XFER_COUNT) & BM_GPMI_CTRL0_XFER_COUNT)
+
+/*============================================================================*/
+#define HW_GPMI_COMPARE 0x00000010
+/*============================================================================*/
+#define HW_GPMI_ECCCTRL 0x00000020
+#define HW_GPMI_ECCCTRL_SET 0x00000024
+#define HW_GPMI_ECCCTRL_CLR 0x00000028
+#define HW_GPMI_ECCCTRL_TOG 0x0000002c
+
+#define BP_GPMI_ECCCTRL_ECC_CMD 13
+#define BM_GPMI_ECCCTRL_ECC_CMD (3 << BP_GPMI_ECCCTRL_ECC_CMD)
+#define BF_GPMI_ECCCTRL_ECC_CMD(v) \
+ (((v) << BP_GPMI_ECCCTRL_ECC_CMD) & BM_GPMI_ECCCTRL_ECC_CMD)
+#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE 0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE 0x1
+
+#define BM_GPMI_ECCCTRL_ENABLE_ECC (1 << 12)
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0
+
+#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
+#define BM_GPMI_ECCCTRL_BUFFER_MASK (0x1ff << BP_GPMI_ECCCTRL_BUFFER_MASK)
+#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \
+ (((v) << BP_GPMI_ECCCTRL_BUFFER_MASK) & BM_GPMI_ECCCTRL_BUFFER_MASK)
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF
+
+/*============================================================================*/
+#define HW_GPMI_ECCCOUNT 0x00000030
+#define HW_GPMI_PAYLOAD 0x00000040
+#define HW_GPMI_AUXILIARY 0x00000050
+/*============================================================================*/
+#define HW_GPMI_CTRL1 0x00000060
+#define HW_GPMI_CTRL1_SET 0x00000064
+#define HW_GPMI_CTRL1_CLR 0x00000068
+#define HW_GPMI_CTRL1_TOG 0x0000006c
+
+#define BM_GPMI_CTRL1_BCH_MODE (1 << 18)
+
+#define BP_GPMI_CTRL1_DLL_ENABLE 17
+#define BM_GPMI_CTRL1_DLL_ENABLE (1 << BP_GPMI_CTRL1_DLL_ENABLE)
+
+#define BP_GPMI_CTRL1_HALF_PERIOD 16
+#define BM_GPMI_CTRL1_HALF_PERIOD (1 << BP_GPMI_CTRL1_HALF_PERIOD)
+
+#define BP_GPMI_CTRL1_RDN_DELAY 12
+#define BM_GPMI_CTRL1_RDN_DELAY (0xf << BP_GPMI_CTRL1_RDN_DELAY)
+#define BF_GPMI_CTRL1_RDN_DELAY(v) \
+ (((v) << BP_GPMI_CTRL1_RDN_DELAY) & BM_GPMI_CTRL1_RDN_DELAY)
+
+#define BM_GPMI_CTRL1_DEV_RESET (1 << 3)
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
+
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2)
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
+
+#define BM_GPMI_CTRL1_CAMERA_MODE (1 << 1)
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1
+
+#define BM_GPMI_CTRL1_GPMI_MODE (1 << 0)
+
+/*============================================================================*/
+#define HW_GPMI_TIMING0 0x00000070
+
+#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP (0xff << BP_GPMI_TIMING0_ADDRESS_SETUP)
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \
+ (((v) << BP_GPMI_TIMING0_ADDRESS_SETUP) & BM_GPMI_TIMING0_ADDRESS_SETUP)
+
+#define BP_GPMI_TIMING0_DATA_HOLD 8
+#define BM_GPMI_TIMING0_DATA_HOLD (0xff << BP_GPMI_TIMING0_DATA_HOLD)
+#define BF_GPMI_TIMING0_DATA_HOLD(v) \
+ (((v) << BP_GPMI_TIMING0_DATA_HOLD) & BM_GPMI_TIMING0_DATA_HOLD)
+
+#define BP_GPMI_TIMING0_DATA_SETUP 0
+#define BM_GPMI_TIMING0_DATA_SETUP (0xff << BP_GPMI_TIMING0_DATA_SETUP)
+#define BF_GPMI_TIMING0_DATA_SETUP(v) \
+ (((v) << BP_GPMI_TIMING0_DATA_SETUP) & BM_GPMI_TIMING0_DATA_SETUP)
+
+/*============================================================================*/
+#define HW_GPMI_TIMING1 0x00000080
+#define HW_GPMI_TIMING2 0x00000090
+#define HW_GPMI_DATA 0x000000a0
+/*============================ MX28 uses this to detect READY ================*/
+#define HW_GPMI_STAT 0x000000b0
+#define MX28_BP_GPMI_STAT_READY_BUSY 24
+#define MX28_BM_GPMI_STAT_READY_BUSY (0xff << MX28_BP_GPMI_STAT_READY_BUSY)
+#define MX28_BF_GPMI_STAT_READY_BUSY(v) \
+ (((v) << MX28_BP_GPMI_STAT_READY_BUSY) & MX28_BM_GPMI_STAT_READY_BUSY)
+/*============================ MX23 uses this to detect READY ================*/
+#define HW_GPMI_DEBUG 0x000000c0
+#define MX23_BP_GPMI_DEBUG_READY0 28
+#define MX23_BM_GPMI_DEBUG_READY0 (1 << MX23_BP_GPMI_DEBUG_READY0)
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/hal-mx23-mx28.c b/drivers/mtd/nand/gpmi-nfc/hal-mx23-mx28.c
new file mode 100644
index 0000000..3981346
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/hal-mx23-mx28.c
@@ -0,0 +1,562 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+#include "gpmi-mx23-mx28.h"
+#include "bch-mx23-mx28.h"
+
+static int init_hal(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+
+ /* Enable the clock */
+ clk_enable(resources->clock);
+
+ /* Reset the GPMI block. */
+ mxs_reset_block(resources->gpmi_regs);
+
+ /* Choose NAND mode. */
+ __raw_writel(BM_GPMI_CTRL1_GPMI_MODE,
+ resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+ /* Set the IRQ polarity. */
+ __raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Disable write protection. */
+ __raw_writel(BM_GPMI_CTRL1_DEV_RESET,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Select BCH ECC. */
+ __raw_writel(BM_GPMI_CTRL1_BCH_MODE,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Disable the clock. */
+ clk_disable(resources->clock);
+ return 0;
+}
+
+/* Configures the NFC geometry for BCH. */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ struct nfc_geometry *nfc = &this->nfc_geometry;
+ unsigned int block_count;
+ unsigned int block_size;
+ unsigned int metadata_size;
+ unsigned int ecc_strength;
+ unsigned int page_size;
+
+ if (common_nfc_set_geometry(this))
+ return !0;
+
+ block_count = nfc->ecc_chunk_count - 1;
+ block_size = nfc->ecc_chunk_size_in_bytes;
+ metadata_size = nfc->metadata_size_in_bytes;
+ ecc_strength = nfc->ecc_strength >> 1;
+ page_size = nfc->page_size_in_bytes;
+
+ clk_enable(resources->clock);
+
+ /*
+ * Reset the BCH block. Notice that we pass in true for the just_enable
+ * flag. This is because the soft reset for the version 0 BCH block
+ * doesn't work. If you try to soft reset the BCH block, it becomes
+ * unusable until the next hard reset.
+ */
+ mxs_reset_block(resources->bch_regs);
+
+ /* Configure layout 0. */
+ __raw_writel(
+ BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count) |
+ BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) |
+ BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength) |
+ BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size) ,
+ resources->bch_regs + HW_BCH_FLASH0LAYOUT0);
+
+ __raw_writel(
+ BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size) |
+ BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength) |
+ BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) ,
+ resources->bch_regs + HW_BCH_FLASH0LAYOUT1);
+
+ /* Set *all* chip selects to use layout 0. */
+ __raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT);
+
+ /* Enable interrupts. */
+ __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
+ resources->bch_regs + HW_BCH_CTRL_SET);
+
+ clk_disable(resources->clock);
+ return 0;
+}
+
+static int set_timing(struct gpmi_nfc_data *this,
+ const struct nand_timing *timing)
+{
+ struct nfc_hal *nfc = this->nfc;
+
+ nfc->timing = *timing;
+ return 0;
+}
+
+/**
+ * get_timing() - Retrieves the NFC hardware timing.
+ *
+ * @this: Per-device data.
+ * @clock_frequency_in_hz: The clock frequency, in Hz, during the current
+ * I/O transaction. If no I/O transaction is in
+ * progress, this is the clock frequency during the
+ * most recent I/O transaction.
+ * @hardware_timing: The hardware timing configuration in effect during
+ * the current I/O transaction. If no I/O transaction
+ * is in progress, this is the hardware timing
+ * configuration during the most recent I/O
+ * transaction.
+ */
+static void get_timing(struct gpmi_nfc_data *this,
+ unsigned long *clock_frequency_in_hz,
+ struct gpmi_nfc_hardware_timing *hardware_timing)
+{
+ struct resources *resources = &this->resources;
+ struct nfc_hal *nfc = this->nfc;
+ unsigned char *gpmi_regs = resources->gpmi_regs;
+ uint32_t register_image;
+
+ /* Return the clock frequency. */
+ *clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+
+ /* We'll be reading the hardware, so let's enable the clock. */
+ clk_enable(resources->clock);
+
+ /* Retrieve the hardware timing. */
+ register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0);
+
+ hardware_timing->data_setup_in_cycles =
+ (register_image & BM_GPMI_TIMING0_DATA_SETUP) >>
+ BP_GPMI_TIMING0_DATA_SETUP;
+
+ hardware_timing->data_hold_in_cycles =
+ (register_image & BM_GPMI_TIMING0_DATA_HOLD) >>
+ BP_GPMI_TIMING0_DATA_HOLD;
+
+ hardware_timing->address_setup_in_cycles =
+ (register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >>
+ BP_GPMI_TIMING0_ADDRESS_SETUP;
+
+ register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1);
+
+ hardware_timing->use_half_periods =
+ (register_image & BM_GPMI_CTRL1_HALF_PERIOD) >>
+ BP_GPMI_CTRL1_HALF_PERIOD;
+
+ hardware_timing->sample_delay_factor =
+ (register_image & BM_GPMI_CTRL1_RDN_DELAY) >>
+ BP_GPMI_CTRL1_RDN_DELAY;
+
+ /* We're done reading the hardware, so disable the clock. */
+ clk_disable(resources->clock);
+}
+
+static void exit(struct gpmi_nfc_data *this)
+{
+}
+
+/* Begin the I/O */
+static void begin(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ struct nfc_hal *nfc = this->nfc;
+ struct gpmi_nfc_hardware_timing hw;
+ unsigned char *gpmi_regs = resources->gpmi_regs;
+ unsigned int clock_period_in_ns;
+ uint32_t register_image;
+ unsigned int dll_wait_time_in_us;
+
+ /* Enable the clock. */
+ clk_enable(resources->clock);
+
+ /* set the timing for imx23 */
+ if (!cpu_is_mx23())
+ return;
+
+ /* Get the timing information we need. */
+ nfc->clock_frequency_in_hz = clk_get_rate(resources->clock);
+ clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
+
+ gpmi_nfc_compute_hardware_timing(this, &hw);
+
+ /* Set up all the simple timing parameters. */
+ register_image =
+ BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
+ BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) |
+ BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ;
+
+ __raw_writel(register_image, gpmi_regs + HW_GPMI_TIMING0);
+
+ /*
+ * HEY - PAY ATTENTION!
+ *
+ * DLL_ENABLE must be set to zero when setting RDN_DELAY or HALF_PERIOD.
+ */
+ __raw_writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+ /* Clear out the DLL control fields. */
+ __raw_writel(BM_GPMI_CTRL1_RDN_DELAY, gpmi_regs + HW_GPMI_CTRL1_CLR);
+ __raw_writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+ /* If no sample delay is called for, return immediately. */
+ if (!hw.sample_delay_factor)
+ return;
+
+ /* Configure the HALF_PERIOD flag. */
+
+ if (hw.use_half_periods)
+ __raw_writel(BM_GPMI_CTRL1_HALF_PERIOD,
+ gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Set the delay factor. */
+ __raw_writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor),
+ gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Enable the DLL. */
+ __raw_writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /*
+ * After we enable the GPMI DLL, we have to wait 64 clock cycles before
+ * we can use the GPMI.
+ *
+ * Calculate the amount of time we need to wait, in microseconds.
+ */
+ dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
+
+ if (!dll_wait_time_in_us)
+ dll_wait_time_in_us = 1;
+
+ /* Wait for the DLL to settle. */
+ udelay(dll_wait_time_in_us);
+}
+
+static void end(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ clk_disable(resources->clock);
+}
+
+/* Clears a BCH interrupt. */
+static void clear_bch(struct gpmi_nfc_data *this)
+{
+ struct resources *r = &this->resources;
+ __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
+}
+
+/* Returns the Ready/Busy status of the given chip. */
+static int is_ready(struct gpmi_nfc_data *this, unsigned chip)
+{
+ struct resources *resources = &this->resources;
+ uint32_t mask;
+ uint32_t reg;
+
+ if (cpu_is_mx23()) {
+ mask = MX23_BM_GPMI_DEBUG_READY0 << chip;
+ reg = __raw_readl(resources->gpmi_regs + HW_GPMI_DEBUG);
+ } else if (cpu_is_mx28()) {
+ mask = MX28_BF_GPMI_STAT_READY_BUSY(1 << chip);
+ reg = __raw_readl(resources->gpmi_regs + HW_GPMI_STAT);
+ } else
+ BUG();
+ return !!(reg & mask);
+}
+
+static int send_command(struct gpmi_nfc_data *this)
+{
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ struct dma_async_tx_descriptor *desc;
+ struct scatterlist *sgl;
+ u32 pio[3];
+
+ /* [1] send out the PIO words */
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(mil->current_chip)
+ | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
+ | BM_GPMI_CTRL0_ADDRESS_INCREMENT
+ | BF_GPMI_CTRL0_XFER_COUNT(mil->command_length);
+ pio[1] = pio[2] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] send out the COMMAND + ADDRESS string stored in @buffer */
+ sgl = &mil->cmd_sgl;
+
+ sg_init_one(sgl, mil->cmd_buffer, mil->command_length);
+ dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
+ desc = channel->device->device_prep_slave_sg(channel,
+ sgl, 1, DMA_TO_DEVICE, 1);
+ if (!desc) {
+ log("error");
+ return -1;
+ }
+
+ /* [3] submit the DMA */
+ this->dma_type = DMA_FOR_COMMAND;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int send_data(struct gpmi_nfc_data *this)
+{
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ uint32_t command_mode;
+ uint32_t address;
+ u32 pio[2];
+
+ /* [1] PIO */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(mil->current_chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] send DMA request */
+ prepare_data_dma(this, DMA_TO_DEVICE);
+ desc = channel->device->device_prep_slave_sg(channel, &mil->data_sgl,
+ 1, DMA_TO_DEVICE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+ /* [3] submit the DMA */
+ this->dma_type = DMA_FOR_WRITE_DATA;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int read_data(struct gpmi_nfc_data *this)
+{
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ u32 pio[2];
+
+ /* [1] : send PIO */
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(mil->current_chip)
+ | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
+ | BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] : send DMA request */
+ prepare_data_dma(this, DMA_FROM_DEVICE);
+ desc = channel->device->device_prep_slave_sg(channel, &mil->data_sgl,
+ 1, DMA_FROM_DEVICE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+
+ /* [3] : submit the DMA */
+ this->dma_type = DMA_FOR_READ_DATA;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int send_page(struct gpmi_nfc_data *this,
+ dma_addr_t payload, dma_addr_t auxiliary)
+{
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ uint32_t command_mode;
+ uint32_t address;
+ uint32_t ecc_command;
+ uint32_t buffer_mask;
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ int chip = mil->current_chip;
+ u32 pio[6];
+
+ /* A DMA descriptor that does an ECC page read. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+ ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
+ buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+ BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(0) ;
+ pio[1] = 0;
+ pio[2] =
+ BM_GPMI_ECCCTRL_ENABLE_ECC |
+ BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) |
+ BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+ pio[3] = geo->page_size_in_bytes;
+ pio[4] = payload;
+ pio[5] = auxiliary;
+
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+ this->dma_type = DMA_FOR_WRITE_ECC_PAGE;
+ return start_dma_with_bch_irq(this, desc);
+}
+
+static int read_page(struct gpmi_nfc_data *this,
+ dma_addr_t payload, dma_addr_t auxiliary)
+{
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ uint32_t command_mode;
+ uint32_t address;
+ uint32_t ecc_command;
+ uint32_t buffer_mask;
+
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ int chip = mil->current_chip;
+ u32 pio[6];
+
+ /* [1] Wait for the chip to report ready. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(chip)
+ | BF_GPMI_CTRL0_ADDRESS(address)
+ | BF_GPMI_CTRL0_XFER_COUNT(0);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio, 2, DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] Enable the BCH block and read. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+ ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
+ buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
+ | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(chip)
+ | BF_GPMI_CTRL0_ADDRESS(address)
+ | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size_in_bytes);
+
+ pio[1] = 0;
+ pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
+ | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
+ | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
+ pio[3] = geo->page_size_in_bytes;
+ pio[4] = payload;
+ pio[5] = auxiliary;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+
+ /* [3] Disable the BCH block */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(geo->page_size_in_bytes) ;
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio, 2, DMA_NONE, 1);
+ if (!desc) {
+ log("step 3 error");
+ return -1;
+ }
+
+ /* [4] submit the DMA */
+ this->dma_type = DMA_FOR_READ_ECC_PAGE;
+ return start_dma_with_bch_irq(this, desc);
+}
+
+struct nfc_hal gpmi_nfc_hal_imx23_imx28 = {
+ .description = "GPMI and BCH for IMX23/IMX28",
+ .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >>
+ BP_GPMI_TIMING0_DATA_SETUP),
+ .internal_data_setup_in_ns = 0,
+ .max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >>
+ BP_GPMI_CTRL1_RDN_DELAY),
+ .max_dll_clock_period_in_ns = 32,
+ .max_dll_delay_in_ns = 16,
+ .init = init_hal,
+ .set_geometry = set_geometry,
+ .set_timing = set_timing,
+ .get_timing = get_timing,
+ .exit = exit,
+ .begin = begin,
+ .end = end,
+ .clear_bch = clear_bch,
+ .is_ready = is_ready,
+ .send_command = send_command,
+ .read_data = read_data,
+ .send_data = send_data,
+ .read_page = read_page,
+ .send_page = send_page,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/rom-mx23.c b/drivers/mtd/nand/gpmi-nfc/rom-mx23.c
new file mode 100644
index 0000000..8193874
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/rom-mx23.c
@@ -0,0 +1,300 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+
+/* Useful variables for Boot ROM Helper version 0. */
+static const char *fingerprint = "STMP";
+
+/* Sets geometry for the Boot ROM Helper. */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct boot_rom_geometry *geometry = &this->rom_geometry;
+ struct nand_chip *nand = &this->mil.nand;
+ int error;
+
+ error = gpmi_nfc_rom_helper_set_geometry(this);
+ if (error)
+ return error;
+
+ if (!pdata->boot_area_size_in_bytes) {
+ geometry->boot_area_count = 0;
+ geometry->boot_area_size_in_bytes = 0;
+ return 0;
+ }
+
+ if (nand->numchips == 1) {
+ geometry->boot_area_count = 1;
+ geometry->boot_area_size_in_bytes =
+ pdata->boot_area_size_in_bytes * 2;
+ } else {
+ geometry->boot_area_count = 2;
+ geometry->boot_area_size_in_bytes =
+ pdata->boot_area_size_in_bytes;
+ }
+ return 0;
+}
+
+static int check_transcription_stamp(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_geometry *rom_geo = &this->rom_geometry;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+ struct nand_chip *nand = &mil->nand;
+ unsigned int search_area_size_in_strides;
+ unsigned int stride;
+ unsigned int page;
+ loff_t byte;
+ uint8_t *buffer = nand->buffers->databuf;
+ int saved_chip_number;
+ int found_an_ncb_fingerprint = false;
+
+ /* Compute the number of strides in a search area. */
+ search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent;
+
+ /* Select chip 0. */
+ saved_chip_number = mil->current_chip;
+ nand->select_chip(mtd, 0);
+
+ /*
+ * Loop through the first search area, looking for the NCB fingerprint.
+ */
+ pr_info("Scanning for an NCB fingerprint...\n");
+
+ for (stride = 0; stride < search_area_size_in_strides; stride++) {
+ /* Compute the page and byte addresses. */
+ page = stride * rom_geo->stride_size_in_pages;
+ byte = page * mtd->writesize;
+
+ pr_info(" Looking for a fingerprint in page 0x%x\n", page);
+
+ /*
+ * Read the NCB fingerprint. The fingerprint is four bytes long
+ * and starts in the 12th byte of the page.
+ */
+ nand->cmdfunc(mtd, NAND_CMD_READ0, 12, page);
+ nand->read_buf(mtd, buffer, strlen(fingerprint));
+
+ /* Look for the fingerprint. */
+ if (!memcmp(buffer, fingerprint, strlen(fingerprint))) {
+ found_an_ncb_fingerprint = true;
+ break;
+ }
+
+ }
+
+ /* Deselect chip 0. */
+ nand->select_chip(mtd, saved_chip_number);
+
+ if (found_an_ncb_fingerprint)
+ pr_info(" Found a fingerprint\n");
+ else
+ pr_info(" No fingerprint found\n");
+ return found_an_ncb_fingerprint;
+}
+
+/* Writes a transcription stamp. */
+static int write_transcription_stamp(struct gpmi_nfc_data *this)
+{
+ struct device *dev = this->dev;
+ struct boot_rom_geometry *rom_geo = &this->rom_geometry;
+ struct nand_device_info *info = &this->device_info;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+ struct nand_chip *nand = &mil->nand;
+ unsigned int block_size_in_pages;
+ unsigned int search_area_size_in_strides;
+ unsigned int search_area_size_in_pages;
+ unsigned int search_area_size_in_blocks;
+ unsigned int block;
+ unsigned int stride;
+ unsigned int page;
+ loff_t byte;
+ uint8_t *buffer = nand->buffers->databuf;
+ int saved_chip_number;
+ int status;
+
+ /* Compute the search area geometry. */
+ block_size_in_pages = info->attr.block_size_in_pages;
+ search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent;
+ search_area_size_in_pages = search_area_size_in_strides *
+ rom_geo->stride_size_in_pages;
+ search_area_size_in_blocks =
+ (search_area_size_in_pages + (block_size_in_pages - 1)) /
+ block_size_in_pages;
+
+ pr_info("-------------------------------------------\n");
+ pr_info("Search Area Geometry\n");
+ pr_info("-------------------------------------------\n");
+ pr_info("Search Area Size in Blocks : %u", search_area_size_in_blocks);
+ pr_info("Search Area Size in Strides: %u", search_area_size_in_strides);
+ pr_info("Search Area Size in Pages : %u", search_area_size_in_pages);
+
+ /* Select chip 0. */
+ saved_chip_number = mil->current_chip;
+ nand->select_chip(mtd, 0);
+
+ /* Loop over blocks in the first search area, erasing them. */
+ pr_info("Erasing the search area...\n");
+
+ for (block = 0; block < search_area_size_in_blocks; block++) {
+ /* Compute the page address. */
+ page = block * block_size_in_pages;
+
+ /* Erase this block. */
+ pr_info(" Erasing block 0x%x\n", block);
+ nand->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+ nand->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
+
+ /* Wait for the erase to finish. */
+ status = nand->waitfunc(mtd, nand);
+ if (status & NAND_STATUS_FAIL)
+ dev_err(dev, "[%s] Erase failed.\n", __func__);
+ }
+
+ /* Write the NCB fingerprint into the page buffer. */
+ memset(buffer, ~0, mtd->writesize);
+ memset(nand->oob_poi, ~0, mtd->oobsize);
+ memcpy(buffer + 12, fingerprint, strlen(fingerprint));
+
+ /* Loop through the first search area, writing NCB fingerprints. */
+ pr_info("Writing NCB fingerprints...\n");
+ for (stride = 0; stride < search_area_size_in_strides; stride++) {
+ /* Compute the page and byte addresses. */
+ page = stride * rom_geo->stride_size_in_pages;
+ byte = page * mtd->writesize;
+
+ /* Write the first page of the current stride. */
+ pr_info(" Writing an NCB fingerprint in page 0x%x\n", page);
+ nand->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+ nand->ecc.write_page_raw(mtd, nand, buffer);
+ nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ /* Wait for the write to finish. */
+ status = nand->waitfunc(mtd, nand);
+ if (status & NAND_STATUS_FAIL)
+ dev_err(dev, "[%s] Write failed.\n", __func__);
+ }
+
+ /* Deselect chip 0. */
+ nand->select_chip(mtd, saved_chip_number);
+ return 0;
+}
+
+static int imx23_rom_extra_init(struct gpmi_nfc_data *this)
+{
+ struct device *dev = this->dev;
+ struct mil *mil = &this->mil;
+ struct nand_chip *nand = &mil->nand;
+ struct mtd_info *mtd = &mil->mtd;
+ struct nand_device_info *info = &this->device_info;
+ unsigned int block_count;
+ unsigned int block;
+ int chip;
+ int page;
+ loff_t byte;
+ uint8_t block_mark;
+ int error = 0;
+
+ /*
+ * If control arrives here, we can't use block mark swapping, which
+ * means we're forced to use transcription. First, scan for the
+ * transcription stamp. If we find it, then we don't have to do
+ * anything -- the block marks are already transcribed.
+ */
+ if (check_transcription_stamp(this))
+ return 0;
+
+ /*
+ * If control arrives here, we couldn't find a transcription stamp, so
+ * so we presume the block marks are in the conventional location.
+ */
+ pr_info("Transcribing bad block marks...\n");
+
+ /* Compute the number of blocks in the entire medium. */
+ block_count = info->attr.chip_size_in_bytes >> nand->phys_erase_shift;
+
+ /*
+ * Loop over all the blocks in the medium, transcribing block marks as
+ * we go.
+ */
+ for (block = 0; block < block_count; block++) {
+ /*
+ * Compute the chip, page and byte addresses for this block's
+ * conventional mark.
+ */
+ chip = block >> (nand->chip_shift - nand->phys_erase_shift);
+ page = block << (nand->phys_erase_shift - nand->page_shift);
+ byte = block << nand->phys_erase_shift;
+
+ /* Select the chip. */
+ nand->select_chip(mtd, chip);
+
+ /* Send the command to read the conventional block mark. */
+ nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
+
+ /* Read the conventional block mark. */
+ block_mark = nand->read_byte(mtd);
+
+ /*
+ * Check if the block is marked bad. If so, we need to mark it
+ * again, but this time the result will be a mark in the
+ * location where we transcribe block marks.
+ *
+ * Notice that we have to explicitly set the marking_a_bad_block
+ * member before we call through the block_markbad function
+ * pointer in the owning struct nand_chip. If we could call
+ * though the block_markbad function pointer in the owning
+ * struct mtd_info, which we have hooked, then this would be
+ * taken care of for us. Unfortunately, we can't because that
+ * higher-level code path will do things like consulting the
+ * in-memory bad block table -- which doesn't even exist yet!
+ * So, we have to call at a lower level and handle some details
+ * ourselves.
+ */
+ if (block_mark != 0xff) {
+ pr_info("Transcribing mark in block %u\n", block);
+ mil->marking_a_bad_block = true;
+ error = nand->block_markbad(mtd, byte);
+ mil->marking_a_bad_block = false;
+ if (error)
+ dev_err(dev, "Failed to mark block bad with "
+ "error %d\n", error);
+ }
+
+ /* Deselect the chip. */
+ nand->select_chip(mtd, -1);
+ }
+
+ /* Write the stamp that indicates we've transcribed the block marks. */
+ write_transcription_stamp(this);
+ return 0;
+}
+
+/* This structure represents the Boot ROM Helper for this version. */
+struct boot_rom_helper gpmi_nfc_boot_rom_imx23 = {
+ .version = 0,
+ .description = "Single/dual-chip boot area, "
+ "no block mark swapping",
+ .swap_block_mark = false,
+ .set_geometry = set_geometry,
+ .rom_extra_init = imx23_rom_extra_init,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/rom-mx28.c b/drivers/mtd/nand/gpmi-nfc/rom-mx28.c
new file mode 100644
index 0000000..03be07f
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/rom-mx28.c
@@ -0,0 +1,66 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+
+/* Sets geometry for the Boot ROM Helper. */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct boot_rom_geometry *geometry = &this->rom_geometry;
+ int error;
+
+ /* Version-independent geometry. */
+ error = gpmi_nfc_rom_helper_set_geometry(this);
+ if (error)
+ return error;
+
+ /*
+ * Check if the platform data indicates we are to protect the boot area.
+ */
+ if (!pdata->boot_area_size_in_bytes) {
+ geometry->boot_area_count = 0;
+ geometry->boot_area_size_in_bytes = 0;
+ return 0;
+ }
+
+ /*
+ * If control arrives here, we are supposed to set up partitions to
+ * protect the boot areas. In this version of the ROM, we support only
+ * one boot area.
+ */
+ geometry->boot_area_count = 1;
+
+ /*
+ * Use the platform's boot area size.
+ */
+ geometry->boot_area_size_in_bytes = pdata->boot_area_size_in_bytes;
+
+ return 0;
+}
+
+/* This structure represents the Boot ROM Helper for this version. */
+struct boot_rom_helper gpmi_nfc_boot_rom_imx28 = {
+ .version = 1,
+ .description = "Single-chip boot area, "
+ "block mark swapping supported",
+ .swap_block_mark = true,
+ .set_geometry = set_geometry,
+};
--
1.7.0.4
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH V3 6/6] MTD : add GPMI driver in the config and Makefile
2011-03-30 8:40 [PATCH V3 0/6] add the GPMI controller driver for IMX23/IMX28 Huang Shijie
` (4 preceding siblings ...)
2011-03-30 8:40 ` [PATCH V3 5/6] MTD: add support for imx23 and imx28 Huang Shijie
@ 2011-03-30 8:40 ` Huang Shijie
5 siblings, 0 replies; 31+ messages in thread
From: Huang Shijie @ 2011-03-30 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux, David.Woodhouse, dedekind1, Huang Shijie, linux-mtd,
ffainelli, shijie8
add the GPMI driver in the relevant Kconfig and Makefile in the MTD.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/nand/Kconfig | 10 ++++++++++
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/gpmi-nfc/Makefile | 6 ++++++
3 files changed, 17 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/gpmi-nfc/Makefile
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 450afc5..86effe8 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -426,6 +426,16 @@ config MTD_NAND_NANDSIM
The simulator may simulate various NAND flash chips for the
MTD nand layer.
+config MTD_NAND_GPMI_NFC
+ bool "GPMI NAND Flash Controller driver"
+ depends on MTD_NAND && (SOC_IMX23 || SOC_IMX28)
+ select MTD_PARTITIONS
+ help
+ Enables NAND Flash support for IMX23 or IMX28.
+ The GPMI controller is very powerful, with the help of BCH
+ module, it can do the hardware ECC. The GPMI supports several
+ NAND flashs at the same time.
+
config MTD_NAND_PLATFORM
tristate "Support for generic platform NAND driver"
help
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 8ad6fae..80d1f08 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -48,5 +48,6 @@ obj-$(CONFIG_MTD_NAND_BCM_UMI) += bcm_umi_nand.o nand_bcm_umi.o
obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
+obj-$(CONFIG_MTD_NAND_GPMI_NFC) += gpmi-nfc/
nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/gpmi-nfc/Makefile b/drivers/mtd/nand/gpmi-nfc/Makefile
new file mode 100644
index 0000000..8d91314
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/Makefile
@@ -0,0 +1,6 @@
+obj-$(CONFIG_MTD_NAND_GPMI_NFC) += gpmi-nfc.o
+gpmi-nfc-objs += gpmi-nfc-main.o
+gpmi-nfc-objs += hal-mx23-mx28.o
+gpmi-nfc-objs += rom-mx23.o
+gpmi-nfc-objs += rom-mx28.o
+gpmi-nfc-objs += ../nand_device_info.o
--
1.7.0.4
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH V3 3/6] MTD : add the database for the NANDs
2011-03-30 8:40 ` [PATCH V3 3/6] MTD : add the database for the NANDs Huang Shijie
@ 2011-03-30 8:46 ` Florian Fainelli
2011-03-30 9:05 ` Huang Shijie
0 siblings, 1 reply; 31+ messages in thread
From: Florian Fainelli @ 2011-03-30 8:46 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux, David.Woodhouse, dedekind1, Huang Shijie, linux-mtd, shijie8
Hello Huang,
On Wednesday 30 March 2011 10:40:10 Huang Shijie wrote:
> This is a new database for the NANDs which is searched by the id_bytes.
drivers/mtd//nand/nand_base.c will be able to detect all of your chips listed
below based on the ids present in drivers/mtd/nand/nand_ids.c
If you have new chips to support in the future, you should add them in
drivers/mtd/nand/nand_ids.c and not keep this file.
I still do not understand why this would be needed, is it because the generic
code does not provide enough informations for your driver?
>
> Signed-off-by: Huang Shijie <b32955@freescale.com>
> ---
> drivers/mtd/nand/nand_device_info.c | 157
> +++++++++++++++++++++++++++++++++++ drivers/mtd/nand/nand_device_info.h |
> 88 +++++++++++++++++++
> 2 files changed, 245 insertions(+), 0 deletions(-)
> create mode 100644 drivers/mtd/nand/nand_device_info.c
> create mode 100644 drivers/mtd/nand/nand_device_info.h
>
> diff --git a/drivers/mtd/nand/nand_device_info.c
> b/drivers/mtd/nand/nand_device_info.c new file mode 100644
> index 0000000..757ed89
> --- /dev/null
> +++ b/drivers/mtd/nand/nand_device_info.c
> @@ -0,0 +1,157 @@
> +/*
> + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +#include <asm/sizes.h>
> +#include <linux/mtd/nand.h>
> +
> +#include "nand_device_info.h"
> +
> +static const struct nand_device_info samsung_nand[] = {
> + {
> + .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
> + .id_len = 8,
> + .desc = "K9G8G08U0M, K9HAG08U1M",
> + .attr = ATTR(MLC, NAND_BUSWIDTH_8, 1LL * SZ_1G, 128,
> + 2 * SZ_1K + 64, 8, 512),
> + }, {
> + .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
> + .id_len = 8,
> + .desc = "K9LBG08U0D",
> + .attr = ATTR(MLC, NAND_BUSWIDTH_8, 4LL * SZ_1G, 128,
> + 4 * SZ_1K + 218, 16, 512),
> + }, {
> + .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
> + .id_len = 8,
> + .desc = "K9GAG08U0M",
> + .attr = ATTR(MLC, NAND_BUSWIDTH_8, 2LL * SZ_1G, 128,
> + 4 * SZ_1K + 218, 16, 512),
> + }, {
> + /* end of the table. */
> + .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
> + },
> +};
> +
> +/* macro to get the id bytes */
> +#define ID_GET_MFR_CODE(id) ((id)[0])
> +
> +void nand_device_print_info(struct nand_device_info *info)
> +{
> + unsigned i;
> + const char *mfr_name;
> + const char *cell_technology_name;
> + uint64_t chip_size;
> + const char *chip_size_units;
> + unsigned page_size;
> + unsigned oob_size;
> + struct nand_attr *attr = &info->attr;
> +
> + /* Prepare the manufacturer name. */
> + mfr_name = "Unknown";
> + for (i = 0; nand_manuf_ids[i].id; i++) {
> + if (nand_manuf_ids[i].id == ID_GET_MFR_CODE(info->id)) {
> + mfr_name = nand_manuf_ids[i].name;
> + break;
> + }
> + }
> +
> + /* Prepare the name of the cell technology. */
> + switch (attr->cell_technology) {
> + case SLC:
> + cell_technology_name = "SLC";
> + break;
> + case MLC:
> + cell_technology_name = "MLC";
> + break;
> + default:
> + cell_technology_name = "Unknown";
> + break;
> + }
> +
> + /* Prepare the chip size. */
> + if ((attr->chip_size_in_bytes >= SZ_1G) &&
> + !(attr->chip_size_in_bytes % SZ_1G)) {
> + chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1G);
> + chip_size_units = "GiB";
> + } else if ((attr->chip_size_in_bytes >= SZ_1M) &&
> + !(attr->chip_size_in_bytes % SZ_1M)) {
> + chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1M);
> + chip_size_units = "MiB";
> + } else {
> + chip_size = attr->chip_size_in_bytes;
> + chip_size_units = "B";
> + }
> +
> + /* Prepare the page geometry. */
> + page_size = (1 << (fls(attr->page_total_size_in_bytes) - 1));
> + oob_size = attr->page_total_size_in_bytes - page_size;
> +
> + /* Print the infomation. */
> + pr_info("--------------------------------------\n");
> + pr_info(" NAND device infomation (RAW)\n");
> + pr_info("--------------------------------------\n");
> + pr_info("Manufacturer : %s (0x%02x)\n", mfr_name, info->id[0]);
> + pr_info("Device Code : 0x%02x\n", info->id[1]);
> + pr_info("Cell Technology : %s\n", cell_technology_name);
> + pr_info("Chip Size : %llu %s\n", chip_size, chip_size_units);
> + pr_info("Pages per Block : %u\n", attr->block_size_in_pages);
> + pr_info("Page Geometry : %u+%u\n", page_size, oob_size);
> + pr_info("ECC Strength : %u bits\n", attr->ecc_strength_in_bits);
> + pr_info("ECC Size : %u B\n", attr->ecc_size_in_bytes);
> + pr_info("Description : %s\n", info->desc);
> +}
> +
> +static struct nand_device_info * __init
> +search_table(const struct nand_device_info *table, const uint8_t id[])
> +{
> + struct nand_device_info *info = (struct nand_device_info *)table;
> +
> + while (ID_GET_MFR_CODE(info->id)) {
> + int i;
> +
> + /* match all the valid id bytes. Is it too strict? */
> + for (i = 0; i < info->id_len; i++)
> + if (info->id[i] != id[i])
> + break;
> +
> + /* found it */
> + if (i == info->id_len)
> + return info;
> + info++;
> + }
> + return NULL;
> +}
> +
> +struct nand_device_mfr_info {
> + uint8_t id;
> + const struct nand_device_info *table;
> +};
> +
> +static const struct nand_device_mfr_info nand_device_mfr_directory[] = {
> + { NAND_MFR_SAMSUNG, samsung_nand },
> + { 0, NULL },
> +};
> +
> +struct nand_device_info *nand_device_get_info(const uint8_t id[])
> +{
> + uint8_t mfr_id = ID_GET_MFR_CODE(id);
> + unsigned i;
> +
> + for (i = 0; nand_device_mfr_directory[i].id; i++) {
> + if (nand_device_mfr_directory[i].id == mfr_id) {
> + const struct nand_device_info *table;
> +
> + table = nand_device_mfr_directory[i].table;
> + return search_table(table, id);
> + }
> + }
> + return NULL;
> +}
> diff --git a/drivers/mtd/nand/nand_device_info.h
> b/drivers/mtd/nand/nand_device_info.h new file mode 100644
> index 0000000..15f688d
> --- /dev/null
> +++ b/drivers/mtd/nand/nand_device_info.h
> @@ -0,0 +1,88 @@
> +/*
> + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +#ifndef __DRIVERS_NAND_DEVICE_INFO_H
> +#define __DRIVERS_NAND_DEVICE_INFO_H
> +
> +enum nand_device_cell_technology {
> + SLC = 0,
> + MLC = 1,
> +};
> +
> +/**
> + * @cell_technology: The storage cell technology.
> + * @busw: The bus width of the NAND.
> + * @chip_size_in_bytes: The total size of the storage behind a single
> + * chip select, in bytes. Notice that this is *not*
> + * necessarily the total size of the storage in a
> + * *package*, which may contain several chips.
> + * @block_size_in_pages: The number of pages in a block.
> + * @page_total_size_in_bytes: The total size of a page, in bytes,
> including + * both the data and the OOB.
> + * @ecc_strength_in_bits: The strength of the ECC called for by the
> + * manufacturer, in number of correctable bits.
> + * @ecc_size_in_bytes: The size of the data block over which the
> + * manufacturer calls for the given ECC algorithm
> + * and strength.
> + */
> +struct nand_attr {
> + /* Technology */
> + enum nand_device_cell_technology cell_technology;
> +
> + /* bus width */
> +#define NAND_BUSWIDTH_8 0
> + uint32_t busw;
> +
> + /* Geometry */
> + uint64_t chip_size_in_bytes;
> + uint32_t block_size_in_pages;
> + uint32_t page_total_size_in_bytes;
> +
> + /* ECC */
> + uint16_t ecc_strength_in_bits;
> + uint16_t ecc_size_in_bytes;
> +};
> +
> +#define ID_BYTES (8)
> +/*
> + * struct nand_device_info - Information about a single NAND Flash device.
> + *
> + * This structure contains all the *essential* information about a NAND
> Flash + * device, derived from the device's data sheet.
> + */
> +struct nand_device_info {
> + /* id */
> + uint8_t id[ID_BYTES];
> + unsigned int id_len;
> +
> + /* Description */
> + const char *desc;
> +
> + /* attribute*/
> + struct nand_attr attr;
> +};
> +
> +/* macro for the NAND attribute */
> +#define ATTR(_a, _b, _c, _d, _e, _f, _g) \
> + { \
> + .cell_technology = (_a), \
> + .busw = (_b), \
> + .chip_size_in_bytes = (_c), \
> + .block_size_in_pages = (_d), \
> + .page_total_size_in_bytes = (_e), \
> + .ecc_strength_in_bits = (_f), \
> + .ecc_size_in_bytes = (_g), \
> + }
> +
> +struct nand_device_info *nand_device_get_info(const uint8_t id_bytes[]);
> +void nand_device_print_info(struct nand_device_info *info);
> +#endif
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 2/6] dmaengine: change the flags of request_irq()
2011-03-30 8:40 ` [PATCH V3 2/6] dmaengine: change the flags of request_irq() Huang Shijie
@ 2011-03-30 9:03 ` Lothar Waßmann
2011-03-30 9:13 ` Shawn Guo
0 siblings, 1 reply; 31+ messages in thread
From: Lothar Waßmann @ 2011-03-30 9:03 UTC (permalink / raw)
To: Huang Shijie
Cc: linux, David.Woodhouse, dedekind1, linux-mtd, ffainelli, shijie8,
linux-arm-kernel
Hi,
Huang Shijie writes:
> The GPMI may have many DMA channels, such as the imx23 has
> four DMA channels. All these DMA channels share the same interrupt.
> So change the flags from '0' to IRQF_SHARED, else there will be
> an EBUSY error returns.
>
> Signed-off-by: Huang Shijie <b32955@freescale.com>
> ---
> drivers/dma/mxs-dma.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
> index 88aad4f..0ee5b52 100644
> --- a/drivers/dma/mxs-dma.c
> +++ b/drivers/dma/mxs-dma.c
> @@ -328,7 +328,7 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
> memset(mxs_chan->ccw, 0, PAGE_SIZE);
>
> ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
> - 0, "mxs-dma", mxs_dma);
> + IRQF_SHARED, "mxs-dma", mxs_dma);
> if (ret)
> goto err_irq;
>
IMO this is wrong. The interrupt is requested with all the same
parameters for each DMA channel. So, actually it is not a shared IRQ,
but an IRQ with the same handler registered multiple times, which is
just nonsense.
Instead of declaring it as shared, it would be more sensible to only
register it for the first channel. Otherwise the handler will be
called multiple times in case of an interrupt with only the first
invocation doing all the work and the subsequent invocations just
returning without doing anything.
Lothar Waßmann
--
___________________________________________________________
Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Geschäftsführer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996
www.karo-electronics.de | info@karo-electronics.de
___________________________________________________________
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 3/6] MTD : add the database for the NANDs
2011-03-30 8:46 ` Florian Fainelli
@ 2011-03-30 9:05 ` Huang Shijie
2011-03-30 9:23 ` Florian Fainelli
2011-03-31 10:10 ` Artem Bityutskiy
0 siblings, 2 replies; 31+ messages in thread
From: Huang Shijie @ 2011-03-30 9:05 UTC (permalink / raw)
To: Florian Fainelli
Cc: linux, David.Woodhouse, dedekind1, linux-mtd, shijie8, linux-arm-kernel
Hi Florian:
thanks for a so quick reply. :)
> Hello Huang,
>
> On Wednesday 30 March 2011 10:40:10 Huang Shijie wrote:
>> This is a new database for the NANDs which is searched by the id_bytes.
> drivers/mtd//nand/nand_base.c will be able to detect all of your chips listed
> below based on the ids present in drivers/mtd/nand/nand_ids.c
>
yes.
But I will use the new database to replace the old one.
I will submit new patches to modify the generic code if my driver is
accepted.
> If you have new chips to support in the future, you should add them in
> drivers/mtd/nand/nand_ids.c and not keep this file.
>
The data structure nand_flash_dev{} does not contain enough information.
So I want to the nand_device_info{} to replace it in future.
> I still do not understand why this would be needed, is it because the generic
> code does not provide enough informations for your driver?
>
yes.
IMHO, the generic code is somehow trapped in a wrong way. :(
Paring the id bytes is not sufficient to get all the information you
need which is faced by me.
What's more, I think the paring code is ugly, see the nand_get_flash_type().
Why not create a new database which contains all the necessary
information for a nand, and can be easy
find by the id bytes as the keyword?
I wish David and Artem give some advice about this.
>> Signed-off-by: Huang Shijie<b32955@freescale.com>
>> ---
>> drivers/mtd/nand/nand_device_info.c | 157
>> +++++++++++++++++++++++++++++++++++ drivers/mtd/nand/nand_device_info.h |
>> 88 +++++++++++++++++++
>> 2 files changed, 245 insertions(+), 0 deletions(-)
>> create mode 100644 drivers/mtd/nand/nand_device_info.c
>> create mode 100644 drivers/mtd/nand/nand_device_info.h
>>
>> diff --git a/drivers/mtd/nand/nand_device_info.c
>> b/drivers/mtd/nand/nand_device_info.c new file mode 100644
>> index 0000000..757ed89
>> --- /dev/null
>> +++ b/drivers/mtd/nand/nand_device_info.c
>> @@ -0,0 +1,157 @@
>> +/*
>> + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
>> + */
>> +
>> +/*
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +#include<asm/sizes.h>
>> +#include<linux/mtd/nand.h>
>> +
>> +#include "nand_device_info.h"
>> +
>> +static const struct nand_device_info samsung_nand[] = {
>> + {
>> + .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
>> + .id_len = 8,
>> + .desc = "K9G8G08U0M, K9HAG08U1M",
>> + .attr = ATTR(MLC, NAND_BUSWIDTH_8, 1LL * SZ_1G, 128,
>> + 2 * SZ_1K + 64, 8, 512),
>> + }, {
>> + .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
>> + .id_len = 8,
>> + .desc = "K9LBG08U0D",
>> + .attr = ATTR(MLC, NAND_BUSWIDTH_8, 4LL * SZ_1G, 128,
>> + 4 * SZ_1K + 218, 16, 512),
>> + }, {
>> + .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
>> + .id_len = 8,
>> + .desc = "K9GAG08U0M",
>> + .attr = ATTR(MLC, NAND_BUSWIDTH_8, 2LL * SZ_1G, 128,
>> + 4 * SZ_1K + 218, 16, 512),
>> + }, {
>> + /* end of the table. */
>> + .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
>> + },
>> +};
>> +
>> +/* macro to get the id bytes */
>> +#define ID_GET_MFR_CODE(id) ((id)[0])
>> +
>> +void nand_device_print_info(struct nand_device_info *info)
>> +{
>> + unsigned i;
>> + const char *mfr_name;
>> + const char *cell_technology_name;
>> + uint64_t chip_size;
>> + const char *chip_size_units;
>> + unsigned page_size;
>> + unsigned oob_size;
>> + struct nand_attr *attr =&info->attr;
>> +
>> + /* Prepare the manufacturer name. */
>> + mfr_name = "Unknown";
>> + for (i = 0; nand_manuf_ids[i].id; i++) {
>> + if (nand_manuf_ids[i].id == ID_GET_MFR_CODE(info->id)) {
>> + mfr_name = nand_manuf_ids[i].name;
>> + break;
>> + }
>> + }
>> +
>> + /* Prepare the name of the cell technology. */
>> + switch (attr->cell_technology) {
>> + case SLC:
>> + cell_technology_name = "SLC";
>> + break;
>> + case MLC:
>> + cell_technology_name = "MLC";
>> + break;
>> + default:
>> + cell_technology_name = "Unknown";
>> + break;
>> + }
>> +
>> + /* Prepare the chip size. */
>> + if ((attr->chip_size_in_bytes>= SZ_1G)&&
>> + !(attr->chip_size_in_bytes % SZ_1G)) {
>> + chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1G);
>> + chip_size_units = "GiB";
>> + } else if ((attr->chip_size_in_bytes>= SZ_1M)&&
>> + !(attr->chip_size_in_bytes % SZ_1M)) {
>> + chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1M);
>> + chip_size_units = "MiB";
>> + } else {
>> + chip_size = attr->chip_size_in_bytes;
>> + chip_size_units = "B";
>> + }
>> +
>> + /* Prepare the page geometry. */
>> + page_size = (1<< (fls(attr->page_total_size_in_bytes) - 1));
>> + oob_size = attr->page_total_size_in_bytes - page_size;
>> +
>> + /* Print the infomation. */
>> + pr_info("--------------------------------------\n");
>> + pr_info(" NAND device infomation (RAW)\n");
>> + pr_info("--------------------------------------\n");
>> + pr_info("Manufacturer : %s (0x%02x)\n", mfr_name, info->id[0]);
>> + pr_info("Device Code : 0x%02x\n", info->id[1]);
>> + pr_info("Cell Technology : %s\n", cell_technology_name);
>> + pr_info("Chip Size : %llu %s\n", chip_size, chip_size_units);
>> + pr_info("Pages per Block : %u\n", attr->block_size_in_pages);
>> + pr_info("Page Geometry : %u+%u\n", page_size, oob_size);
>> + pr_info("ECC Strength : %u bits\n", attr->ecc_strength_in_bits);
>> + pr_info("ECC Size : %u B\n", attr->ecc_size_in_bytes);
>> + pr_info("Description : %s\n", info->desc);
>> +}
>> +
>> +static struct nand_device_info * __init
>> +search_table(const struct nand_device_info *table, const uint8_t id[])
>> +{
>> + struct nand_device_info *info = (struct nand_device_info *)table;
>> +
>> + while (ID_GET_MFR_CODE(info->id)) {
>> + int i;
>> +
>> + /* match all the valid id bytes. Is it too strict? */
>> + for (i = 0; i< info->id_len; i++)
>> + if (info->id[i] != id[i])
>> + break;
>> +
>> + /* found it */
>> + if (i == info->id_len)
>> + return info;
>> + info++;
>> + }
>> + return NULL;
>> +}
>> +
>> +struct nand_device_mfr_info {
>> + uint8_t id;
>> + const struct nand_device_info *table;
>> +};
>> +
>> +static const struct nand_device_mfr_info nand_device_mfr_directory[] = {
>> + { NAND_MFR_SAMSUNG, samsung_nand },
>> + { 0, NULL },
>> +};
>> +
>> +struct nand_device_info *nand_device_get_info(const uint8_t id[])
>> +{
>> + uint8_t mfr_id = ID_GET_MFR_CODE(id);
>> + unsigned i;
>> +
>> + for (i = 0; nand_device_mfr_directory[i].id; i++) {
>> + if (nand_device_mfr_directory[i].id == mfr_id) {
>> + const struct nand_device_info *table;
>> +
>> + table = nand_device_mfr_directory[i].table;
>> + return search_table(table, id);
>> + }
>> + }
>> + return NULL;
>> +}
>> diff --git a/drivers/mtd/nand/nand_device_info.h
>> b/drivers/mtd/nand/nand_device_info.h new file mode 100644
>> index 0000000..15f688d
>> --- /dev/null
>> +++ b/drivers/mtd/nand/nand_device_info.h
>> @@ -0,0 +1,88 @@
>> +/*
>> + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
>> + */
>> +
>> +/*
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +#ifndef __DRIVERS_NAND_DEVICE_INFO_H
>> +#define __DRIVERS_NAND_DEVICE_INFO_H
>> +
>> +enum nand_device_cell_technology {
>> + SLC = 0,
>> + MLC = 1,
>> +};
>> +
>> +/**
>> + * @cell_technology: The storage cell technology.
>> + * @busw: The bus width of the NAND.
>> + * @chip_size_in_bytes: The total size of the storage behind a single
>> + * chip select, in bytes. Notice that this is *not*
>> + * necessarily the total size of the storage in a
>> + * *package*, which may contain several chips.
>> + * @block_size_in_pages: The number of pages in a block.
>> + * @page_total_size_in_bytes: The total size of a page, in bytes,
>> including + * both the data and the OOB.
>> + * @ecc_strength_in_bits: The strength of the ECC called for by the
>> + * manufacturer, in number of correctable bits.
>> + * @ecc_size_in_bytes: The size of the data block over which the
>> + * manufacturer calls for the given ECC algorithm
>> + * and strength.
>> + */
>> +struct nand_attr {
>> + /* Technology */
>> + enum nand_device_cell_technology cell_technology;
>> +
>> + /* bus width */
>> +#define NAND_BUSWIDTH_8 0
>> + uint32_t busw;
>> +
>> + /* Geometry */
>> + uint64_t chip_size_in_bytes;
>> + uint32_t block_size_in_pages;
>> + uint32_t page_total_size_in_bytes;
>> +
>> + /* ECC */
>> + uint16_t ecc_strength_in_bits;
>> + uint16_t ecc_size_in_bytes;
>> +};
>> +
>> +#define ID_BYTES (8)
>> +/*
>> + * struct nand_device_info - Information about a single NAND Flash device.
>> + *
>> + * This structure contains all the *essential* information about a NAND
>> Flash + * device, derived from the device's data sheet.
>> + */
>> +struct nand_device_info {
>> + /* id */
>> + uint8_t id[ID_BYTES];
>> + unsigned int id_len;
>> +
>> + /* Description */
>> + const char *desc;
>> +
>> + /* attribute*/
>> + struct nand_attr attr;
>> +};
>> +
>> +/* macro for the NAND attribute */
>> +#define ATTR(_a, _b, _c, _d, _e, _f, _g) \
>> + { \
>> + .cell_technology = (_a), \
>> + .busw = (_b), \
>> + .chip_size_in_bytes = (_c), \
>> + .block_size_in_pages = (_d), \
>> + .page_total_size_in_bytes = (_e), \
>> + .ecc_strength_in_bits = (_f), \
>> + .ecc_size_in_bytes = (_g), \
>> + }
>> +
>> +struct nand_device_info *nand_device_get_info(const uint8_t id_bytes[]);
>> +void nand_device_print_info(struct nand_device_info *info);
>> +#endif
Best Regards
Huang Shijie
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 2/6] dmaengine: change the flags of request_irq()
2011-03-30 9:03 ` Lothar Waßmann
@ 2011-03-30 9:13 ` Shawn Guo
2011-03-30 9:15 ` Lothar Waßmann
0 siblings, 1 reply; 31+ messages in thread
From: Shawn Guo @ 2011-03-30 9:13 UTC (permalink / raw)
To: Lothar Waßmann
Cc: linux, David.Woodhouse, dedekind1, Huang Shijie, linux-mtd,
ffainelli, shijie8, linux-arm-kernel
On Wed, Mar 30, 2011 at 11:03:02AM +0200, Lothar Waßmann wrote:
> Hi,
>
> Huang Shijie writes:
> > The GPMI may have many DMA channels, such as the imx23 has
> > four DMA channels. All these DMA channels share the same interrupt.
> > So change the flags from '0' to IRQF_SHARED, else there will be
> > an EBUSY error returns.
> >
> > Signed-off-by: Huang Shijie <b32955@freescale.com>
> > ---
> > drivers/dma/mxs-dma.c | 2 +-
> > 1 files changed, 1 insertions(+), 1 deletions(-)
> >
> > diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
> > index 88aad4f..0ee5b52 100644
> > --- a/drivers/dma/mxs-dma.c
> > +++ b/drivers/dma/mxs-dma.c
> > @@ -328,7 +328,7 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
> > memset(mxs_chan->ccw, 0, PAGE_SIZE);
> >
> > ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
> > - 0, "mxs-dma", mxs_dma);
> > + IRQF_SHARED, "mxs-dma", mxs_dma);
> > if (ret)
> > goto err_irq;
> >
> IMO this is wrong. The interrupt is requested with all the same
> parameters for each DMA channel. So, actually it is not a shared IRQ,
The parameter mxs_chan->chan_irq is different for each channel, except
gpmi which has 4 channels sharing one irq.
> but an IRQ with the same handler registered multiple times, which is
> just nonsense.
>
> Instead of declaring it as shared, it would be more sensible to only
> register it for the first channel. Otherwise the handler will be
> called multiple times in case of an interrupt with only the first
> invocation doing all the work and the subsequent invocations just
> returning without doing anything.
>
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 2/6] dmaengine: change the flags of request_irq()
2011-03-30 9:13 ` Shawn Guo
@ 2011-03-30 9:15 ` Lothar Waßmann
2011-03-30 9:44 ` Huang Shijie
2011-03-31 7:02 ` [PATCH V3 2/6] dmaengine: add interrupt check for GPMI controller Huang Shijie
0 siblings, 2 replies; 31+ messages in thread
From: Lothar Waßmann @ 2011-03-30 9:15 UTC (permalink / raw)
To: Shawn Guo
Cc: linux, David.Woodhouse, dedekind1, Huang Shijie, linux-mtd,
ffainelli, shijie8, linux-arm-kernel
Shawn Guo writes:
> On Wed, Mar 30, 2011 at 11:03:02AM +0200, Lothar Waßmann wrote:
> > Hi,
> >
> > Huang Shijie writes:
> > > The GPMI may have many DMA channels, such as the imx23 has
> > > four DMA channels. All these DMA channels share the same interrupt.
> > > So change the flags from '0' to IRQF_SHARED, else there will be
> > > an EBUSY error returns.
> > >
> > > Signed-off-by: Huang Shijie <b32955@freescale.com>
> > > ---
> > > drivers/dma/mxs-dma.c | 2 +-
> > > 1 files changed, 1 insertions(+), 1 deletions(-)
> > >
> > > diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
> > > index 88aad4f..0ee5b52 100644
> > > --- a/drivers/dma/mxs-dma.c
> > > +++ b/drivers/dma/mxs-dma.c
> > > @@ -328,7 +328,7 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
> > > memset(mxs_chan->ccw, 0, PAGE_SIZE);
> > >
> > > ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
> > > - 0, "mxs-dma", mxs_dma);
> > > + IRQF_SHARED, "mxs-dma", mxs_dma);
> > > if (ret)
> > > goto err_irq;
> > >
> > IMO this is wrong. The interrupt is requested with all the same
> > parameters for each DMA channel. So, actually it is not a shared IRQ,
>
> The parameter mxs_chan->chan_irq is different for each channel, except
> gpmi which has 4 channels sharing one irq.
>
That's what I mean. The other interrupts won't need the IRQF_SHARED
flag anyway.
> > but an IRQ with the same handler registered multiple times, which is
> > just nonsense.
> >
> > Instead of declaring it as shared, it would be more sensible to only
> > register it for the first channel. Otherwise the handler will be
> > called multiple times in case of an interrupt with only the first
> > invocation doing all the work and the subsequent invocations just
> > returning without doing anything.
> >
>
> --
> Regards,
> Shawn
>
Lothar Waßmann
--
___________________________________________________________
Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Geschäftsführer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996
www.karo-electronics.de | info@karo-electronics.de
___________________________________________________________
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 3/6] MTD : add the database for the NANDs
2011-03-30 9:05 ` Huang Shijie
@ 2011-03-30 9:23 ` Florian Fainelli
2011-03-30 9:54 ` Huang Shijie
2011-03-31 10:10 ` Artem Bityutskiy
1 sibling, 1 reply; 31+ messages in thread
From: Florian Fainelli @ 2011-03-30 9:23 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux, David.Woodhouse, dedekind1, Huang Shijie, linux-mtd, shijie8
Hello Huang,
On Wednesday 30 March 2011 11:05:59 Huang Shijie wrote:
> Hi Florian:
>
> thanks for a so quick reply. :)
>
> > Hello Huang,
> >
> > On Wednesday 30 March 2011 10:40:10 Huang Shijie wrote:
> >> This is a new database for the NANDs which is searched by the id_bytes.
> >
> > drivers/mtd//nand/nand_base.c will be able to detect all of your chips
> > listed below based on the ids present in drivers/mtd/nand/nand_ids.c
>
> yes.
>
> But I will use the new database to replace the old one.
>
> I will submit new patches to modify the generic code if my driver is
> accepted.
I think you can start right away submitting patches to modify generic code,
this can either be a premilinary patch series to the GPMI driver, or in the
same patch series as the GPMI driver.
>
> > If you have new chips to support in the future, you should add them in
> > drivers/mtd/nand/nand_ids.c and not keep this file.
>
> The data structure nand_flash_dev{} does not contain enough information.
> So I want to the nand_device_info{} to replace it in future.
Ok, you should have written that in the patch description, otherwise it is
misleading and I though you just duplicated code without knowing what the
existing code could do.
>
> > I still do not understand why this would be needed, is it because the
> > generic code does not provide enough informations for your driver?
>
> yes.
>
> IMHO, the generic code is somehow trapped in a wrong way. :(
> Paring the id bytes is not sufficient to get all the information you
> need which is faced by me.
>
> What's more, I think the paring code is ugly, see the
> nand_get_flash_type().
>
> Why not create a new database which contains all the necessary
> information for a nand, and can be easy
> find by the id bytes as the keyword?
The idea is to hardcode as little information as possible, and let the rest be
detected at runtime when possible. I think this it the right approach, because
it is more future proof.
>
> I wish David and Artem give some advice about this.
I would also like them to jump into this discussion.
>
> >> Signed-off-by: Huang Shijie<b32955@freescale.com>
> >> ---
> >>
> >> drivers/mtd/nand/nand_device_info.c | 157
> >>
> >> +++++++++++++++++++++++++++++++++++ drivers/mtd/nand/nand_device_info.h
> >> |
> >>
> >> 88 +++++++++++++++++++
> >> 2 files changed, 245 insertions(+), 0 deletions(-)
> >> create mode 100644 drivers/mtd/nand/nand_device_info.c
> >> create mode 100644 drivers/mtd/nand/nand_device_info.h
> >>
> >> diff --git a/drivers/mtd/nand/nand_device_info.c
> >> b/drivers/mtd/nand/nand_device_info.c new file mode 100644
> >> index 0000000..757ed89
> >> --- /dev/null
> >> +++ b/drivers/mtd/nand/nand_device_info.c
> >> @@ -0,0 +1,157 @@
> >> +/*
> >> + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights
> >> Reserved. + */
> >> +
> >> +/*
> >> + * The code contained herein is licensed under the GNU General Public
> >> + * License. You may obtain a copy of the GNU General Public License
> >> + * Version 2 or later at the following locations:
> >> + *
> >> + * http://www.opensource.org/licenses/gpl-license.html
> >> + * http://www.gnu.org/copyleft/gpl.html
> >> + */
> >> +#include<asm/sizes.h>
> >> +#include<linux/mtd/nand.h>
> >> +
> >> +#include "nand_device_info.h"
> >> +
> >> +static const struct nand_device_info samsung_nand[] = {
> >> + {
> >> + .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
> >> + .id_len = 8,
> >> + .desc = "K9G8G08U0M, K9HAG08U1M",
> >> + .attr = ATTR(MLC, NAND_BUSWIDTH_8, 1LL * SZ_1G, 128,
> >> + 2 * SZ_1K + 64, 8, 512),
> >> + }, {
> >> + .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
> >> + .id_len = 8,
> >> + .desc = "K9LBG08U0D",
> >> + .attr = ATTR(MLC, NAND_BUSWIDTH_8, 4LL * SZ_1G, 128,
> >> + 4 * SZ_1K + 218, 16, 512),
> >> + }, {
> >> + .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
> >> + .id_len = 8,
> >> + .desc = "K9GAG08U0M",
> >> + .attr = ATTR(MLC, NAND_BUSWIDTH_8, 2LL * SZ_1G, 128,
> >> + 4 * SZ_1K + 218, 16, 512),
> >> + }, {
> >> + /* end of the table. */
> >> + .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
> >> + },
> >> +};
> >> +
> >> +/* macro to get the id bytes */
> >> +#define ID_GET_MFR_CODE(id) ((id)[0])
> >> +
> >> +void nand_device_print_info(struct nand_device_info *info)
> >> +{
> >> + unsigned i;
> >> + const char *mfr_name;
> >> + const char *cell_technology_name;
> >> + uint64_t chip_size;
> >> + const char *chip_size_units;
> >> + unsigned page_size;
> >> + unsigned oob_size;
> >> + struct nand_attr *attr =&info->attr;
> >> +
> >> + /* Prepare the manufacturer name. */
> >> + mfr_name = "Unknown";
> >> + for (i = 0; nand_manuf_ids[i].id; i++) {
> >> + if (nand_manuf_ids[i].id == ID_GET_MFR_CODE(info->id)) {
> >> + mfr_name = nand_manuf_ids[i].name;
> >> + break;
> >> + }
> >> + }
> >> +
> >> + /* Prepare the name of the cell technology. */
> >> + switch (attr->cell_technology) {
> >> + case SLC:
> >> + cell_technology_name = "SLC";
> >> + break;
> >> + case MLC:
> >> + cell_technology_name = "MLC";
> >> + break;
> >> + default:
> >> + cell_technology_name = "Unknown";
> >> + break;
> >> + }
> >> +
> >> + /* Prepare the chip size. */
> >> + if ((attr->chip_size_in_bytes>= SZ_1G)&&
> >> + !(attr->chip_size_in_bytes % SZ_1G)) {
> >> + chip_size = attr->chip_size_in_bytes / ((uint64_t)
SZ_1G);
> >> + chip_size_units = "GiB";
> >> + } else if ((attr->chip_size_in_bytes>= SZ_1M)&&
> >> + !(attr->chip_size_in_bytes % SZ_1M)) {
> >> + chip_size = attr->chip_size_in_bytes / ((uint64_t)
SZ_1M);
> >> + chip_size_units = "MiB";
> >> + } else {
> >> + chip_size = attr->chip_size_in_bytes;
> >> + chip_size_units = "B";
> >> + }
> >> +
> >> + /* Prepare the page geometry. */
> >> + page_size = (1<< (fls(attr->page_total_size_in_bytes) - 1));
> >> + oob_size = attr->page_total_size_in_bytes - page_size;
> >> +
> >> + /* Print the infomation. */
> >> + pr_info("--------------------------------------\n");
> >> + pr_info(" NAND device infomation (RAW)\n");
> >> + pr_info("--------------------------------------\n");
> >> + pr_info("Manufacturer : %s (0x%02x)\n", mfr_name, info->id[0]);
> >> + pr_info("Device Code : 0x%02x\n", info->id[1]);
> >> + pr_info("Cell Technology : %s\n", cell_technology_name);
> >> + pr_info("Chip Size : %llu %s\n", chip_size,
chip_size_units);
> >> + pr_info("Pages per Block : %u\n", attr->block_size_in_pages);
> >> + pr_info("Page Geometry : %u+%u\n", page_size, oob_size);
> >> + pr_info("ECC Strength : %u bits\n", attr-
>ecc_strength_in_bits);
> >> + pr_info("ECC Size : %u B\n", attr->ecc_size_in_bytes);
> >> + pr_info("Description : %s\n", info->desc);
> >> +}
> >> +
> >> +static struct nand_device_info * __init
> >> +search_table(const struct nand_device_info *table, const uint8_t id[])
> >> +{
> >> + struct nand_device_info *info = (struct nand_device_info *)table;
> >> +
> >> + while (ID_GET_MFR_CODE(info->id)) {
> >> + int i;
> >> +
> >> + /* match all the valid id bytes. Is it too strict? */
> >> + for (i = 0; i< info->id_len; i++)
> >> + if (info->id[i] != id[i])
> >> + break;
> >> +
> >> + /* found it */
> >> + if (i == info->id_len)
> >> + return info;
> >> + info++;
> >> + }
> >> + return NULL;
> >> +}
> >> +
> >> +struct nand_device_mfr_info {
> >> + uint8_t id;
> >> + const struct nand_device_info *table;
> >> +};
> >> +
> >> +static const struct nand_device_mfr_info nand_device_mfr_directory[] =
> >> { + { NAND_MFR_SAMSUNG, samsung_nand },
> >> + { 0, NULL },
> >> +};
> >> +
> >> +struct nand_device_info *nand_device_get_info(const uint8_t id[])
> >> +{
> >> + uint8_t mfr_id = ID_GET_MFR_CODE(id);
> >> + unsigned i;
> >> +
> >> + for (i = 0; nand_device_mfr_directory[i].id; i++) {
> >> + if (nand_device_mfr_directory[i].id == mfr_id) {
> >> + const struct nand_device_info *table;
> >> +
> >> + table = nand_device_mfr_directory[i].table;
> >> + return search_table(table, id);
> >> + }
> >> + }
> >> + return NULL;
> >> +}
> >> diff --git a/drivers/mtd/nand/nand_device_info.h
> >> b/drivers/mtd/nand/nand_device_info.h new file mode 100644
> >> index 0000000..15f688d
> >> --- /dev/null
> >> +++ b/drivers/mtd/nand/nand_device_info.h
> >> @@ -0,0 +1,88 @@
> >> +/*
> >> + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
> >> + */
> >> +
> >> +/*
> >> + * The code contained herein is licensed under the GNU General Public
> >> + * License. You may obtain a copy of the GNU General Public License
> >> + * Version 2 or later at the following locations:
> >> + *
> >> + * http://www.opensource.org/licenses/gpl-license.html
> >> + * http://www.gnu.org/copyleft/gpl.html
> >> + */
> >> +#ifndef __DRIVERS_NAND_DEVICE_INFO_H
> >> +#define __DRIVERS_NAND_DEVICE_INFO_H
> >> +
> >> +enum nand_device_cell_technology {
> >> + SLC = 0,
> >> + MLC = 1,
> >> +};
> >> +
> >> +/**
> >> + * @cell_technology: The storage cell technology.
> >> + * @busw: The bus width of the NAND.
> >> + * @chip_size_in_bytes: The total size of the storage behind a
single
> >> + * chip select, in bytes. Notice that this is *not*
> >> + * necessarily the total size of the storage in a
> >> + * *package*, which may contain several chips.
> >> + * @block_size_in_pages: The number of pages in a block.
> >> + * @page_total_size_in_bytes: The total size of a page, in bytes,
> >> including + * both the data and the OOB.
> >> + * @ecc_strength_in_bits: The strength of the ECC called for by the
> >> + * manufacturer, in number of correctable bits.
> >> + * @ecc_size_in_bytes: The size of the data block over which the
> >> + * manufacturer calls for the given ECC algorithm
> >> + * and strength.
> >> + */
> >> +struct nand_attr {
> >> + /* Technology */
> >> + enum nand_device_cell_technology cell_technology;
> >> +
> >> + /* bus width */
> >> +#define NAND_BUSWIDTH_8 0
> >> + uint32_t busw;
> >> +
> >> + /* Geometry */
> >> + uint64_t chip_size_in_bytes;
> >> + uint32_t block_size_in_pages;
> >> + uint32_t page_total_size_in_bytes;
> >> +
> >> + /* ECC */
> >> + uint16_t ecc_strength_in_bits;
> >> + uint16_t ecc_size_in_bytes;
> >> +};
> >> +
> >> +#define ID_BYTES (8)
> >> +/*
> >> + * struct nand_device_info - Information about a single NAND Flash
> >> device. + *
> >> + * This structure contains all the *essential* information about a NAND
> >> Flash + * device, derived from the device's data sheet.
> >> + */
> >> +struct nand_device_info {
> >> + /* id */
> >> + uint8_t id[ID_BYTES];
> >> + unsigned int id_len;
> >> +
> >> + /* Description */
> >> + const char *desc;
> >> +
> >> + /* attribute*/
> >> + struct nand_attr attr;
> >> +};
> >> +
> >> +/* macro for the NAND attribute */
> >> +#define ATTR(_a, _b, _c, _d, _e, _f, _g) \
> >> + { \
> >> + .cell_technology = (_a), \
> >> + .busw = (_b), \
> >> + .chip_size_in_bytes = (_c), \
> >> + .block_size_in_pages = (_d), \
> >> + .page_total_size_in_bytes = (_e), \
> >> + .ecc_strength_in_bits = (_f), \
> >> + .ecc_size_in_bytes = (_g), \
> >> + }
> >> +
> >> +struct nand_device_info *nand_device_get_info(const uint8_t
> >> id_bytes[]); +void nand_device_print_info(struct nand_device_info
> >> *info);
> >> +#endif
>
> Best Regards
> Huang Shijie
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 2/6] dmaengine: change the flags of request_irq()
2011-03-30 9:15 ` Lothar Waßmann
@ 2011-03-30 9:44 ` Huang Shijie
2011-03-31 7:02 ` [PATCH V3 2/6] dmaengine: add interrupt check for GPMI controller Huang Shijie
1 sibling, 0 replies; 31+ messages in thread
From: Huang Shijie @ 2011-03-30 9:44 UTC (permalink / raw)
To: Lothar Waßmann
Cc: linux, David.Woodhouse, dedekind1, linux-mtd, linux-arm-kernel,
ffainelli, shijie8, Shawn Guo
Hi:
> Shawn Guo writes:
>> On Wed, Mar 30, 2011 at 11:03:02AM +0200, Lothar Waßmann wrote:
>>> Hi,
>>>
>>> Huang Shijie writes:
>>>> The GPMI may have many DMA channels, such as the imx23 has
>>>> four DMA channels. All these DMA channels share the same interrupt.
>>>> So change the flags from '0' to IRQF_SHARED, else there will be
>>>> an EBUSY error returns.
>>>>
>>>> Signed-off-by: Huang Shijie<b32955@freescale.com>
>>>> ---
>>>> drivers/dma/mxs-dma.c | 2 +-
>>>> 1 files changed, 1 insertions(+), 1 deletions(-)
>>>>
>>>> diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
>>>> index 88aad4f..0ee5b52 100644
>>>> --- a/drivers/dma/mxs-dma.c
>>>> +++ b/drivers/dma/mxs-dma.c
>>>> @@ -328,7 +328,7 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
>>>> memset(mxs_chan->ccw, 0, PAGE_SIZE);
>>>>
>>>> ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
>>>> - 0, "mxs-dma", mxs_dma);
>>>> + IRQF_SHARED, "mxs-dma", mxs_dma);
>>>> if (ret)
>>>> goto err_irq;
>>>>
>>> IMO this is wrong. The interrupt is requested with all the same
>>> parameters for each DMA channel. So, actually it is not a shared IRQ,
>> The parameter mxs_chan->chan_irq is different for each channel, except
>> gpmi which has 4 channels sharing one irq.
>>
> That's what I mean. The other interrupts won't need the IRQF_SHARED
> flag anyway.
>
Ok. I will add a GPMI-INTERRUPT check in the mxs_dma_alloc_chan_resources().
>>> but an IRQ with the same handler registered multiple times, which is
>>> just nonsense.
>>>
>>> Instead of declaring it as shared, it would be more sensible to only
>>> register it for the first channel. Otherwise the handler will be
>>> called multiple times in case of an interrupt with only the first
>>> invocation doing all the work and the subsequent invocations just
>>> returning without doing anything.
>>>
>> --
>> Regards,
>> Shawn
>>
> Lothar Waßmann
Huang Shijie
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 3/6] MTD : add the database for the NANDs
2011-03-30 9:23 ` Florian Fainelli
@ 2011-03-30 9:54 ` Huang Shijie
0 siblings, 0 replies; 31+ messages in thread
From: Huang Shijie @ 2011-03-30 9:54 UTC (permalink / raw)
To: Florian Fainelli
Cc: linux, David.Woodhouse, dedekind1, linux-mtd, shijie8, linux-arm-kernel
Hi Florian:
> Hello Huang,
>
> On Wednesday 30 March 2011 11:05:59 Huang Shijie wrote:
>> Hi Florian:
>>
>> thanks for a so quick reply. :)
>>
>>> Hello Huang,
>>>
>>> On Wednesday 30 March 2011 10:40:10 Huang Shijie wrote:
>>>> This is a new database for the NANDs which is searched by the id_bytes.
>>> drivers/mtd//nand/nand_base.c will be able to detect all of your chips
>>> listed below based on the ids present in drivers/mtd/nand/nand_ids.c
>> yes.
>>
>> But I will use the new database to replace the old one.
>>
>> I will submit new patches to modify the generic code if my driver is
>> accepted.
> I think you can start right away submitting patches to modify generic code,
> this can either be a premilinary patch series to the GPMI driver, or in the
> same patch series as the GPMI driver.
>
I prefer to change the generic code after the driver is merged.
thanks.
I am too busy to change it right now.
>>> If you have new chips to support in the future, you should add them in
>>> drivers/mtd/nand/nand_ids.c and not keep this file.
>> The data structure nand_flash_dev{} does not contain enough information.
>> So I want to the nand_device_info{} to replace it in future.
> Ok, you should have written that in the patch description, otherwise it is
> misleading and I though you just duplicated code without knowing what the
> existing code could do.
>
my fault.
>>> I still do not understand why this would be needed, is it because the
>>> generic code does not provide enough informations for your driver?
>> yes.
>>
>> IMHO, the generic code is somehow trapped in a wrong way. :(
>> Paring the id bytes is not sufficient to get all the information you
>> need which is faced by me.
>>
>> What's more, I think the paring code is ugly, see the
>> nand_get_flash_type().
>>
>> Why not create a new database which contains all the necessary
>> information for a nand, and can be easy
>> find by the id bytes as the keyword?
> The idea is to hardcode as little information as possible, and let the rest be
> detected at runtime when possible. I think this it the right approach, because
> it is more future proof.
>
thanks.
>> I wish David and Artem give some advice about this.
> I would also like them to jump into this discussion.
>
me too:)
>>>> Signed-off-by: Huang Shijie<b32955@freescale.com>
>>>> ---
>>>>
>>>> drivers/mtd/nand/nand_device_info.c | 157
>>>>
>>>> +++++++++++++++++++++++++++++++++++ drivers/mtd/nand/nand_device_info.h
>>>> |
>>>>
>>>> 88 +++++++++++++++++++
>>>> 2 files changed, 245 insertions(+), 0 deletions(-)
>>>> create mode 100644 drivers/mtd/nand/nand_device_info.c
>>>> create mode 100644 drivers/mtd/nand/nand_device_info.h
>>>>
>>>> diff --git a/drivers/mtd/nand/nand_device_info.c
>>>> b/drivers/mtd/nand/nand_device_info.c new file mode 100644
>>>> index 0000000..757ed89
>>>> --- /dev/null
>>>> +++ b/drivers/mtd/nand/nand_device_info.c
>>>> @@ -0,0 +1,157 @@
>>>> +/*
>>>> + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights
>>>> Reserved. + */
>>>> +
>>>> +/*
>>>> + * The code contained herein is licensed under the GNU General Public
>>>> + * License. You may obtain a copy of the GNU General Public License
>>>> + * Version 2 or later at the following locations:
>>>> + *
>>>> + * http://www.opensource.org/licenses/gpl-license.html
>>>> + * http://www.gnu.org/copyleft/gpl.html
>>>> + */
>>>> +#include<asm/sizes.h>
>>>> +#include<linux/mtd/nand.h>
>>>> +
>>>> +#include "nand_device_info.h"
>>>> +
>>>> +static const struct nand_device_info samsung_nand[] = {
>>>> + {
>>>> + .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
>>>> + .id_len = 8,
>>>> + .desc = "K9G8G08U0M, K9HAG08U1M",
>>>> + .attr = ATTR(MLC, NAND_BUSWIDTH_8, 1LL * SZ_1G, 128,
>>>> + 2 * SZ_1K + 64, 8, 512),
>>>> + }, {
>>>> + .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
>>>> + .id_len = 8,
>>>> + .desc = "K9LBG08U0D",
>>>> + .attr = ATTR(MLC, NAND_BUSWIDTH_8, 4LL * SZ_1G, 128,
>>>> + 4 * SZ_1K + 218, 16, 512),
>>>> + }, {
>>>> + .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
>>>> + .id_len = 8,
>>>> + .desc = "K9GAG08U0M",
>>>> + .attr = ATTR(MLC, NAND_BUSWIDTH_8, 2LL * SZ_1G, 128,
>>>> + 4 * SZ_1K + 218, 16, 512),
>>>> + }, {
>>>> + /* end of the table. */
>>>> + .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
>>>> + },
>>>> +};
>>>> +
>>>> +/* macro to get the id bytes */
>>>> +#define ID_GET_MFR_CODE(id) ((id)[0])
>>>> +
>>>> +void nand_device_print_info(struct nand_device_info *info)
>>>> +{
>>>> + unsigned i;
>>>> + const char *mfr_name;
>>>> + const char *cell_technology_name;
>>>> + uint64_t chip_size;
>>>> + const char *chip_size_units;
>>>> + unsigned page_size;
>>>> + unsigned oob_size;
>>>> + struct nand_attr *attr =&info->attr;
>>>> +
>>>> + /* Prepare the manufacturer name. */
>>>> + mfr_name = "Unknown";
>>>> + for (i = 0; nand_manuf_ids[i].id; i++) {
>>>> + if (nand_manuf_ids[i].id == ID_GET_MFR_CODE(info->id)) {
>>>> + mfr_name = nand_manuf_ids[i].name;
>>>> + break;
>>>> + }
>>>> + }
>>>> +
>>>> + /* Prepare the name of the cell technology. */
>>>> + switch (attr->cell_technology) {
>>>> + case SLC:
>>>> + cell_technology_name = "SLC";
>>>> + break;
>>>> + case MLC:
>>>> + cell_technology_name = "MLC";
>>>> + break;
>>>> + default:
>>>> + cell_technology_name = "Unknown";
>>>> + break;
>>>> + }
>>>> +
>>>> + /* Prepare the chip size. */
>>>> + if ((attr->chip_size_in_bytes>= SZ_1G)&&
>>>> + !(attr->chip_size_in_bytes % SZ_1G)) {
>>>> + chip_size = attr->chip_size_in_bytes / ((uint64_t)
> SZ_1G);
>>>> + chip_size_units = "GiB";
>>>> + } else if ((attr->chip_size_in_bytes>= SZ_1M)&&
>>>> + !(attr->chip_size_in_bytes % SZ_1M)) {
>>>> + chip_size = attr->chip_size_in_bytes / ((uint64_t)
> SZ_1M);
>>>> + chip_size_units = "MiB";
>>>> + } else {
>>>> + chip_size = attr->chip_size_in_bytes;
>>>> + chip_size_units = "B";
>>>> + }
>>>> +
>>>> + /* Prepare the page geometry. */
>>>> + page_size = (1<< (fls(attr->page_total_size_in_bytes) - 1));
>>>> + oob_size = attr->page_total_size_in_bytes - page_size;
>>>> +
>>>> + /* Print the infomation. */
>>>> + pr_info("--------------------------------------\n");
>>>> + pr_info(" NAND device infomation (RAW)\n");
>>>> + pr_info("--------------------------------------\n");
>>>> + pr_info("Manufacturer : %s (0x%02x)\n", mfr_name, info->id[0]);
>>>> + pr_info("Device Code : 0x%02x\n", info->id[1]);
>>>> + pr_info("Cell Technology : %s\n", cell_technology_name);
>>>> + pr_info("Chip Size : %llu %s\n", chip_size,
> chip_size_units);
>>>> + pr_info("Pages per Block : %u\n", attr->block_size_in_pages);
>>>> + pr_info("Page Geometry : %u+%u\n", page_size, oob_size);
>>>> + pr_info("ECC Strength : %u bits\n", attr-
>> ecc_strength_in_bits);
>>>> + pr_info("ECC Size : %u B\n", attr->ecc_size_in_bytes);
>>>> + pr_info("Description : %s\n", info->desc);
>>>> +}
>>>> +
>>>> +static struct nand_device_info * __init
>>>> +search_table(const struct nand_device_info *table, const uint8_t id[])
>>>> +{
>>>> + struct nand_device_info *info = (struct nand_device_info *)table;
>>>> +
>>>> + while (ID_GET_MFR_CODE(info->id)) {
>>>> + int i;
>>>> +
>>>> + /* match all the valid id bytes. Is it too strict? */
>>>> + for (i = 0; i< info->id_len; i++)
>>>> + if (info->id[i] != id[i])
>>>> + break;
>>>> +
>>>> + /* found it */
>>>> + if (i == info->id_len)
>>>> + return info;
>>>> + info++;
>>>> + }
>>>> + return NULL;
>>>> +}
>>>> +
>>>> +struct nand_device_mfr_info {
>>>> + uint8_t id;
>>>> + const struct nand_device_info *table;
>>>> +};
>>>> +
>>>> +static const struct nand_device_mfr_info nand_device_mfr_directory[] =
>>>> { + { NAND_MFR_SAMSUNG, samsung_nand },
>>>> + { 0, NULL },
>>>> +};
>>>> +
>>>> +struct nand_device_info *nand_device_get_info(const uint8_t id[])
>>>> +{
>>>> + uint8_t mfr_id = ID_GET_MFR_CODE(id);
>>>> + unsigned i;
>>>> +
>>>> + for (i = 0; nand_device_mfr_directory[i].id; i++) {
>>>> + if (nand_device_mfr_directory[i].id == mfr_id) {
>>>> + const struct nand_device_info *table;
>>>> +
>>>> + table = nand_device_mfr_directory[i].table;
>>>> + return search_table(table, id);
>>>> + }
>>>> + }
>>>> + return NULL;
>>>> +}
>>>> diff --git a/drivers/mtd/nand/nand_device_info.h
>>>> b/drivers/mtd/nand/nand_device_info.h new file mode 100644
>>>> index 0000000..15f688d
>>>> --- /dev/null
>>>> +++ b/drivers/mtd/nand/nand_device_info.h
>>>> @@ -0,0 +1,88 @@
>>>> +/*
>>>> + * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
>>>> + */
>>>> +
>>>> +/*
>>>> + * The code contained herein is licensed under the GNU General Public
>>>> + * License. You may obtain a copy of the GNU General Public License
>>>> + * Version 2 or later at the following locations:
>>>> + *
>>>> + * http://www.opensource.org/licenses/gpl-license.html
>>>> + * http://www.gnu.org/copyleft/gpl.html
>>>> + */
>>>> +#ifndef __DRIVERS_NAND_DEVICE_INFO_H
>>>> +#define __DRIVERS_NAND_DEVICE_INFO_H
>>>> +
>>>> +enum nand_device_cell_technology {
>>>> + SLC = 0,
>>>> + MLC = 1,
>>>> +};
>>>> +
>>>> +/**
>>>> + * @cell_technology: The storage cell technology.
>>>> + * @busw: The bus width of the NAND.
>>>> + * @chip_size_in_bytes: The total size of the storage behind a
> single
>>>> + * chip select, in bytes. Notice that this is *not*
>>>> + * necessarily the total size of the storage in a
>>>> + * *package*, which may contain several chips.
>>>> + * @block_size_in_pages: The number of pages in a block.
>>>> + * @page_total_size_in_bytes: The total size of a page, in bytes,
>>>> including + * both the data and the OOB.
>>>> + * @ecc_strength_in_bits: The strength of the ECC called for by the
>>>> + * manufacturer, in number of correctable bits.
>>>> + * @ecc_size_in_bytes: The size of the data block over which the
>>>> + * manufacturer calls for the given ECC algorithm
>>>> + * and strength.
>>>> + */
>>>> +struct nand_attr {
>>>> + /* Technology */
>>>> + enum nand_device_cell_technology cell_technology;
>>>> +
>>>> + /* bus width */
>>>> +#define NAND_BUSWIDTH_8 0
>>>> + uint32_t busw;
>>>> +
>>>> + /* Geometry */
>>>> + uint64_t chip_size_in_bytes;
>>>> + uint32_t block_size_in_pages;
>>>> + uint32_t page_total_size_in_bytes;
>>>> +
>>>> + /* ECC */
>>>> + uint16_t ecc_strength_in_bits;
>>>> + uint16_t ecc_size_in_bytes;
>>>> +};
>>>> +
>>>> +#define ID_BYTES (8)
>>>> +/*
>>>> + * struct nand_device_info - Information about a single NAND Flash
>>>> device. + *
>>>> + * This structure contains all the *essential* information about a NAND
>>>> Flash + * device, derived from the device's data sheet.
>>>> + */
>>>> +struct nand_device_info {
>>>> + /* id */
>>>> + uint8_t id[ID_BYTES];
>>>> + unsigned int id_len;
>>>> +
>>>> + /* Description */
>>>> + const char *desc;
>>>> +
>>>> + /* attribute*/
>>>> + struct nand_attr attr;
>>>> +};
>>>> +
>>>> +/* macro for the NAND attribute */
>>>> +#define ATTR(_a, _b, _c, _d, _e, _f, _g) \
>>>> + { \
>>>> + .cell_technology = (_a), \
>>>> + .busw = (_b), \
>>>> + .chip_size_in_bytes = (_c), \
>>>> + .block_size_in_pages = (_d), \
>>>> + .page_total_size_in_bytes = (_e), \
>>>> + .ecc_strength_in_bits = (_f), \
>>>> + .ecc_size_in_bytes = (_g), \
>>>> + }
>>>> +
>>>> +struct nand_device_info *nand_device_get_info(const uint8_t
>>>> id_bytes[]); +void nand_device_print_info(struct nand_device_info
>>>> *info);
>>>> +#endif
>> Best Regards
>> Huang Shijie
>>
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Best Regards
Huang Shijie
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH V3 2/6] dmaengine: add interrupt check for GPMI controller
2011-03-30 9:15 ` Lothar Waßmann
2011-03-30 9:44 ` Huang Shijie
@ 2011-03-31 7:02 ` Huang Shijie
2011-03-31 8:02 ` Lothar Waßmann
1 sibling, 1 reply; 31+ messages in thread
From: Huang Shijie @ 2011-03-31 7:02 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Huang Shijie, linux-mtd, shawn.guo
The GPMI may have many DMA channels, such as the imx23 has
four DMA channels. All these DMA channels share the same interrupt.
Add the interrupt check for the GPMI, only the first DMA channel will
register the irq.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/dma/mxs-dma.c | 36 ++++++++++++++++++++++++++++++++----
1 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index 88aad4f..db36bf1 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -26,6 +26,8 @@
#include <asm/irq.h>
#include <mach/mxs.h>
#include <mach/dma.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
#include <mach/common.h>
/*
@@ -306,6 +308,30 @@ static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
return IRQ_HANDLED;
}
+/* The GPMI has several DMA channels, only the first can register the irq. */
+static bool irq_check(struct mxs_dma_chan *mxs_chan)
+{
+ int irq_num = mxs_chan->chan_irq;
+
+#ifdef CONFIG_SOC_IMX23
+ if (cpu_is_mx23() && irq_num == MX23_INT_GPMI_DMA) {
+ if (mxs_chan->chan.chan_id == MX23_DMA_GPMI0)
+ return true;
+ else
+ return false;
+ }
+#endif
+#ifdef CONFIG_SOC_IMX28
+ if (cpu_is_mx28() && irq_num == MX28_INT_GPMI_DMA) {
+ if (mxs_chan->chan.chan_id == MX28_DMA_GPMI0)
+ return true;
+ else
+ return false;
+ }
+#endif
+ return true;
+}
+
static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
{
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
@@ -327,10 +353,12 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
memset(mxs_chan->ccw, 0, PAGE_SIZE);
- ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
- 0, "mxs-dma", mxs_dma);
- if (ret)
- goto err_irq;
+ if (irq_check(mxs_chan)) {
+ ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
+ 0, "mxs-dma", mxs_dma);
+ if (ret)
+ goto err_irq;
+ }
ret = clk_enable(mxs_dma->clk);
if (ret)
--
1.7.0.4
^ permalink raw reply related [flat|nested] 31+ messages in thread
* Re: [PATCH V3 2/6] dmaengine: add interrupt check for GPMI controller
2011-03-31 7:02 ` [PATCH V3 2/6] dmaengine: add interrupt check for GPMI controller Huang Shijie
@ 2011-03-31 8:02 ` Lothar Waßmann
2011-03-31 8:50 ` Huang Shijie
0 siblings, 1 reply; 31+ messages in thread
From: Lothar Waßmann @ 2011-03-31 8:02 UTC (permalink / raw)
To: Huang Shijie; +Cc: linux-mtd, shawn.guo, linux-arm-kernel
Hi,
Huang Shijie writes:
> The GPMI may have many DMA channels, such as the imx23 has
> four DMA channels. All these DMA channels share the same interrupt.
> Add the interrupt check for the GPMI, only the first DMA channel will
> register the irq.
>
> Signed-off-by: Huang Shijie <b32955@freescale.com>
> ---
> drivers/dma/mxs-dma.c | 36 ++++++++++++++++++++++++++++++++----
> 1 files changed, 32 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
> index 88aad4f..db36bf1 100644
> --- a/drivers/dma/mxs-dma.c
> +++ b/drivers/dma/mxs-dma.c
> @@ -26,6 +26,8 @@
> #include <asm/irq.h>
> #include <mach/mxs.h>
> #include <mach/dma.h>
> +#include <mach/mx23.h>
> +#include <mach/mx28.h>
> #include <mach/common.h>
>
> /*
> @@ -306,6 +308,30 @@ static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
> return IRQ_HANDLED;
> }
>
> +/* The GPMI has several DMA channels, only the first can register the irq. */
> +static bool irq_check(struct mxs_dma_chan *mxs_chan)
> +{
> + int irq_num = mxs_chan->chan_irq;
> +
> +#ifdef CONFIG_SOC_IMX23
> + if (cpu_is_mx23() && irq_num == MX23_INT_GPMI_DMA) {
> + if (mxs_chan->chan.chan_id == MX23_DMA_GPMI0)
> + return true;
> + else
> + return false;
> + }
> +#endif
> +#ifdef CONFIG_SOC_IMX28
> + if (cpu_is_mx28() && irq_num == MX28_INT_GPMI_DMA) {
> + if (mxs_chan->chan.chan_id == MX28_DMA_GPMI0)
> + return true;
> + else
> + return false;
> + }
> +#endif
> + return true;
> +}
>
You should make the distinction based on the platform_id, which would
save you the ugly ifdef's and cpu_is_... macros.
Lothar Waßmann
--
___________________________________________________________
Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Geschäftsführer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996
www.karo-electronics.de | info@karo-electronics.de
___________________________________________________________
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 2/6] dmaengine: add interrupt check for GPMI controller
2011-03-31 8:50 ` Huang Shijie
@ 2011-03-31 8:50 ` Lothar Waßmann
2011-03-31 9:08 ` Huang Shijie
0 siblings, 1 reply; 31+ messages in thread
From: Lothar Waßmann @ 2011-03-31 8:50 UTC (permalink / raw)
To: Huang Shijie; +Cc: linux-mtd, shawn.guo, linux-arm-kernel
Hi,
Huang Shijie writes:
> Hi:
> > Hi,
> >
> > Huang Shijie writes:
> >> The GPMI may have many DMA channels, such as the imx23 has
> >> four DMA channels. All these DMA channels share the same interrupt.
> >> Add the interrupt check for the GPMI, only the first DMA channel will
> >> register the irq.
> >>
> >> Signed-off-by: Huang Shijie<b32955@freescale.com>
> >> ---
> >> drivers/dma/mxs-dma.c | 36 ++++++++++++++++++++++++++++++++----
> >> 1 files changed, 32 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
> >> index 88aad4f..db36bf1 100644
> >> --- a/drivers/dma/mxs-dma.c
> >> +++ b/drivers/dma/mxs-dma.c
> >> @@ -26,6 +26,8 @@
> >> #include<asm/irq.h>
> >> #include<mach/mxs.h>
> >> #include<mach/dma.h>
> >> +#include<mach/mx23.h>
> >> +#include<mach/mx28.h>
> >> #include<mach/common.h>
> >>
> >> /*
> >> @@ -306,6 +308,30 @@ static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
> >> return IRQ_HANDLED;
> >> }
> >>
> >> +/* The GPMI has several DMA channels, only the first can register the irq. */
> >> +static bool irq_check(struct mxs_dma_chan *mxs_chan)
> >> +{
> >> + int irq_num = mxs_chan->chan_irq;
> >> +
> >> +#ifdef CONFIG_SOC_IMX23
> >> + if (cpu_is_mx23()&& irq_num == MX23_INT_GPMI_DMA) {
> >> + if (mxs_chan->chan.chan_id == MX23_DMA_GPMI0)
> >> + return true;
> >> + else
> >> + return false;
> >> + }
> >> +#endif
> >> +#ifdef CONFIG_SOC_IMX28
> >> + if (cpu_is_mx28()&& irq_num == MX28_INT_GPMI_DMA) {
> >> + if (mxs_chan->chan.chan_id == MX28_DMA_GPMI0)
> >> + return true;
> >> + else
> >> + return false;
> >> + }
> >> +#endif
> >> + return true;
> >> +}
> >>
> > You should make the distinction based on the platform_id, which would
> > save you the ugly ifdef's and cpu_is_... macros.
> >
> >
> This in the DMA driver.
> Do you want me to change the DMA driver to add the platform_id?
> The DMA driver has already used the cpu_is_xx() macros.
>
The mxs-dma driver is already using platform ids!
Lothar Waßmann
--
___________________________________________________________
Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Geschäftsführer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996
www.karo-electronics.de | info@karo-electronics.de
___________________________________________________________
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 2/6] dmaengine: add interrupt check for GPMI controller
2011-03-31 8:02 ` Lothar Waßmann
@ 2011-03-31 8:50 ` Huang Shijie
2011-03-31 8:50 ` Lothar Waßmann
0 siblings, 1 reply; 31+ messages in thread
From: Huang Shijie @ 2011-03-31 8:50 UTC (permalink / raw)
To: Lothar Waßmann; +Cc: linux-mtd, shawn.guo, linux-arm-kernel
Hi:
> Hi,
>
> Huang Shijie writes:
>> The GPMI may have many DMA channels, such as the imx23 has
>> four DMA channels. All these DMA channels share the same interrupt.
>> Add the interrupt check for the GPMI, only the first DMA channel will
>> register the irq.
>>
>> Signed-off-by: Huang Shijie<b32955@freescale.com>
>> ---
>> drivers/dma/mxs-dma.c | 36 ++++++++++++++++++++++++++++++++----
>> 1 files changed, 32 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
>> index 88aad4f..db36bf1 100644
>> --- a/drivers/dma/mxs-dma.c
>> +++ b/drivers/dma/mxs-dma.c
>> @@ -26,6 +26,8 @@
>> #include<asm/irq.h>
>> #include<mach/mxs.h>
>> #include<mach/dma.h>
>> +#include<mach/mx23.h>
>> +#include<mach/mx28.h>
>> #include<mach/common.h>
>>
>> /*
>> @@ -306,6 +308,30 @@ static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
>> return IRQ_HANDLED;
>> }
>>
>> +/* The GPMI has several DMA channels, only the first can register the irq. */
>> +static bool irq_check(struct mxs_dma_chan *mxs_chan)
>> +{
>> + int irq_num = mxs_chan->chan_irq;
>> +
>> +#ifdef CONFIG_SOC_IMX23
>> + if (cpu_is_mx23()&& irq_num == MX23_INT_GPMI_DMA) {
>> + if (mxs_chan->chan.chan_id == MX23_DMA_GPMI0)
>> + return true;
>> + else
>> + return false;
>> + }
>> +#endif
>> +#ifdef CONFIG_SOC_IMX28
>> + if (cpu_is_mx28()&& irq_num == MX28_INT_GPMI_DMA) {
>> + if (mxs_chan->chan.chan_id == MX28_DMA_GPMI0)
>> + return true;
>> + else
>> + return false;
>> + }
>> +#endif
>> + return true;
>> +}
>>
> You should make the distinction based on the platform_id, which would
> save you the ugly ifdef's and cpu_is_... macros.
>
>
This in the DMA driver.
Do you want me to change the DMA driver to add the platform_id?
The DMA driver has already used the cpu_is_xx() macros.
Best Regards
Huang Shijie
> Lothar Waßmann
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 2/6] dmaengine: add interrupt check for GPMI controller
2011-03-31 8:50 ` Lothar Waßmann
@ 2011-03-31 9:08 ` Huang Shijie
2011-03-31 9:34 ` Lothar Waßmann
2011-04-01 3:47 ` Shawn Guo
0 siblings, 2 replies; 31+ messages in thread
From: Huang Shijie @ 2011-03-31 9:08 UTC (permalink / raw)
To: Lothar Waßmann; +Cc: linux-mtd, shawn.guo, linux-arm-kernel
Hi,
> Hi,
>
> Huang Shijie writes:
>> Hi:
>>> Hi,
>>>
>>> Huang Shijie writes:
>>>> The GPMI may have many DMA channels, such as the imx23 has
>>>> four DMA channels. All these DMA channels share the same interrupt.
>>>> Add the interrupt check for the GPMI, only the first DMA channel will
>>>> register the irq.
>>>>
>>>> Signed-off-by: Huang Shijie<b32955@freescale.com>
>>>> ---
>>>> drivers/dma/mxs-dma.c | 36 ++++++++++++++++++++++++++++++++----
>>>> 1 files changed, 32 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
>>>> index 88aad4f..db36bf1 100644
>>>> --- a/drivers/dma/mxs-dma.c
>>>> +++ b/drivers/dma/mxs-dma.c
>>>> @@ -26,6 +26,8 @@
>>>> #include<asm/irq.h>
>>>> #include<mach/mxs.h>
>>>> #include<mach/dma.h>
>>>> +#include<mach/mx23.h>
>>>> +#include<mach/mx28.h>
>>>> #include<mach/common.h>
>>>>
>>>> /*
>>>> @@ -306,6 +308,30 @@ static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
>>>> return IRQ_HANDLED;
>>>> }
>>>>
>>>> +/* The GPMI has several DMA channels, only the first can register the irq. */
>>>> +static bool irq_check(struct mxs_dma_chan *mxs_chan)
>>>> +{
>>>> + int irq_num = mxs_chan->chan_irq;
>>>> +
>>>> +#ifdef CONFIG_SOC_IMX23
>>>> + if (cpu_is_mx23()&& irq_num == MX23_INT_GPMI_DMA) {
>>>> + if (mxs_chan->chan.chan_id == MX23_DMA_GPMI0)
>>>> + return true;
>>>> + else
>>>> + return false;
>>>> + }
>>>> +#endif
>>>> +#ifdef CONFIG_SOC_IMX28
>>>> + if (cpu_is_mx28()&& irq_num == MX28_INT_GPMI_DMA) {
>>>> + if (mxs_chan->chan.chan_id == MX28_DMA_GPMI0)
>>>> + return true;
>>>> + else
>>>> + return false;
>>>> + }
>>>> +#endif
>>>> + return true;
>>>> +}
>>>>
>>> You should make the distinction based on the platform_id, which would
>>> save you the ugly ifdef's and cpu_is_... macros.
>>>
>>>
>> This in the DMA driver.
>> Do you want me to change the DMA driver to add the platform_id?
>> The DMA driver has already used the cpu_is_xx() macros.
>>
> The mxs-dma driver is already using platform ids!
>
>
Do you mean the mxd_dma_type[] ?
How can i distinction the imx23 and imx28 with it ?
It seems can not be used to do the work.
thanks.
Huang Shijie
> Lothar Waßmann
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 2/6] dmaengine: add interrupt check for GPMI controller
2011-03-31 9:08 ` Huang Shijie
@ 2011-03-31 9:34 ` Lothar Waßmann
2011-04-01 3:47 ` Shawn Guo
1 sibling, 0 replies; 31+ messages in thread
From: Lothar Waßmann @ 2011-03-31 9:34 UTC (permalink / raw)
To: Huang Shijie; +Cc: linux-mtd, shawn.guo, linux-arm-kernel
Hi,
Huang Shijie writes:
> Hi,
> > Hi,
> >
> > Huang Shijie writes:
> >> Hi:
> >>> Hi,
> >>>
> >>> Huang Shijie writes:
> >>>> The GPMI may have many DMA channels, such as the imx23 has
> >>>> four DMA channels. All these DMA channels share the same interrupt.
> >>>> Add the interrupt check for the GPMI, only the first DMA channel will
> >>>> register the irq.
> >>>>
> >>>> Signed-off-by: Huang Shijie<b32955@freescale.com>
> >>>> ---
> >>>> drivers/dma/mxs-dma.c | 36 ++++++++++++++++++++++++++++++++----
> >>>> 1 files changed, 32 insertions(+), 4 deletions(-)
> >>>>
> >>>> diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
> >>>> index 88aad4f..db36bf1 100644
> >>>> --- a/drivers/dma/mxs-dma.c
> >>>> +++ b/drivers/dma/mxs-dma.c
> >>>> @@ -26,6 +26,8 @@
> >>>> #include<asm/irq.h>
> >>>> #include<mach/mxs.h>
> >>>> #include<mach/dma.h>
> >>>> +#include<mach/mx23.h>
> >>>> +#include<mach/mx28.h>
> >>>> #include<mach/common.h>
> >>>>
> >>>> /*
> >>>> @@ -306,6 +308,30 @@ static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
> >>>> return IRQ_HANDLED;
> >>>> }
> >>>>
> >>>> +/* The GPMI has several DMA channels, only the first can register the irq. */
> >>>> +static bool irq_check(struct mxs_dma_chan *mxs_chan)
> >>>> +{
> >>>> + int irq_num = mxs_chan->chan_irq;
> >>>> +
> >>>> +#ifdef CONFIG_SOC_IMX23
> >>>> + if (cpu_is_mx23()&& irq_num == MX23_INT_GPMI_DMA) {
> >>>> + if (mxs_chan->chan.chan_id == MX23_DMA_GPMI0)
> >>>> + return true;
> >>>> + else
> >>>> + return false;
> >>>> + }
> >>>> +#endif
> >>>> +#ifdef CONFIG_SOC_IMX28
> >>>> + if (cpu_is_mx28()&& irq_num == MX28_INT_GPMI_DMA) {
> >>>> + if (mxs_chan->chan.chan_id == MX28_DMA_GPMI0)
> >>>> + return true;
> >>>> + else
> >>>> + return false;
> >>>> + }
> >>>> +#endif
> >>>> + return true;
> >>>> +}
> >>>>
> >>> You should make the distinction based on the platform_id, which would
> >>> save you the ugly ifdef's and cpu_is_... macros.
> >>>
> >>>
> >> This in the DMA driver.
> >> Do you want me to change the DMA driver to add the platform_id?
> >> The DMA driver has already used the cpu_is_xx() macros.
> >>
> > The mxs-dma driver is already using platform ids!
> >
> >
> Do you mean the mxd_dma_type[] ?
>
> How can i distinction the imx23 and imx28 with it ?
> It seems can not be used to do the work.
>
It should be extended to make this distinction possible.
Lothar Waßmann
--
___________________________________________________________
Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Geschäftsführer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996
www.karo-electronics.de | info@karo-electronics.de
___________________________________________________________
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 3/6] MTD : add the database for the NANDs
2011-03-30 9:05 ` Huang Shijie
2011-03-30 9:23 ` Florian Fainelli
@ 2011-03-31 10:10 ` Artem Bityutskiy
2011-03-31 14:17 ` Huang Shijie
1 sibling, 1 reply; 31+ messages in thread
From: Artem Bityutskiy @ 2011-03-31 10:10 UTC (permalink / raw)
To: Huang Shijie
Cc: linux, David.Woodhouse, linux-mtd, Florian Fainelli, shijie8,
linux-arm-kernel
Hi,
On Wed, 2011-03-30 at 17:05 +0800, Huang Shijie wrote:
> > On Wednesday 30 March 2011 10:40:10 Huang Shijie wrote:
> >> This is a new database for the NANDs which is searched by the id_bytes.
> > drivers/mtd//nand/nand_base.c will be able to detect all of your chips listed
> > below based on the ids present in drivers/mtd/nand/nand_ids.c
> >
> yes.
>
> But I will use the new database to replace the old one.
>
> I will submit new patches to modify the generic code if my driver is
> accepted.
Sorry, but this is not how the opensource community works. The common
practice everywhere in the kernel is that if the generic code/framework
is too limiting, you first change the framework, then start using it. We
do not do things like - I'll first create my custom solution, and then I
promise I will change the framework.
Again, this is not just MTD, this is everywhere in the kernel. This is
how linux goes forward - we force people to improve common code and
accept their drivers, and everyone benefits form this. Yes, this is more
work for you, of course, sorry :-)
> > If you have new chips to support in the future, you should add them in
> > drivers/mtd/nand/nand_ids.c and not keep this file.
> >
> The data structure nand_flash_dev{} does not contain enough information.
> So I want to the nand_device_info{} to replace it in future.
Just add this information, if it is of generic nature (like SLC/MLC
flag, required ECC strength, etc).
> > I still do not understand why this would be needed, is it because the generic
> > code does not provide enough informations for your driver?
> >
> yes.
>
> IMHO, the generic code is somehow trapped in a wrong way. :(
Fix this please :-)
> Paring the id bytes is not sufficient to get all the information you
> need which is faced by me.
Fix this too :-)
> What's more, I think the paring code is ugly, see the nand_get_flash_type().
You are welcome to fix this. There is _a lot_ of ugly code in MTD
because no one loves it. Give it some love :-)
> Why not create a new database which contains all the necessary
> information for a nand, and can be easy
> find by the id bytes as the keyword?
You can create this database by extending/improving/cleaning up the
existing code base with a nice series of patches.
--
Best Regards,
Artem Bityutskiy (Артём Битюцкий)
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 3/6] MTD : add the database for the NANDs
2011-03-31 10:10 ` Artem Bityutskiy
@ 2011-03-31 14:17 ` Huang Shijie
2011-09-14 15:44 ` Brian Norris
0 siblings, 1 reply; 31+ messages in thread
From: Huang Shijie @ 2011-03-31 14:17 UTC (permalink / raw)
To: dedekind1
Cc: linux, David.Woodhouse, Huang Shijie, linux-mtd,
Florian Fainelli, linux-arm-kernel
hi,
2011/3/31 Artem Bityutskiy <dedekind1@gmail.com>:
> Hi,
>
> On Wed, 2011-03-30 at 17:05 +0800, Huang Shijie wrote:
>> > On Wednesday 30 March 2011 10:40:10 Huang Shijie wrote:
>> >> This is a new database for the NANDs which is searched by the id_bytes.
>> > drivers/mtd//nand/nand_base.c will be able to detect all of your chips listed
>> > below based on the ids present in drivers/mtd/nand/nand_ids.c
>> >
>> yes.
>>
>> But I will use the new database to replace the old one.
>>
>> I will submit new patches to modify the generic code if my driver is
>> accepted.
>
> Sorry, but this is not how the opensource community works. The common
> practice everywhere in the kernel is that if the generic code/framework
> is too limiting, you first change the framework, then start using it. We
> do not do things like - I'll first create my custom solution, and then I
> promise I will change the framework.
>
got it.
> Again, this is not just MTD, this is everywhere in the kernel. This is
> how linux goes forward - we force people to improve common code and
> accept their drivers, and everyone benefits form this. Yes, this is more
> work for you, of course, sorry :-)
>
thanks :)
>> > If you have new chips to support in the future, you should add them in
>> > drivers/mtd/nand/nand_ids.c and not keep this file.
>> >
>> The data structure nand_flash_dev{} does not contain enough information.
>> So I want to the nand_device_info{} to replace it in future.
>
> Just add this information, if it is of generic nature (like SLC/MLC
> flag, required ECC strength, etc).
>
>> > I still do not understand why this would be needed, is it because the generic
>> > code does not provide enough informations for your driver?
>> >
>> yes.
>>
>> IMHO, the generic code is somehow trapped in a wrong way. :(
>
> Fix this please :-)
>
>> Paring the id bytes is not sufficient to get all the information you
>> need which is faced by me.
>
> Fix this too :-)
>
>> What's more, I think the paring code is ugly, see the nand_get_flash_type().
>
> You are welcome to fix this. There is _a lot_ of ugly code in MTD
> because no one loves it. Give it some love :-)
>
>> Why not create a new database which contains all the necessary
>> information for a nand, and can be easy
>> find by the id bytes as the keyword?
>
> You can create this database by extending/improving/cleaning up the
> existing code base with a nice series of patches.
>
ok. I will try to fix the generic code before my driver is submitted.
Best Regards.
> --
> Best Regards,
> Artem Bityutskiy (Артём Битюцкий)
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 2/6] dmaengine: add interrupt check for GPMI controller
2011-03-31 9:08 ` Huang Shijie
2011-03-31 9:34 ` Lothar Waßmann
@ 2011-04-01 3:47 ` Shawn Guo
2011-04-01 4:36 ` Huang Shijie
1 sibling, 1 reply; 31+ messages in thread
From: Shawn Guo @ 2011-04-01 3:47 UTC (permalink / raw)
To: Huang Shijie; +Cc: linux-mtd, linux-arm-kernel
On Thu, Mar 31, 2011 at 05:08:54PM +0800, Huang Shijie wrote:
[...]
> >>>You should make the distinction based on the platform_id, which would
> >>>save you the ugly ifdef's and cpu_is_... macros.
> >>>
> >>>
> >>This in the DMA driver.
> >>Do you want me to change the DMA driver to add the platform_id?
> >>The DMA driver has already used the cpu_is_xx() macros.
> >>
> >The mxs-dma driver is already using platform ids!
> >
> >
> Do you mean the mxd_dma_type[] ?
>
> How can i distinction the imx23 and imx28 with it ?
> It seems can not be used to do the work.
>
You can drop the dmaengine patch from your gpmi series. I will find
some time to fix this together with removing cpu_is_xx() and inclusion
of mxs.h, to get it prepared for i.mx50 aphb-dma support.
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 2/6] dmaengine: add interrupt check for GPMI controller
2011-04-01 3:47 ` Shawn Guo
@ 2011-04-01 4:36 ` Huang Shijie
0 siblings, 0 replies; 31+ messages in thread
From: Huang Shijie @ 2011-04-01 4:36 UTC (permalink / raw)
To: Shawn Guo; +Cc: linux-mtd, linux-arm-kernel
hi:
> On Thu, Mar 31, 2011 at 05:08:54PM +0800, Huang Shijie wrote:
> [...]
>>>>> You should make the distinction based on the platform_id, which would
>>>>> save you the ugly ifdef's and cpu_is_... macros.
>>>>>
>>>>>
>>>> This in the DMA driver.
>>>> Do you want me to change the DMA driver to add the platform_id?
>>>> The DMA driver has already used the cpu_is_xx() macros.
>>>>
>>> The mxs-dma driver is already using platform ids!
>>>
>>>
>> Do you mean the mxd_dma_type[] ?
>>
>> How can i distinction the imx23 and imx28 with it ?
>> It seems can not be used to do the work.
>>
> You can drop the dmaengine patch from your gpmi series. I will find
> some time to fix this together with removing cpu_is_xx() and inclusion
> of mxs.h, to get it prepared for i.mx50 aphb-dma support.
>
ok, thanks.
Huang Shijie
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 3/6] MTD : add the database for the NANDs
2011-03-31 14:17 ` Huang Shijie
@ 2011-09-14 15:44 ` Brian Norris
2011-09-15 2:21 ` Huang Shijie
` (2 more replies)
0 siblings, 3 replies; 31+ messages in thread
From: Brian Norris @ 2011-09-14 15:44 UTC (permalink / raw)
To: Huang Shijie
Cc: linux, David.Woodhouse, dedekind1, Huang Shijie, linux-mtd,
Florian Fainelli, linux-arm-kernel
Hi,
I see nothing has happened with this thread recently. It doesn't
deserve to die though.
On Thu, Mar 31, 2011 at 10:17 AM, Huang Shijie <shijie8@gmail.com> wrote:
> 2011/3/31 Artem Bityutskiy <dedekind1@gmail.com>:
>>> > If you have new chips to support in the future, you should add them in
>>> > drivers/mtd/nand/nand_ids.c and not keep this file.
>>> >
>>> The data structure nand_flash_dev{} does not contain enough information.
>>> So I want to the nand_device_info{} to replace it in future.
>>
>> Just add this information, if it is of generic nature (like SLC/MLC
>> flag, required ECC strength, etc).
Are SLC/MLC and ECC strength necessary to track? I don't see a good
benefit to cost ratio of trying to detect ECC strength especially,
since the levels specified in data sheets vary without much pattern
and nobody provides a way for decoding this from ID; do you really
want to have to make separate chip entries for every single chip that
comes around?
>>> > I still do not understand why this would be needed, is it because the generic
>>> > code does not provide enough informations for your driver?
>>> >
>>> yes.
>>>
>>> IMHO, the generic code is somehow trapped in a wrong way. :(
I may agree, but can you be more specific on the trap?
>>> Paring the id bytes is not sufficient to get all the information you
>>> need which is faced by me.
What's an alternative to "paring the id bytes"?
>>> What's more, I think the paring code is ugly, see the nand_get_flash_type().
>>
>> You are welcome to fix this. There is _a lot_ of ugly code in MTD
>> because no one loves it. Give it some love :-)
While I agree that a lot of this is ugly, it is mostly a matter of
necessity. NAND manufacturers do not have a standard (ONFI doesn't
really count, since there's basically 1 manufacturer using it), and so
the most "generic" code is to have different code paths for different
manufacturers (often with exceptions to each rule, since even a single
manufacturer changes its standards arbitrarily). Then you find
manufacturers like Toshiba that recently don't have any (published)
pattern at all for detecting OOB size generically.
Thus, it seems to me like we will need some form of the approach
provided by Huang. As I've found, there are some things that just
can't be decoded from the ID these days, so our ID table will need to
be able to track:
* full ID string (not just the 2nd byte "Device ID")
* relevant bad block scanning options
FWIW, we already implement an exception table in our own driver that
includes the above 2 items, for chips that can't be handled with the
table/detection structure as-is. We don't particularly need SLC/MLC
but I don't object to recording it if we can determine it reliably,
and while ECC level could be useful, it is difficult to discover
generically, as I mentioned above.
>>> Why not create a new database which contains all the necessary
>>> information for a nand, and can be easy
>>> find by the id bytes as the keyword?
>>
>> You can create this database by extending/improving/cleaning up the
>> existing code base with a nice series of patches.
>>
> ok. I will try to fix the generic code before my driver is submitted.
What happened to this statement? I see that your driver was submitted,
but no efforts were made for chip detection cleanup. Were you
satisfied with the current detection?
While we're on the subject, I'll direct your attention to this NAND
data table that I've worked on. It should provide a decent summary of
most of the data sheets I have sorted through. It should also show you
that certain things are going to be very hard to detect (e.g., ECC
level). It should also show that while some chips are not supported by
standard code (e.g., weird bad block scanning features that haven't
been supported, non-standard OOB sizes with no given pattern in the
datasheets), the vast majority of the chips I've come across should be
detected properly:
http://linux-mtd.infradead.org/nand-data/nanddata.html
And of course, please contribute to
git://git.infradead.org/mtd-www.git if you have additions or edits for
the table. It's not perfect, but it can help for sorting through
different chips.
Brian
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 3/6] MTD : add the database for the NANDs
2011-09-14 15:44 ` Brian Norris
@ 2011-09-15 2:21 ` Huang Shijie
2011-09-16 8:11 ` Angus CLARK
2011-11-24 3:11 ` Huang Shijie
2 siblings, 0 replies; 31+ messages in thread
From: Huang Shijie @ 2011-09-15 2:21 UTC (permalink / raw)
To: Brian Norris
Cc: linux, David.Woodhouse, dedekind1, linux-mtd, Florian Fainelli,
Huang Shijie, linux-arm-kernel
Hi Brian:
> Hi,
>
> I see nothing has happened with this thread recently. It doesn't
> deserve to die though.
>
> On Thu, Mar 31, 2011 at 10:17 AM, Huang Shijie<shijie8@gmail.com> wrote:
>> 2011/3/31 Artem Bityutskiy<dedekind1@gmail.com>:
>>>>> If you have new chips to support in the future, you should add them in
>>>>> drivers/mtd/nand/nand_ids.c and not keep this file.
>>>>>
>>>> The data structure nand_flash_dev{} does not contain enough information.
>>>> So I want to the nand_device_info{} to replace it in future.
>>> Just add this information, if it is of generic nature (like SLC/MLC
>>> flag, required ECC strength, etc).
> Are SLC/MLC and ECC strength necessary to track? I don't see a good
> benefit to cost ratio of trying to detect ECC strength especially,
> since the levels specified in data sheets vary without much pattern
> and nobody provides a way for decoding this from ID; do you really
> want to have to make separate chip entries for every single chip that
> comes around?
I do not need the SLC/MCL info. But i do need the ECC strength for the BCH.
Currently i compute it myself based on the ECC chunk size to be 512 bytes.
It's ok now.
But the ONFI nand MAYBE has its own requirements, such as some ONFI nand
requires '24-bit ECC per 1080 bytes of data'(see
MT29F64G08CBAAA,MT29F128G08CEAAA).
In this case, setting the ECC chunk size to 512 bytes maybe is not
proper. It's better to
set the ECC chunk size to 1k, and set ECC strength to 24bit.
So, add the ECC strength to nand is worthful ( at least, it's useful for
ONFI nand) .
>>>>> I still do not understand why this would be needed, is it because the generic
>>>>> code does not provide enough informations for your driver?
>>>>>
>>>> yes.
>>>>
>>>> IMHO, the generic code is somehow trapped in a wrong way. :(
> I may agree, but can you be more specific on the trap?
>
I meant the parsing id code is not good.
Maybe i am wrong.
>>>> Paring the id bytes is not sufficient to get all the information you
>>>> need which is faced by me.
> What's an alternative to "paring the id bytes"?
>
I meant the the code can not get sufficient info for ONFI nand.
But the current code can parse out the info for ONFI nand now.
though it does not parse out all the info.
>>>> What's more, I think the paring code is ugly, see the nand_get_flash_type().
>>> You are welcome to fix this. There is _a lot_ of ugly code in MTD
>>> because no one loves it. Give it some love :-)
> While I agree that a lot of this is ugly, it is mostly a matter of
> necessity. NAND manufacturers do not have a standard (ONFI doesn't
> really count, since there's basically 1 manufacturer using it), and so
> the most "generic" code is to have different code paths for different
> manufacturers (often with exceptions to each rule, since even a single
> manufacturer changes its standards arbitrarily). Then you find
> manufacturers like Toshiba that recently don't have any (published)
> pattern at all for detecting OOB size generically.
>
> Thus, it seems to me like we will need some form of the approach
> provided by Huang. As I've found, there are some things that just
> can't be decoded from the ID these days, so our ID table will need to
> be able to track:
> * full ID string (not just the 2nd byte "Device ID")
The same idea as mine. :) I also thought it's better to store all the
ID bytes.
> * relevant bad block scanning options
>
> FWIW, we already implement an exception table in our own driver that
> includes the above 2 items, for chips that can't be handled with the
> table/detection structure as-is. We don't particularly need SLC/MLC
> but I don't object to recording it if we can determine it reliably,
> and while ECC level could be useful, it is difficult to discover
> generically, as I mentioned above.
>
at least the ECC strength is needed.
>>>> Why not create a new database which contains all the necessary
>>>> information for a nand, and can be easy
>>>> find by the id bytes as the keyword?
>>> You can create this database by extending/improving/cleaning up the
>>> existing code base with a nice series of patches.
>>>
>> ok. I will try to fix the generic code before my driver is submitted.
> What happened to this statement? I see that your driver was submitted,
> but no efforts were made for chip detection cleanup. Were you
> satisfied with the current detection?
I am not satisfied with the current code.
I wish I could add the code to parsing out the ECC strength of ONFI,
and something else.
But I have no time to do this. :(
feel bad.
> While we're on the subject, I'll direct your attention to this NAND
> data table that I've worked on. It should provide a decent summary of
> most of the data sheets I have sorted through. It should also show you
> that certain things are going to be very hard to detect (e.g., ECC
only the ONFI nand's ECC strength is useful now.
You can ignore the normal NANDs, i can compute it myself.
> level). It should also show that while some chips are not supported by
> standard code (e.g., weird bad block scanning features that haven't
> been supported, non-standard OOB sizes with no given pattern in the
> datasheets), the vast majority of the chips I've come across should be
> detected properly:
>
> http://linux-mtd.infradead.org/nand-data/nanddata.html
>
very good!
Huang Shijie
> And of course, please contribute to
> git://git.infradead.org/mtd-www.git if you have additions or edits for
> the table. It's not perfect, but it can help for sorting through
> different chips.
>
> Brian
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 3/6] MTD : add the database for the NANDs
2011-09-14 15:44 ` Brian Norris
2011-09-15 2:21 ` Huang Shijie
@ 2011-09-16 8:11 ` Angus CLARK
2011-11-21 22:18 ` Brian Norris
2011-11-24 3:11 ` Huang Shijie
2 siblings, 1 reply; 31+ messages in thread
From: Angus CLARK @ 2011-09-16 8:11 UTC (permalink / raw)
To: linux-mtd; +Cc: Huang Shijie, Brian Norris, Huang Shijie
Hi Brian, Huang,
Sorry for the long email, but this topic also interests me.
On 09/14/2011 04:44 PM, Brian Norris wrote:
> I see nothing has happened with this thread recently. It doesn't
> deserve to die though.
Having played around with the nand_ids.c and nand_get_flash_type(), I
also think the approach is in need of a bit of an overhaul. The code is
getting increasingly difficult to follow, given the growing number of
non-standard decoding exceptions.
My first attempt was rather similar to Huang's -- using a static table
of READIDs and extended device properties. However, this also gets
rather complicated, and again needs to handle special cases. For
example, early revisions of a NAND device often include 'don't care'
bytes in the READID, or even just shorter READIDs. We could add a
"matching-mask" to the table, and enforce some ordering to the binding
process (e.g. bind against the first match in the table, or perhaps the
most-specific match in the table?), but the semantics of the
table-ordering is difficult to enforce, especially when new devices are
added later. Using a static table also has other disadvantages, such as
size and the need to continually update as new devices emerge (my list
is now over 300 devices!).
I ended up refactoring the nand_get_flash_type() code, according to 3
basic schemes:
'ID 2' : extract properties from nand_flash_ids[]. For 2-byte IDs, or
where device ID gives a non-zero page-size (particularly SP devices).
'Extended ID': decode properties from ID string where possible, falling
back to nand_flash_ids[]. For 3/4/5-byte IDs.
'ID 6' : decode properties from ID string where possible,
falling back to nand_flash_ids[]. For 6-byte IDs.
The refactoring was primarily aimed at simplifying the way in which
decoding exceptions could be accommodated.
I have tested the code on the all the devices found in Brian's most
excellent table:
> http://linux-mtd.infradead.org/nand-data/nanddata.html
with the following exceptions:
- ONFI-only devices: decode not possible using READID
- Multi-CS devices: probe must be repeated on each CS
- Toshiba devices: difficultly in acquiring the datasheets and the full
READID.
I have also added a few more devices and columns to the table (#CS,
#LUNs, #RBn) which I hope to submit shortly.
I was working on a non-standard NAND driver at the time, which made
little use of nand_base.c, and on an older 2.6.32 tree. However, if
there is sufficient interest, I am happy at having a go at updating
nand_get_flash_type() on mtd-2.6.
Let me know if you think this might be useful. Perhaps posting the
standalone test code I used on nanddata.html (actually a csv version of
the table!) would be a good start?
Cheers,
Angus
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 3/6] MTD : add the database for the NANDs
2011-09-16 8:11 ` Angus CLARK
@ 2011-11-21 22:18 ` Brian Norris
2011-12-06 12:06 ` Angus CLARK
0 siblings, 1 reply; 31+ messages in thread
From: Brian Norris @ 2011-11-21 22:18 UTC (permalink / raw)
To: Angus CLARK
Cc: Huang Shijie, Florian Fainelli, linux-mtd, Artem Bityutskiy,
Huang Shijie
Hi Huang, Angus (and anyone else interested in NAND ID decoding),
I have some responses to both Huang and Angus.
Huang:
On Wed, Sep 14, 2011 at 7:21 PM, Huang Shijie <b32955@freescale.com> wrote:
> I do not need the SLC/MCL info. But i do need the ECC strength for the BCH.
> Currently i compute it myself based on the ECC chunk size to be 512 bytes.
> It's ok now.
...
> So, add the ECC strength to nand is worthful ( at least, it's useful for
> ONFI nand) .
For ONFI NAND, you can pull information from the ONFI parameter page
(found in chip->onfi_params.ecc_bits) plus you need to read and decode
the ECC information block. That's up to you to code and submit,
though, which you haven't taken the time to do so far.
>> Thus, it seems to me like we will need some form of the approach
>> provided by Huang. As I've found, there are some things that just
>> can't be decoded from the ID these days, so our ID table will need to
>> be able to track:
>> * full ID string (not just the 2nd byte "Device ID")
>
> The same idea as mine. :) I also thought it's better to store all the ID
> bytes.
We cannot store all the strings for all chips. I think Angus has a
little better of an idea, discussed below.
Angus:
On Fri, Sep 16, 2011 at 1:11 AM, Angus CLARK <angus.clark@st.com> wrote:
> On 09/14/2011 04:44 PM, Brian Norris wrote:
>> I see nothing has happened with this thread recently. It doesn't
>> deserve to die though.
>
> Having played around with the nand_ids.c and nand_get_flash_type(), I
> also think the approach is in need of a bit of an overhaul. The code is
> getting increasingly difficult to follow, given the growing number of
> non-standard decoding exceptions.
Personally, I've spent a lot of time verifying and using this code, so
I don't have a particular problem with its difficulty. But if there
are real improvements that are coupled with some reorganization for
clarity, then I'm fine with it.
> My first attempt was rather similar to Huang's -- using a static table
> of READIDs and extended device properties.
We cannot maintain a full static table of all chips.
> We could add a
> "matching-mask" to the table, and enforce some ordering to the binding
> process (e.g. bind against the first match in the table, or perhaps the
> most-specific match in the table?), but the semantics of the
> table-ordering is difficult to enforce, especially when new devices are
> added later.
I think it'd be easy enough to order chips in "specificity" order; for
instance, divide the table (via comments) into 6-byte, 5-byte, 4-byte,
2-byte, etc. strings (similar to the current nand_ids.c table, where
we section off the 256 Mbit, 512 Mbit, etc.)
> Using a static table also has other disadvantages, such as
> size and the need to continually update as new devices emerge (my list
> is now over 300 devices!).
This is the key reason for the code as it stands. We try to write
rules that limit the number of exceptions and prevent having to
describe each and every device in a table. This is not possible for
some chips/manufacturers, however, when they make no attempt to
provide a pattern to their ID strings.
> I ended up refactoring the nand_get_flash_type() code, according to 3
> basic schemes:
>
> 'ID 2' : extract properties from nand_flash_ids[]. For 2-byte IDs, or
> where device ID gives a non-zero page-size (particularly SP devices).
>
> 'Extended ID': decode properties from ID string where possible, falling
> back to nand_flash_ids[]. For 3/4/5-byte IDs.
>
> 'ID 6' : decode properties from ID string where possible,
> falling back to nand_flash_ids[]. For 6-byte IDs.
As I see it, the only addition is the "ID 6" detection, correct? I
think this is a good start, but it could use more flexibility than
just a 6-byte string. Some 'exceptions' could have shorter or longer
known strings. Perhaps this is where we can use the masking approach
from above.
> I have also added a few more devices and columns to the table (#CS,
> #LUNs, #RBn) which I hope to submit shortly.
Might be useful. Patch it against the CSV in mtd-www.git
(nand-data/nanddata.csv) please.
> I was working on a non-standard NAND driver at the time, which made
> little use of nand_base.c, and on an older 2.6.32 tree. However, if
> there is sufficient interest, I am happy at having a go at updating
> nand_get_flash_type() on mtd-2.6.
>
> Let me know if you think this might be useful.
Sure, it could be useful. It might be difficult to get everything
right, but if you have working suggestions, please send patches! I
think it's usually good to use l2-mtd-2.6 these days, since Artem does
most of the day-to-day MTD patch tracking in his git tree.
> Perhaps posting the
> standalone test code I used on nanddata.html (actually a csv version of
> the table!) would be a good start?
Perhaps. If you have an easily testable framework for validating
against the CSV table from mtd-www.git, then it could be useful.
Personally, I've used a combination of spreadsheet formulas and manual
inspection to validate.
Brian
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 3/6] MTD : add the database for the NANDs
2011-09-14 15:44 ` Brian Norris
2011-09-15 2:21 ` Huang Shijie
2011-09-16 8:11 ` Angus CLARK
@ 2011-11-24 3:11 ` Huang Shijie
2 siblings, 0 replies; 31+ messages in thread
From: Huang Shijie @ 2011-11-24 3:11 UTC (permalink / raw)
To: Brian Norris
Cc: linux, David.Woodhouse, dedekind1, linux-mtd, Florian Fainelli,
Huang Shijie, linux-arm-kernel
Hi Brian:
> Hi,
>
> I see nothing has happened with this thread recently. It doesn't
> deserve to die though.
>
> On Thu, Mar 31, 2011 at 10:17 AM, Huang Shijie<shijie8@gmail.com> wrote:
>> 2011/3/31 Artem Bityutskiy<dedekind1@gmail.com>:
>>>>> If you have new chips to support in the future, you should add them in
>>>>> drivers/mtd/nand/nand_ids.c and not keep this file.
>>>>>
>>>> The data structure nand_flash_dev{} does not contain enough information.
>>>> So I want to the nand_device_info{} to replace it in future.
>>> Just add this information, if it is of generic nature (like SLC/MLC
>>> flag, required ECC strength, etc).
> Are SLC/MLC and ECC strength necessary to track? I don't see a good
We do not necessary to track it. For normal nand, I can compute it
myself ,
just as the current driver does; for ONFI nand ,we should parse it out
from the Parameter Page.
It need an extra patch to do this.
> benefit to cost ratio of trying to detect ECC strength especially,
> since the levels specified in data sheets vary without much pattern
> and nobody provides a way for decoding this from ID; do you really
> want to have to make separate chip entries for every single chip that
> comes around?
>
>>>>> I still do not understand why this would be needed, is it because the generic
>>>>> code does not provide enough informations for your driver?
>>>>>
>>>> yes.
>>>>
>>>> IMHO, the generic code is somehow trapped in a wrong way. :(
> I may agree, but can you be more specific on the trap?
>
>>>> Paring the id bytes is not sufficient to get all the information you
>>>> need which is faced by me.
> What's an alternative to "paring the id bytes"?
>
>>>> What's more, I think the paring code is ugly, see the nand_get_flash_type().
>>> You are welcome to fix this. There is _a lot_ of ugly code in MTD
>>> because no one loves it. Give it some love :-)
> While I agree that a lot of this is ugly, it is mostly a matter of
> necessity. NAND manufacturers do not have a standard (ONFI doesn't
> really count, since there's basically 1 manufacturer using it), and so
> the most "generic" code is to have different code paths for different
> manufacturers (often with exceptions to each rule, since even a single
> manufacturer changes its standards arbitrarily). Then you find
> manufacturers like Toshiba that recently don't have any (published)
> pattern at all for detecting OOB size generically.
bad news. I do not have such chip yet, If i have , i will test it, and
change the current MTD code.
> Thus, it seems to me like we will need some form of the approach
> provided by Huang. As I've found, there are some things that just
> can't be decoded from the ID these days, so our ID table will need to
> be able to track:
> * full ID string (not just the 2nd byte "Device ID")
> * relevant bad block scanning options
>
> FWIW, we already implement an exception table in our own driver that
> includes the above 2 items, for chips that can't be handled with the
> table/detection structure as-is. We don't particularly need SLC/MLC
> but I don't object to recording it if we can determine it reliably,
> and while ECC level could be useful, it is difficult to discover
> generically, as I mentioned above.
>
I do not use the SLC/MLC info now.
>>>> Why not create a new database which contains all the necessary
>>>> information for a nand, and can be easy
>>>> find by the id bytes as the keyword?
>>> You can create this database by extending/improving/cleaning up the
>>> existing code base with a nice series of patches.
>>>
>> ok. I will try to fix the generic code before my driver is submitted.
> What happened to this statement? I see that your driver was submitted,
> but no efforts were made for chip detection cleanup. Were you
> satisfied with the current detection?
When i am free, I will change the current code. But i am a little busy
now :(
Best Regards
Huang Shijie
> While we're on the subject, I'll direct your attention to this NAND
> data table that I've worked on. It should provide a decent summary of
> most of the data sheets I have sorted through. It should also show you
> that certain things are going to be very hard to detect (e.g., ECC
> level). It should also show that while some chips are not supported by
> standard code (e.g., weird bad block scanning features that haven't
> been supported, non-standard OOB sizes with no given pattern in the
> datasheets), the vast majority of the chips I've come across should be
> detected properly:
>
> http://linux-mtd.infradead.org/nand-data/nanddata.html
>
> And of course, please contribute to
> git://git.infradead.org/mtd-www.git if you have additions or edits for
> the table. It's not perfect, but it can help for sorting through
> different chips.
>
> Brian
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH V3 3/6] MTD : add the database for the NANDs
2011-11-21 22:18 ` Brian Norris
@ 2011-12-06 12:06 ` Angus CLARK
0 siblings, 0 replies; 31+ messages in thread
From: Angus CLARK @ 2011-12-06 12:06 UTC (permalink / raw)
To: linux-mtd; +Cc: Brian Norris
Hi Brian,
On 11/21/2011 10:18 PM, Brian Norris wrote:
>
>> I have also added a few more devices and columns to the table (#CS,
>> #LUNs, #RBn) which I hope to submit shortly.
>
> Might be useful. Patch it against the CSV in mtd-www.git
> (nand-data/nanddata.csv) please.
>
Just about send the patches to the list...
>> the table!) would be a good start?
>
> Perhaps. If you have an easily testable framework for validating
> against the CSV table from mtd-www.git, then it could be useful.
I will update the test framework to work with the CSV table and post the result
here... probably not until next week now...
Cheers,
Angus
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2011-12-06 12:06 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-03-30 8:40 [PATCH V3 0/6] add the GPMI controller driver for IMX23/IMX28 Huang Shijie
2011-03-30 8:40 ` [PATCH V3 1/6] ARM: add GPMI support for imx23/imx28 Huang Shijie
2011-03-30 8:40 ` [PATCH V3 2/6] dmaengine: change the flags of request_irq() Huang Shijie
2011-03-30 9:03 ` Lothar Waßmann
2011-03-30 9:13 ` Shawn Guo
2011-03-30 9:15 ` Lothar Waßmann
2011-03-30 9:44 ` Huang Shijie
2011-03-31 7:02 ` [PATCH V3 2/6] dmaengine: add interrupt check for GPMI controller Huang Shijie
2011-03-31 8:02 ` Lothar Waßmann
2011-03-31 8:50 ` Huang Shijie
2011-03-31 8:50 ` Lothar Waßmann
2011-03-31 9:08 ` Huang Shijie
2011-03-31 9:34 ` Lothar Waßmann
2011-04-01 3:47 ` Shawn Guo
2011-04-01 4:36 ` Huang Shijie
2011-03-30 8:40 ` [PATCH V3 3/6] MTD : add the database for the NANDs Huang Shijie
2011-03-30 8:46 ` Florian Fainelli
2011-03-30 9:05 ` Huang Shijie
2011-03-30 9:23 ` Florian Fainelli
2011-03-30 9:54 ` Huang Shijie
2011-03-31 10:10 ` Artem Bityutskiy
2011-03-31 14:17 ` Huang Shijie
2011-09-14 15:44 ` Brian Norris
2011-09-15 2:21 ` Huang Shijie
2011-09-16 8:11 ` Angus CLARK
2011-11-21 22:18 ` Brian Norris
2011-12-06 12:06 ` Angus CLARK
2011-11-24 3:11 ` Huang Shijie
2011-03-30 8:40 ` [PATCH V3 4/6] MTD : add the common code for GPMI controller driver Huang Shijie
2011-03-30 8:40 ` [PATCH V3 5/6] MTD: add support for imx23 and imx28 Huang Shijie
2011-03-30 8:40 ` [PATCH V3 6/6] MTD : add GPMI driver in the config and Makefile Huang Shijie
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