From: chenxiang <chenxiang66@hisilicon.com>
To: <js07.lee@samsung.com>, <michael@walle.cc>, <vigneshr@ti.com>
Cc: Xiang Chen <chenxiang66@hisilicon.com>,
john.garry@huawei.com, linux-mtd@lists.infradead.org,
linuxarm@huawei.com, Tudor.Ambarus@microchip.com
Subject: [PATCH] mtd: spi-nor: Enable locking for n25q128a11
Date: Wed, 25 Mar 2020 11:07:43 +0800 [thread overview]
Message-ID: <1585105663-199127-1-git-send-email-chenxiang66@hisilicon.com> (raw)
From: Xiang Chen <chenxiang66@hisilicon.com>
As 4bit block protection pathset for some micron models are merged,
n25q128a11 also uses 4 bit Block Protection scheme, so enable locking
for it. Tested it on n25q128a11, the locking functions work well.
Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com>
---
drivers/mtd/spi-nor/micron-st.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 6c034b9..02c0b53 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -29,7 +29,9 @@ static const struct flash_info st_parts[] = {
{ "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128,
SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256,
- SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+ SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
+ SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256,
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,
--
2.8.1
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next reply other threads:[~2020-03-25 3:12 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-25 3:07 chenxiang [this message]
2020-04-14 1:16 ` [PATCH] mtd: spi-nor: Enable locking for n25q128a11 chenxiang (M)
2020-04-16 10:43 ` Jungseung Lee
2020-04-17 1:06 ` chenxiang (M)
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